From d7f3f91f18de038b69b9ba8cbd6a894437c543b0 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Thu, 30 Jul 2020 10:58:35 -0700 Subject: [PATCH 1/2] implement fast loadmem feature --- docs/Simulation/Software-RTL-Simulation.rst | 23 +++++++++++++++++++++ generators/testchipip | 2 +- sims/firesim | 2 +- variables.mk | 5 +++++ 4 files changed, 30 insertions(+), 2 deletions(-) diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index bdafd60f..93e4dcc6 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -62,6 +62,12 @@ For instance, to run one of the riscv-tools assembly tests. .. Note:: In a VCS simulator, the simulator name will be ``simv-chipyard-RocketConfig`` instead of ``simulator-chipyard-RocketConfig``. +The makefiles have a ``run-binary`` rule that simplifies running the simulation executable. It adds many of the common command line options for you and redirects the output to a file. + +.. code-block:: shell + + make run-binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple + Alternatively, we can run a pre-packaged suite of RISC-V assembly or benchmark tests, by adding the make target ``run-asm-tests`` or ``run-bmark-tests``. For example: @@ -126,6 +132,23 @@ All ``make`` targets that can be applied to the default example, can also be app Finally, in the ``generated-src/<...>--/`` directory resides all of the collateral and Verilog source files for the build/simulation. Specifically, the SoC top-level (``TOP``) Verilog file is denoted with ``*.top.v`` while the ``TestHarness`` file is denoted with ``*.harness.v``. +Fast Memory Loading +------------------- + +The simulator loads the program binary over a simulated serial line. This can be quite slow if there is a lot of static data, so the simulator also allows data to be loaded from a file directly into the DRAM model. + +.. code-block:: shell + + make run-binary BINARY=test.riscv LOADMEM=testdata.hex LOADMEM_ADDR=81000000 + +The ``.hex`` file should be a text file with a hexadecimal number on each line. + +.. code-block:: text + + deadbeef + 0123 + +Each line uses little-endian order, so this file would produce the bytes "ef be ad de 01 23". ``LOADMEM_ADDR`` specifies which address in memory (in hexadecimal) to write the first byte to. The default is 0x81000000. Generating Waveforms ----------------------- diff --git a/generators/testchipip b/generators/testchipip index 8b5c89a5..3366844f 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 8b5c89a5f7120e64a7ac5ce5210165426a58f3de +Subproject commit 3366844f50a7969f1997125c07ce8d00e5494cf0 diff --git a/sims/firesim b/sims/firesim index 8064d880..ec9d615f 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 8064d8808b9c936711361532a95affbfc2fcbdca +Subproject commit ec9d615f6db72684cfee16a2b57f50493b63ca1f diff --git a/variables.mk b/variables.mk index 48da498e..1aa129f3 100644 --- a/variables.mk +++ b/variables.mk @@ -163,7 +163,12 @@ output_dir=$(sim_dir)/output/$(long_name) PERMISSIVE_ON=+permissive PERMISSIVE_OFF=+permissive-off BINARY ?= +LOADMEM ?= +LOADMEM_ADDR ?= 81000000 override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(timeout_cycles) +ifneq ($(LOADMEM),) +override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR) +endif VERBOSE_FLAGS ?= +verbose sim_out_name = $(output_dir)/$(subst $() $(),_,$(notdir $(basename $(BINARY)))) From 813d1fdb9e37391e9a6e9445bedcb7181be74e23 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 3 Aug 2020 16:09:16 -0700 Subject: [PATCH 2/2] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index ec9d615f..b13e7529 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit ec9d615f6db72684cfee16a2b57f50493b63ca1f +Subproject commit b13e75296c44b1f3fa987d15df6a595668842dfe