MultiPort remove random println

GenerateSpec fix so "generate top test" does not rely on side-effects of previous test
GenerateTopSpec fix so it creates needed input file itself, does not rely on other tests to do that
This commit is contained in:
chick
2021-08-10 16:26:11 -07:00
parent 74d5da6f4a
commit 08eba27126
3 changed files with 31 additions and 17 deletions

View File

@@ -316,7 +316,6 @@ class SplitWidth_2rw_differentMasks extends MacroCompilerSpec with HasSRAMGenera
lazy val memMaskGranB = 8 // these generators are run at constructor time
override def generateMemSRAM() = {
println(memMaskGranB)
SRAMMacro(
name = mem_name,
width = memWidth,

View File

@@ -8,7 +8,6 @@ import chisel3.stage.ChiselStage
import firrtl.FileUtils
import org.scalatest.freespec.AnyFreeSpec
import org.scalatest.matchers.must.Matchers.be
import org.scalatest.matchers.should.Matchers
import org.scalatest.matchers.should.Matchers.convertToAnyShouldWrapper
import java.io.{File, PrintWriter}
@@ -60,34 +59,40 @@ class GenerateExampleTester extends MultiIOModule {
}
class GenerateSpec extends AnyFreeSpec {
"generate test data" in {
val targetDir = "test_run_dir/generate_spec_source"
def generateTestData(targetDir: String): Unit = {
FileUtils.makeDirectory(targetDir)
(new ChiselStage()).emitFirrtl(new GenerateExampleTester, Array("--target-dir", targetDir))
new ChiselStage().emitFirrtl(new GenerateExampleTester, Array("--target-dir", targetDir))
val blackBoxInverterText = """
|module BlackBoxInverter(
| input [0:0] in,
| output [0:0] out
|);
| assign out = !in;
|endmodule
|""".stripMargin
val blackBoxInverterText =
"""
|module BlackBoxInverter(
| input [0:0] in,
| output [0:0] out
|);
| assign out = !in;
|endmodule
|""".stripMargin
val printWriter2 = new PrintWriter(new File(s"$targetDir/BlackBoxInverter.v"))
printWriter2.write(blackBoxInverterText)
printWriter2.close()
}
new File(s"$targetDir/GenerateExampleTester.fir").exists() should be (true)
"generate test data" in {
val targetDir = "test_run_dir/generate_spec_source"
generateTestData(targetDir)
new File(s"$targetDir/GenerateExampleTester.fir").exists() should be(true)
}
"generate top test" in {
val sourceDir = "test_run_dir/generate_spec_source"
val targetDir = "test_run_dir/generate_spec"
generateTestData(targetDir)
GenerateTop.main(Array(
"-i", s"$sourceDir/GenerateExampleTester.fir",
"-i", s"$targetDir/GenerateExampleTester.fir",
"-o", s"$targetDir/GenerateExampleTester.v"
))
new File(s"$targetDir/GenerateExampleTester.v").exists() should be (true)

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@@ -2,6 +2,7 @@
package barstools.tapeout.transforms
import chisel3.stage.ChiselStage
import firrtl.FileUtils
import org.scalatest.freespec.AnyFreeSpec
import org.scalatest.matchers.should.Matchers
@@ -11,9 +12,18 @@ import java.io.{ByteArrayOutputStream, File, PrintStream, PrintWriter}
class GenerateTopSpec extends AnyFreeSpec with Matchers {
"Generate top and harness" - {
"should include the following transforms" in {
val targetDir = "test_run_dir/generate_top_and_harness"
FileUtils.makeDirectory(targetDir)
(new ChiselStage).emitChirrtl(new ExampleModuleNeedsResetInverted, Array("--target-dir", targetDir))
val buffer = new ByteArrayOutputStream()
Console.withOut(new PrintStream(buffer)) {
GenerateTopAndHarness.main(Array("-i", "ExampleModuleNeedsResetInverted.fir", "-ll", "info"))
GenerateTopAndHarness.main(
Array(
"-i", s"$targetDir/ExampleModuleNeedsResetInverted.fir",
"-ll", "info"
)
)
}
val output = buffer.toString
output should include("barstools.tapeout.transforms.AddSuffixToModuleNames")