Remove references to ENABLE_YOSYS

2023-12-13 10:07:14 -08:00
parent f882280290
commit 088e9ea45a
6 changed files with 4 additions and 15 deletions
--- a/vlsi/tutorial.mk
+++ b/vlsi/tutorial.mk
@@ -39,7 +39,4 @@ ifeq ($(tutorial),sky130-openroad)
                            example-designs/sky130-openroad-rockettile.yml, )
    VLSI_OBJ_DIR      ?= build-sky130-openroad
    INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
-    # Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time.
-    ENABLE_YOSYS_FLOW  = 1
 endif
-