From 08839930009a6f15f2b3ba73940c243d34750ab6 Mon Sep 17 00:00:00 2001
From: Harrison Liew <harrisonliew@gmail.com>
Date: Wed, 8 Mar 2023 16:11:01 -0800
Subject: [PATCH] model and top reference common modules, need to filter them
 out from sim to avoid module collisions

---
 vlsi/sim.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/vlsi/sim.mk b/vlsi/sim.mk
index 13a7fcc3..1f5b530d 100644
--- a/vlsi/sim.mk
+++ b/vlsi/sim.mk
@@ -10,7 +10,7 @@ $(SIM_CONF): $(sim_common_files)
 	echo "  top_module: $(VLSI_TOP)" >> $@
 	echo "  tb_name: ''" >> $@  # don't specify -top
 	echo "  input_files:" >> $@
-	for x in $$(cat $(MODEL_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) | sort -u) $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \
+	for x in $$(comm -23 <(cat $(MODEL_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) | sort -u) <(sort $(VLSI_RTL))) $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \
 		echo '    - "'$$x'"' >> $@; \
 	done
 	echo "  input_files_meta: 'append'" >> $@