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Bump to chisel3.6

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This commit is contained in:
Jerry Zhao
2023-06-20 17:26:54 -07:00
parent a2502d34de
commit 078bce1323
12 changed files with 22 additions and 33 deletions
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2
fpga/src/main/scala/vc707/TestHarness.scala
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@@ -90,7 +90,7 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators {
val vc707Outer = _outer
val reset = IO(Input(Bool()))
val reset = IO(Input(Bool())).suggestName("reset")
_outer.xdc.addBoardPin(reset, "reset")
val resetIBUF = Module(new IBUF)