wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Bump to chisel3.6

Browse Source
This commit is contained in:
Jerry Zhao
2023-06-20 17:26:54 -07:00
parent a2502d34de
commit 078bce1323
12 changed files with 22 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
fpga/src/main/scala/vc707/TestHarness.scala
View File

@@ -90,7 +90,7 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators {
val vc707Outer = _outer
val reset = IO(Input(Bool()))
val reset = IO(Input(Bool())).suggestName("reset")
_outer.xdc.addBoardPin(reset, "reset")
val resetIBUF = Module(new IBUF)

2
fpga/src/main/scala/vcu118/TestHarness.scala
View File

@@ -93,7 +93,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators {
val vcu118Outer = _outer
val reset = IO(Input(Bool()))
val reset = IO(Input(Bool())).suggestName("reset")
_outer.xdc.addPackagePin(reset, "L19")
_outer.xdc.addIOStandard(reset, "LVCMOS12")