wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Fix spike-cosim causing problems for firesim

Browse Source
This commit is contained in:
Jerry Zhao
2023-02-03 11:27:14 -08:00
parent 2968151d24
commit 071ba76209
3 changed files with 18 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
generators/chipyard/src/main/scala/Cospike.scala
View File

@@ -32,15 +32,19 @@ class CospikeResources(
addResource("/vsrc/cospike.v") addResource("/vsrc/cospike.v")
} }
case object SpikeCosimKey extends Field[Boolean](false)
trait CanHaveSpikeCosim { this: ChipyardSystem => trait CanHaveSpikeCosim { this: ChipyardSystem =>
InModuleBody { if (p(SpikeCosimKey)) {
val isa = tiles.headOption.map(_.isaDTS).getOrElse("") InModuleBody {
val mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)) val isa = tiles.headOption.map(_.isaDTS).getOrElse("")
val mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)) val mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0))
val pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0) val mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0))
val nharts = tiles.size val pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0)
val bootrom = bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse("") val nharts = tiles.size
val resources = Module(new CospikeResources(isa, pmpregions, mem0_base, mem0_size, nharts, bootrom)) val bootrom = bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse("")
val resources = Module(new CospikeResources(isa, pmpregions, mem0_base, mem0_size, nharts, bootrom))
}
} }
} }

1
generators/chipyard/src/main/scala/config/BoomConfigs.scala
View File

@@ -57,6 +57,7 @@ class DromajoBoomConfig extends Config(
class MediumBoomCosimConfig extends Config( class MediumBoomCosimConfig extends Config(
new chipyard.harness.WithCospikeBridge ++ // attach spike-cosim new chipyard.harness.WithCospikeBridge ++ // attach spike-cosim
new chipyard.config.EnableSpikeCosim ++ // enable co-sim
new chipyard.config.WithTraceIO ++ // enable the traceio new chipyard.config.WithTraceIO ++ // enable the traceio
new boom.common.WithNMediumBooms(1) ++ new boom.common.WithNMediumBooms(1) ++
new chipyard.config.AbstractConfig) new chipyard.config.AbstractConfig)

6
generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
View File

@@ -9,7 +9,7 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams
import boom.common.{BoomTileAttachParams} import boom.common.{BoomTileAttachParams}
import cva6.{CVA6TileAttachParams} import cva6.{CVA6TileAttachParams}
import chipyard.{SpikeCosimKey}
import testchipip._ import testchipip._
class WithL2TLBs(entries: Int) extends Config((site, here, up) => { class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
@@ -79,3 +79,7 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => {
)) ))
} }
}) })
class EnableSpikeCosim extends Config((site, here, up) => {
case SpikeCosimKey => true
})