upgrade to latest rocket-chip

This commit is contained in:
Howard Mao
2017-05-25 10:42:19 -07:00
parent a123d82677
commit 062d443863
15 changed files with 112 additions and 100 deletions

View File

@@ -1,11 +1,12 @@
package example
import util.GeneratorApp
import diplomacy.LazyModule
import rocketchip._
import testchipip._
import chisel3._
import config.Parameters
import _root_.util.{HasGeneratorUtilities, ParsedInputNames}
import java.io.File
class TestHarness(implicit val p: Parameters) extends Module {
val io = IO(new Bundle {
@@ -17,11 +18,6 @@ class TestHarness(implicit val p: Parameters) extends Module {
val dut = Module(buildTop(p).module)
val ser = Module(new SimSerialWrapper(p(SerialInterfaceWidth)))
dut.io.debug.map { dbg =>
dbg.req.valid := false.B
dbg.resp.ready := false.B
}
val nMemChannels = p(coreplex.BankedL2Config).nMemoryChannels
val mem = Module(LazyModule(new SimAXIMem(nMemChannels)).module)
mem.io.axi4 <> dut.io.mem_axi4
@@ -29,9 +25,32 @@ class TestHarness(implicit val p: Parameters) extends Module {
io.success := ser.io.exit
}
object Generator extends GeneratorApp {
val longName = names.topModuleProject + "." +
trait ExampleGeneratorApp extends App with HasGeneratorUtilities {
lazy val names = ParsedInputNames(
targetDir = args(0),
topModuleProject = args(1),
topModuleClass = args(2),
configProject = args(3),
configs = args(4))
lazy val config = getConfig(names)
lazy val world = config.toInstance
lazy val params = Parameters.root(world)
lazy val circuit = Driver.elaborate(() =>
Class.forName(names.fullTopModuleClass)
.getConstructor(classOf[Parameters])
.newInstance(params)
.asInstanceOf[Module])
lazy val longName = names.topModuleProject + "." +
names.topModuleClass + "." +
names.configs
def generateFirrtl =
Driver.dumpFirrtl(circuit,
Some(new File(names.targetDir, s"$longName.fir")))
}
object Generator extends ExampleGeneratorApp {
generateFirrtl
}

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@@ -10,9 +10,9 @@ class ExampleTop(implicit p: Parameters) extends BaseTop()(p)
with PeripheryBootROM
with PeripheryZero
with PeripheryCounter
with PeripheryDebug
with HardwiredResetVector
with RocketPlexMaster
with NoDebug
with PeripherySerial {
override lazy val module = new ExampleTopModule(this, () => new ExampleTopBundle(this))
}
@@ -22,7 +22,6 @@ class ExampleTopBundle[+L <: ExampleTop](l: L) extends BaseTopBundle(l)
with PeripheryBootROMBundle
with PeripheryZeroBundle
with PeripheryCounterBundle
with PeripheryDebugBundle
with HardwiredResetVectorBundle
with RocketPlexMasterBundle
with PeripherySerialBundle
@@ -33,7 +32,7 @@ class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](l: L, b: ()
with PeripheryBootROMModule
with PeripheryZeroModule
with PeripheryCounterModule
with PeripheryDebugModule
with HardwiredResetVectorModule
with RocketPlexMasterModule
with NoDebugModule
with PeripherySerialModule

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@@ -1,6 +1,5 @@
package pwm
import util.GeneratorApp
import config.Parameters
import diplomacy.LazyModule
@@ -9,9 +8,6 @@ class TestHarness(q: Parameters) extends example.TestHarness()(q) {
LazyModule(new ExampleTopWithPWM()(p))
}
object Generator extends GeneratorApp {
val longName = names.topModuleProject + "." +
names.topModuleClass + "." +
names.configs
object Generator extends example.ExampleGeneratorApp {
generateFirrtl
}