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[tracegen] Add tracegen support for the BOOM L1D (#362)

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* [tracegen] Add tracegen support for the BOOM L1D

* [tracegen] Split up BOOM Tracegen mixin and shim.

* [ci] Fix tracegen hash for testing
This commit is contained in:
Jerry Zhao
2020-01-23 16:01:32 -08:00
committed by GitHub
parent 1859054f73
commit 05f17f5b99
7 changed files with 301 additions and 7 deletions
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15
generators/tracegen/src/main/scala/System.scala
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@@ -6,12 +6,18 @@ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams}
import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams}
import freechips.rocketchip.subsystem._
case object TraceGenKey extends Field[Seq[TraceGenParams]]
case object BoomTraceGenKey extends Field[Seq[TraceGenParams]](Nil)
case object TraceGenKey extends Field[Seq[TraceGenParams]](Nil)
trait HasTraceGenTiles { this: BaseSubsystem =>
val tiles = p(TraceGenKey).zipWithIndex.map { case (params, i) =>
val rocket_tiles = p(TraceGenKey).zipWithIndex.map { case (params, i) =>
LazyModule(new TraceGenTile(i, params, p))
}
val boom_tiles = p(BoomTraceGenKey).zipWithIndex.map { case (params, i) =>
LazyModule(new BoomTraceGenTile(i, params, p))
}
val tiles = rocket_tiles ++ boom_tiles
tiles.foreach { t =>
sbus.fromTile(None, buffer = BufferParams.default) { t.masterNode }
@@ -26,7 +32,10 @@ trait HasTraceGenTilesModuleImp extends LazyModuleImp {
t.module.constants.hartid := i.U
}
val status = DebugCombiner(outer.tiles.map(_.module.status))
val status = DebugCombiner(
outer.rocket_tiles.map(_.module.status) ++
outer.boom_tiles.map(_.module.status)
)
success := status.finished
}