Fix tracegen target and add to CI
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@@ -138,3 +138,38 @@ class RocketNICF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_Fir
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}
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class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "BaseF1Config_MCRams")
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class RamModelBoomF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimBoomConfig", "BaseF1Config_MCRams")
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abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String)
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extends firesim.TestSuiteCommon with IsFireSimGeneratorLike {
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val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
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lazy val generatorArgs = GeneratorArgs(
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midasFlowKind = "midas",
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targetDir = "generated-src",
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topModuleProject = "firesim.firesim",
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topModuleClass = "FireSimTraceGen",
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targetConfigProject = "firesim.firesim",
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targetConfigs = targetConfig ++ "_WithScalaTestFeatures",
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platformConfigProject = "firesim.firesim",
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platformConfigs = platformConfig)
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// From HasFireSimGeneratorUtilities
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// For the firesim utilities to use the same directory as the test suite
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override lazy val testDir = genDir
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// From TestSuiteCommon
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val targetTuple = generatorArgs.tupleName
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val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}",
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s"TARGET_CONFIG=${generatorArgs.targetConfigs}",
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s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}")
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it should "pass" in {
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assert(make("fsim-tracegen") == 0)
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}
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}
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class FireSimLLCTraceGenTest extends FireSimTraceGenTest(
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"DDR3FRFCFSLLC4MB_FireSimTraceGenConfig", "BaseF1Config")
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class FireSimL2TraceGenTest extends FireSimTraceGenTest(
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"DDR3FRFCFS_FireSimTraceGenL2Config", "BaseF1Config")
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