Fix tracegen target and add to CI

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -18,6 +18,7 @@ import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig}
 import firesim.bridges._
 import firesim.configs.MemModelKey
 import firesim.util.RegisterBridgeBinder
+import tracegen.HasTraceGenTilesModuleImp
 
 class WithTiedOffDebug extends RegisterBridgeBinder({ case target: HasPeripheryDebugModuleImp =>
   target.debug.clockeddmi.foreach({ cdmi =>
@@ -64,6 +65,11 @@ class WithTracerVBridge extends RegisterBridgeBinder({
   case target: HasTraceIOImp => TracerVBridge(target.traceIO)(target.p)
 })
 
+class WithTraceGenBridge extends RegisterBridgeBinder({
+  case target: HasTraceGenTilesModuleImp =>
+    Seq(GroundTestBridge(target.success)(target.p))
+})
+
 // Shorthand to register all of the provided bridges above
 class WithDefaultFireSimBridges extends Config(
   new WithTiedOffDebug ++

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -88,6 +88,7 @@ class WithScalaTestFeatures extends Config((site, here, up) => {
 
 // FASED Config Aliases. This to enable config generation via "_" concatenation
 // which requires that all config classes be defined in the same package
+class DDR3FRFCFS extends FRFCFS16GBQuadRank
 class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB
 
 // L2 Config Aliases. For use with "_" concatenation
@@ -279,6 +280,7 @@ class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
 class FireSimTraceGenConfig extends Config(
   new WithTraceGen(
     List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
+  new WithTraceGenBridge ++
   new FireSimRocketChipConfig)
 
 class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
@@ -316,4 +318,5 @@ class FireSimTraceGenL2Config extends Config(
     nBanks = 4,
     capacityKB = 1024,
     outerLatencyCycles = 50) ++
+  new WithTraceGenBridge ++
   new FireSimRocketChipConfig)

generators/firechip/src/main/scala/Targets.scala

@@ -88,17 +88,20 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends SubsystemModule
 
 class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimNoNICDUT)
 
-class FireSimTraceGen(implicit p: Parameters) extends BaseSubsystem
+class FireSimTraceGenDUT(implicit p: Parameters) extends BaseSubsystem
     with HasHierarchicalBusTopology
     with HasTraceGenTiles
     with CanHaveMasterAXI4MemPort {
   override lazy val module = new FireSimTraceGenModuleImp(this)
 }
 
-class FireSimTraceGenModuleImp(outer: FireSimTraceGen) extends BaseSubsystemModuleImp(outer)
+class FireSimTraceGenModuleImp(outer: FireSimTraceGenDUT) extends BaseSubsystemModuleImp(outer)
     with HasTraceGenTilesModuleImp
     with CanHaveMasterAXI4MemPortModuleImp
 
+class FireSimTraceGen(implicit p: Parameters) extends DefaultFireSimHarness(
+  () => new FireSimTraceGenDUT)
+
 // Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimHarness) to something > 1
 class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT)