Bump rocketchip to latest, chisel to 3.5.2

Remove fork of BusTopologies from rocket-chip

Update generators/chipyard/src/main/scala/config/AbstractConfig.scala

Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>

generators/firechip/src/main/scala/FireSim.scala

@@ -262,9 +262,7 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessSigna
     // instantiation of the dut, otherwise the initial instance will be
     // reused across each node
     import freechips.rocketchip.subsystem.AsyncClockGroupsKey
-    val lazyModule = LazyModule(p(BuildTop)(p.alterPartial({
-      case AsyncClockGroupsKey => p(AsyncClockGroupsKey).copy
-    })))
+    val lazyModule = LazyModule(p(BuildTop)(p))
     val module = Module(lazyModule.module)
 
     lazyModule match { case d: HasIOBinders =>