Rename Config Mixins to Fragments (#451)

* [docs] rename config mixins -> fragments [ci skip] * [docs] cleanup naming | link similar sections [ci skip] * [boom] bump for mixin rename [ci skip] * [docs] cleanup capitalization [ci skip] * [docs] consistent config fragment naming [ci skip] * [boom] bump boom for documentation changes [ci skip] * [docs] update source comments [ci skip] * [docs] fix last config fragment name [ci skip] Co-Authored-By: alonamid <alonamid@eecs.berkeley.edu> Co-authored-by: alonamid <alonamid@eecs.berkeley.edu>
2020-02-27 09:31:08 -08:00
parent b6faed283a
commit 01238c8b7a
22 changed files with 91 additions and 93 deletions
--- a/generators/chipyard/src/main/scala/ConfigFragments.scala
+++ b/generators/chipyard/src/main/scala/ConfigFragments.scala
@@ -0,0 +1,140 @@
+package chipyard.config
+
+import chisel3._
+import chisel3.util.{log2Up}
+
+import freechips.rocketchip.config.{Field, Parameters, Config}
+import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, CacheBlockBytes}
+import freechips.rocketchip.diplomacy.{LazyModule, ValName}
+import freechips.rocketchip.devices.tilelink.BootROMParams
+import freechips.rocketchip.devices.debug.{Debug}
+import freechips.rocketchip.tile.{XLen, BuildRoCC, TileKey, LazyRoCC, RocketTileParams, MaxHartIdBits}
+import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}
+import freechips.rocketchip.util.{AsyncResetReg}
+
+import boom.common.{BoomTilesKey}
+
+import testchipip._
+
+import hwacha.{Hwacha}
+
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.uart._
+
+import chipyard.{BuildTop}
+
+/**
+ * TODO: Why do we need this?
+ */
+object ConfigValName {
+  implicit val valName = ValName("TestHarness")
+}
+import ConfigValName._
+
+// -----------------------
+// Common Config Fragments
+// -----------------------
+
+class WithBootROM extends Config((site, here, up) => {
+  case BootROMParams => BootROMParams(
+    contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")
+})
+
+// DOC include start: gpio config fragment
+class WithGPIO extends Config((site, here, up) => {
+  case PeripheryGPIOKey => Seq(
+    GPIOParams(address = 0x10012000, width = 4, includeIOF = false))
+})
+// DOC include end: gpio config fragment
+
+class WithUART extends Config((site, here, up) => {
+  case PeripheryUARTKey => Seq(
+    UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256))
+})
+
+class WithNoGPIO extends Config((site, here, up) => {
+  case PeripheryGPIOKey => Seq()
+})
+
+class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
+  case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy(
+    core = tile.core.copy(nL2TLBEntries = entries)
+  ))
+  case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(
+    core = tile.core.copy(nL2TLBEntries = entries)
+  ))
+})
+
+class WithTracegenTop extends Config((site, here, up) => {
+  case BuildTop => (p: Parameters) => Module(LazyModule(new tracegen.TraceGenSystem()(p)).suggestName("Top").module)
+})
+
+
+// ------------------
+// Multi-RoCC Support
+// ------------------
+
+/**
+ * Map from a hartId to a particular RoCC accelerator
+ */
+case object MultiRoCCKey extends Field[Map[Int, Seq[Parameters => LazyRoCC]]](Map.empty[Int, Seq[Parameters => LazyRoCC]])
+
+/**
+ * Config fragment to enable different RoCCs based on the hartId
+ */
+class WithMultiRoCC extends Config((site, here, up) => {
+  case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).hartId, Nil)
+})
+
+/**
+ * Config fragment to add Hwachas to cores based on hart
+ *
+ * For ex:
+ *   Core 0, 1, 2, 3 have been defined earlier
+ *     with hartIds of 0, 1, 2, 3 respectively
+ *   And you call WithMultiRoCCHwacha(0,1)
+ *   Then Core 0 and 1 will get a Hwacha
+ *
+ * @param harts harts to specify which will get a Hwacha
+ */
+class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => {
+  case MultiRoCCKey => {
+    require(harts.max <= ((up(RocketTilesKey, site).length + up(BoomTilesKey, site).length) - 1))
+    up(MultiRoCCKey, site) ++ harts.distinct.map{ i =>
+      (i -> Seq((p: Parameters) => {
+        LazyModule(new Hwacha()(p)).suggestName("hwacha")
+      }))
+    }
+  }
+})
+
+
+/**
+ * Config fragment to add a small Rocket core to the system as a "control" core.
+ * Used as an example of a PMU core.
+ */
+class WithControlCore extends Config((site, here, up) => {
+  case RocketTilesKey => up(RocketTilesKey, site) :+
+    RocketTileParams(
+      core = RocketCoreParams(
+        useVM = false,
+        fpu = None,
+        mulDiv = Some(MulDivParams(mulUnroll = 8))),
+      btb = None,
+      dcache = Some(DCacheParams(
+        rowBits = site(SystemBusKey).beatBits,
+        nSets = 64,
+        nWays = 1,
+        nTLBEntries = 4,
+        nMSHRs = 0,
+        blockBytes = site(CacheBlockBytes))),
+      icache = Some(ICacheParams(
+        rowBits = site(SystemBusKey).beatBits,
+        nSets = 64,
+        nWays = 1,
+        nTLBEntries = 4,
+        blockBytes = site(CacheBlockBytes))),
+      hartId = up(RocketTilesKey, site).size + up(BoomTilesKey, site).size
+    )
+  case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1)
+})