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Rename Config Mixins to Fragments (#451)

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* [docs] rename config mixins -> fragments [ci skip]

* [docs] cleanup naming | link similar sections [ci skip]

* [boom] bump for mixin rename [ci skip]

* [docs] cleanup capitalization [ci skip]

* [docs] consistent config fragment naming [ci skip]

* [boom] bump boom for documentation changes [ci skip]

* [docs] update source comments [ci skip]

* [docs] fix last config fragment name [ci skip]

Co-Authored-By: alonamid <alonamid@eecs.berkeley.edu>

Co-authored-by: alonamid <alonamid@eecs.berkeley.edu>
This commit is contained in:
Abraham Gonzalez
2020-02-27 09:31:08 -08:00
committed by GitHub
parent b6faed283a
commit 01238c8b7a
22 changed files with 91 additions and 93 deletions
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10
docs/Customization/Memory-Hierarchy.rst
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@@ -12,8 +12,8 @@ uses 16 KiB, 4-way set-associative instruction and data caches. However,
if you use the ``WithNMedCores`` or ``WithNSmallCores`` configurations, you can
configure 4 KiB direct-mapped caches for L1I and L1D.
If you only want to change the size or associativity, there are configuration
mixins for those too. See :ref:`Mixins` for how to add these to a custom ``Config``
If you only want to change the size or associativity, there are config
fragments for those too. See :ref:`Config Fragments` for how to add these to a custom ``Config``.
.. code-block:: scala
@@ -41,7 +41,7 @@ number of channels and number of banks to 0.
The SiFive L2 Cache
-------------------
The default RocketConfig provided in the Chipyard example project uses SiFive's
The default ``RocketConfig`` provided in the Chipyard example project uses SiFive's
InclusiveCache generator to produce a shared L2 cache. In the default
configuration, the L2 uses a single cache bank with 512 KiB capacity and 8-way
set-associativity. However, you can change these parameters to obtain your
@@ -58,11 +58,11 @@ If you do not want to use the L2 cache (say, for a resource-limited embedded
design), you can create a configuration without it. Instead of using the L2
cache, you will instead use RocketChip's TileLink broadcast hub.
To make such a configuration, you can just copy the definition of
``RocketConfig`` but omit the ``WithInclusiveCache`` mixin from the
``RocketConfig`` but omit the ``WithInclusiveCache`` config fragment from the
list of included mixims.
If you want to reduce the resources used even further, you can configure
the Broadcast Hub to use a bufferless design. This mixin is
the Broadcast Hub to use a bufferless design. This config fragment is
``freechips.rocketchip.subsystem.WithBufferlessBroadcastHub``.