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Merge remote-tracking branch 'origin' into symmetric_sertl

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This commit is contained in:
Jerry Zhao
2024-01-01 11:23:31 -08:00
parent 8600640a40 76b7f8d12f
commit 0069d17caf
5 changed files with 90 additions and 19 deletions
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56
fpga/src/main/scala/arty100t/HarnessBinders.scala
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@@ -24,7 +24,17 @@ import testchipip.serdes._
class WithArty100TUARTTSI extends HarnessBinder({
case (th: HasHarnessInstantiators, port: UARTTSIPort, chipId: Int) => {
val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
ath.io_uart_bb.bundle <> port.io.uart
val harnessIO = IO(new UARTPortIO(port.io.uartParams)).suggestName("uart_tsi")
harnessIO <> port.io.uart
val packagePinsWithPackageIOs = Seq(
("A9" , IOPin(harnessIO.rxd)),
("D10", IOPin(harnessIO.txd)))
packagePinsWithPackageIOs foreach { case (pin, io) => {
ath.xdc.addPackagePin(io, pin)
ath.xdc.addIOStandard(io, "LVCMOS33")
ath.xdc.addIOB(io)
} }
ath.other_leds(1) := port.io.dropped
ath.other_leds(9) := port.io.tsi2tl_state(0)
ath.other_leds(10) := port.io.tsi2tl_state(1)
@@ -33,6 +43,7 @@ class WithArty100TUARTTSI extends HarnessBinder({
}
})
class WithArty100TDDRTL extends HarnessBinder({
case (th: HasHarnessInstantiators, port: TLMemPort, chipId: Int) => {
val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
@@ -93,3 +104,46 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
}
}
})
// Maps the UART device to the on-board USB-UART
class WithArty100TUART(rxdPin: String = "A9", txdPin: String = "D10") extends HarnessBinder({
case (th: HasHarnessInstantiators, port: UARTPort) => {
val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
val harnessIO = IO(chiselTypeOf(port.io)).suggestName("uart")
harnessIO <> port.io
val packagePinsWithPackageIOs = Seq(
(rxdPin, IOPin(harnessIO.rxd)),
(txdPin, IOPin(harnessIO.txd)))
packagePinsWithPackageIOs foreach { case (pin, io) => {
ath.xdc.addPackagePin(io, pin)
ath.xdc.addIOStandard(io, "LVCMOS33")
ath.xdc.addIOB(io)
} }
}
})
// Maps the UART device to PMOD JD pins 3/7
class WithArty100TPMODUART extends WithArty100TUART("G2", "F3")
class WithArty100TJTAG extends HarnessBinder({
case (th: HasHarnessInstantiators, port: JTAGPort) => {
val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
val harnessIO = IO(chiselTypeOf(port.io)).suggestName("jtag")
harnessIO <> port.io
ath.sdc.addClock("JTCK", IOPin(harnessIO.TCK), 10)
ath.sdc.addGroup(clocks = Seq("JTCK"))
ath.xdc.clockDedicatedRouteFalse(IOPin(harnessIO.TCK))
val packagePinsWithPackageIOs = Seq(
("F4", IOPin(harnessIO.TCK)),
("D2", IOPin(harnessIO.TMS)),
("E2", IOPin(harnessIO.TDI)),
("D4", IOPin(harnessIO.TDO))
)
packagePinsWithPackageIOs foreach { case (pin, io) => {
ath.xdc.addPackagePin(io, pin)
ath.xdc.addIOStandard(io, "LVCMOS33")
ath.xdc.addPullup(io)
} }
}
})