35 lines
883 B
Scala
35 lines
883 B
Scala
import chisel3._
|
|
|
|
class Clint(p: CoreParams = CoreParams()) extends Module {
|
|
val io = IO(new Bundle {
|
|
val addr = Input(UInt(p.xlen.W))
|
|
val wen = Input(Bool())
|
|
val wdata = Input(UInt(p.xlen.W))
|
|
val ren = Input(Bool())
|
|
val rdata = Output(UInt(p.xlen.W))
|
|
val mipMSIP = Output(Bool())
|
|
val mipMTIP = Output(Bool())
|
|
})
|
|
|
|
val msip = RegInit(false.B)
|
|
val mtime = RegInit(0.U(p.xlen.W))
|
|
val mtimecmp = RegInit(~0.U(p.xlen.W))
|
|
mtime := mtime + 1.U
|
|
|
|
when(io.wen) {
|
|
when(io.addr === "h0".U) {
|
|
msip := io.wdata(0)
|
|
}.elsewhen(io.addr === "h4000".U) {
|
|
mtimecmp := io.wdata
|
|
}.elsewhen(io.addr === "hbff8".U) {
|
|
mtime := io.wdata
|
|
}
|
|
}
|
|
|
|
io.rdata := Mux(io.addr === "h0".U, msip,
|
|
Mux(io.addr === "h4000".U, mtimecmp,
|
|
Mux(io.addr === "hbff8".U, mtime, 0.U)))
|
|
io.mipMSIP := msip
|
|
io.mipMTIP := mtime >= mtimecmp
|
|
}
|