44 lines
1.0 KiB
Makefile
44 lines
1.0 KiB
Makefile
VERILATOR = verilator
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VERILATOR_FLAGS = --cc --exe --build -Wall --trace -Wno-fatal
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VERILATOR_FLAGS += -CFLAGS "-std=c++14 -O2"
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SBT = env SBT_OPTS="-Dsbt.boot.directory=/tmp/sbt-boot -Dsbt.ivy.home=/tmp/sbt-ivy" COURSIER_CACHE=/tmp/coursier-cache sbt
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CHISEL_DIR = ../..
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GENERATED_DIR = $(CHISEL_DIR)/generated
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SRC_FILES = testbench.cpp memory.cpp
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VERILOG_FILES = $(GENERATED_DIR)/Core.sv
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TARGET = obj_dir/VCore
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.PHONY: all verilog compile run clean
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all: compile
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verilog:
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@echo "Generating Verilog from Chisel..."
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cd $(CHISEL_DIR) && $(SBT) "runMain Core"
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compile: verilog
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@echo "Compiling with Verilator..."
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$(VERILATOR) $(VERILATOR_FLAGS) \
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-I$(GENERATED_DIR) \
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--top-module Core \
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-o VCore \
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$(VERILOG_FILES) $(SRC_FILES)
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run: compile
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@if [ -z "$(TEST)" ]; then \
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echo "Usage: make run TEST=<path/to/test>"; \
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exit 1; \
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fi
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./$(TARGET) $(TEST)
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test-simple: compile
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@echo "Running simple test..."
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./$(TARGET) ../../riscv-tests/isa/rv64ui-p-simple
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clean:
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rm -rf obj_dir
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rm -rf $(GENERATED_DIR)
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