16 lines
321 B
Systemverilog
16 lines
321 B
Systemverilog
// Generated by CIRCT firtool-1.139.0
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module WriteBackStage(
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input io_valid,
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input [5:0] io_physDest,
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input [63:0] io_data,
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output io_wen,
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output [5:0] io_waddr,
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output [63:0] io_wdata
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);
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assign io_wen = io_valid;
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assign io_waddr = io_physDest;
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assign io_wdata = io_data;
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endmodule
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