1164 lines
50 KiB
Systemverilog
1164 lines
50 KiB
Systemverilog
// Generated by CIRCT firtool-1.139.0
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module RenameStage(
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input clock,
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reset,
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io_inValid_0,
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io_inValid_1,
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input [63:0] io_in_0_pc,
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input [31:0] io_in_0_inst,
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input [4:0] io_in_0_rs1,
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io_in_0_rs2,
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io_in_0_rd,
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input [2:0] io_in_0_funct3,
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input [63:0] io_in_0_immI,
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io_in_0_immS,
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io_in_0_immB,
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io_in_0_immU,
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io_in_0_immJ,
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input [3:0] io_in_0_opClass,
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input [4:0] io_in_0_aluFn,
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input [2:0] io_in_0_memWidth,
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input io_in_0_memSigned,
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io_in_0_isLoad,
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io_in_0_isStore,
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io_in_0_isBranch,
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io_in_0_isJal,
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io_in_0_isJalr,
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io_in_0_isLui,
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io_in_0_isAuipc,
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io_in_0_isOpImm,
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io_in_0_isWord,
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io_in_0_isSystem,
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io_in_0_isFenceI,
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io_in_0_isEcall,
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io_in_0_isEbreak,
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io_in_0_isMret,
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io_in_0_isSret,
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io_in_0_isSfenceVma,
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io_in_0_isXret,
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io_in_0_isWfi,
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io_in_0_isAmo,
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input [4:0] io_in_0_amoOp,
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input io_in_0_writesRd,
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io_in_0_illegal,
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io_in_0_fetchException,
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input [63:0] io_in_0_fetchExceptionCause,
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io_in_0_fetchExceptionTval,
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io_in_1_pc,
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input [31:0] io_in_1_inst,
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input [4:0] io_in_1_rs1,
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io_in_1_rs2,
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io_in_1_rd,
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input [2:0] io_in_1_funct3,
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input [63:0] io_in_1_immI,
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io_in_1_immS,
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io_in_1_immB,
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io_in_1_immU,
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io_in_1_immJ,
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input [3:0] io_in_1_opClass,
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input [4:0] io_in_1_aluFn,
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input [2:0] io_in_1_memWidth,
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input io_in_1_memSigned,
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io_in_1_isLoad,
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io_in_1_isStore,
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io_in_1_isBranch,
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io_in_1_isJal,
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io_in_1_isJalr,
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io_in_1_isLui,
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io_in_1_isAuipc,
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io_in_1_isOpImm,
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io_in_1_isWord,
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io_in_1_isSystem,
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io_in_1_isFenceI,
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io_in_1_isEcall,
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io_in_1_isEbreak,
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io_in_1_isMret,
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io_in_1_isSret,
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io_in_1_isSfenceVma,
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io_in_1_isXret,
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io_in_1_isWfi,
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io_in_1_isAmo,
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input [4:0] io_in_1_amoOp,
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input io_in_1_writesRd,
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io_in_1_illegal,
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io_in_1_fetchException,
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input [63:0] io_in_1_fetchExceptionCause,
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io_in_1_fetchExceptionTval,
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output io_outValid_0,
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io_outValid_1,
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output [63:0] io_out_0_decoded_pc,
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output [31:0] io_out_0_decoded_inst,
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output [4:0] io_out_0_decoded_rs1,
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io_out_0_decoded_rs2,
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output [2:0] io_out_0_decoded_funct3,
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output [63:0] io_out_0_decoded_immI,
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io_out_0_decoded_immS,
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io_out_0_decoded_immB,
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io_out_0_decoded_immU,
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io_out_0_decoded_immJ,
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output [4:0] io_out_0_decoded_aluFn,
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output [2:0] io_out_0_decoded_memWidth,
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output io_out_0_decoded_memSigned,
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io_out_0_decoded_isLoad,
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io_out_0_decoded_isStore,
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io_out_0_decoded_isBranch,
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io_out_0_decoded_isJal,
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io_out_0_decoded_isJalr,
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io_out_0_decoded_isLui,
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io_out_0_decoded_isAuipc,
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io_out_0_decoded_isOpImm,
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io_out_0_decoded_isWord,
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io_out_0_decoded_isSystem,
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io_out_0_decoded_isFenceI,
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io_out_0_decoded_isEcall,
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io_out_0_decoded_isEbreak,
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io_out_0_decoded_isMret,
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io_out_0_decoded_isSret,
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io_out_0_decoded_isSfenceVma,
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io_out_0_decoded_isXret,
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io_out_0_decoded_isWfi,
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io_out_0_decoded_isAmo,
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output [4:0] io_out_0_decoded_amoOp,
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output io_out_0_decoded_writesRd,
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io_out_0_decoded_illegal,
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io_out_0_decoded_fetchException,
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output [63:0] io_out_0_decoded_fetchExceptionCause,
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io_out_0_decoded_fetchExceptionTval,
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output [5:0] io_out_0_prs1,
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io_out_0_prs2,
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output io_out_0_src1Ready,
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io_out_0_src2Ready,
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output [5:0] io_out_0_prd,
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io_out_0_robIdx,
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output [63:0] io_out_1_decoded_pc,
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output [31:0] io_out_1_decoded_inst,
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output [4:0] io_out_1_decoded_rs1,
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io_out_1_decoded_rs2,
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output [2:0] io_out_1_decoded_funct3,
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output [63:0] io_out_1_decoded_immI,
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io_out_1_decoded_immS,
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io_out_1_decoded_immB,
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io_out_1_decoded_immU,
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io_out_1_decoded_immJ,
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output [4:0] io_out_1_decoded_aluFn,
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output [2:0] io_out_1_decoded_memWidth,
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output io_out_1_decoded_memSigned,
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io_out_1_decoded_isLoad,
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io_out_1_decoded_isStore,
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io_out_1_decoded_isBranch,
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io_out_1_decoded_isJal,
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io_out_1_decoded_isJalr,
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io_out_1_decoded_isLui,
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io_out_1_decoded_isAuipc,
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io_out_1_decoded_isOpImm,
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io_out_1_decoded_isWord,
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io_out_1_decoded_isSystem,
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io_out_1_decoded_isFenceI,
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io_out_1_decoded_isEcall,
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io_out_1_decoded_isEbreak,
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io_out_1_decoded_isMret,
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io_out_1_decoded_isSret,
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io_out_1_decoded_isSfenceVma,
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io_out_1_decoded_isXret,
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io_out_1_decoded_isWfi,
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io_out_1_decoded_isAmo,
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output [4:0] io_out_1_decoded_amoOp,
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output io_out_1_decoded_writesRd,
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io_out_1_decoded_illegal,
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io_out_1_decoded_fetchException,
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output [63:0] io_out_1_decoded_fetchExceptionCause,
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io_out_1_decoded_fetchExceptionTval,
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output [5:0] io_out_1_prs1,
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io_out_1_prs2,
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output io_out_1_src1Ready,
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io_out_1_src2Ready,
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output [5:0] io_out_1_prd,
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io_out_1_robIdx,
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output io_canAccept,
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input io_wbValid_0,
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io_wbValid_1,
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input [5:0] io_wbPhys_0,
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io_wbPhys_1,
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input io_completeValid_0,
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io_completeValid_1,
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input [5:0] io_completeIdx_0,
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io_completeIdx_1,
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input io_completeException_0,
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io_completeException_1,
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input [63:0] io_completeCause_0,
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io_completeCause_1,
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io_completeBadAddr_0,
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io_completeBadAddr_1,
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input io_completeMispredict_0,
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io_completeMispredict_1,
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input [63:0] io_completeRedirectPc_0,
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io_completeRedirectPc_1,
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input io_completeCsrValid_0,
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io_completeCsrValid_1,
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input [11:0] io_completeCsrAddr_0,
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io_completeCsrAddr_1,
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input [2:0] io_completeCsrCmd_0,
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io_completeCsrCmd_1,
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input [63:0] io_completeCsrRs1_0,
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io_completeCsrRs1_1,
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input [4:0] io_completeCsrZimm_0,
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io_completeCsrZimm_1,
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input io_completeFenceI_0,
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io_completeFenceI_1,
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io_completeSfenceVma_0,
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io_completeSfenceVma_1,
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io_completeXret_0,
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io_completeXret_1,
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io_completeXretIsMret_0,
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io_completeXretIsMret_1,
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io_commitReady_0,
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io_commitReady_1,
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output io_commitValid_0,
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io_commitValid_1,
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io_commitEntry_0_valid,
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output [5:0] io_commitEntry_0_robIdx,
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output [63:0] io_commitEntry_0_pc,
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output [4:0] io_commitEntry_0_archDest,
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output io_commitEntry_0_writesDest,
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output [3:0] io_commitEntry_0_opClass,
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output [5:0] io_commitEntry_0_dest,
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io_commitEntry_0_oldDest,
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output io_commitEntry_0_exception,
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output [63:0] io_commitEntry_0_exceptionCause,
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io_commitEntry_0_badAddr,
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output io_commitEntry_0_branchMispredict,
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output [63:0] io_commitEntry_0_redirectPc,
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output io_commitEntry_0_csrValid,
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output [11:0] io_commitEntry_0_csrAddr,
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output [2:0] io_commitEntry_0_csrCmd,
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output [63:0] io_commitEntry_0_csrRs1,
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output [4:0] io_commitEntry_0_csrZimm,
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output io_commitEntry_0_fenceI,
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io_commitEntry_0_sfenceVma,
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io_commitEntry_0_xret,
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io_commitEntry_0_xretIsMret,
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output [5:0] io_commitEntry_1_robIdx,
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output [63:0] io_commitEntry_1_pc,
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output [4:0] io_commitEntry_1_archDest,
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output io_commitEntry_1_writesDest,
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output [3:0] io_commitEntry_1_opClass,
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output [5:0] io_commitEntry_1_dest,
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io_commitEntry_1_oldDest,
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output io_commitEntry_1_exception,
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output [63:0] io_commitEntry_1_exceptionCause,
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io_commitEntry_1_badAddr,
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output io_commitEntry_1_branchMispredict,
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output [63:0] io_commitEntry_1_redirectPc,
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output io_commitEntry_1_csrValid,
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output [11:0] io_commitEntry_1_csrAddr,
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output [2:0] io_commitEntry_1_csrCmd,
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output [63:0] io_commitEntry_1_csrRs1,
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output [4:0] io_commitEntry_1_csrZimm,
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output io_commitEntry_1_fenceI,
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io_commitEntry_1_sfenceVma,
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io_commitEntry_1_xret,
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io_commitEntry_1_xretIsMret,
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input io_commitMapValid_0,
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io_commitMapValid_1,
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input [4:0] io_commitArch_0,
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io_commitArch_1,
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input [5:0] io_commitPhys_0,
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io_commitPhys_1,
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input io_commitFreeOld_0,
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io_commitFreeOld_1,
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input [5:0] io_commitOldPhys_0,
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io_commitOldPhys_1,
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input io_flush
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);
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wire e_1_valid;
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wire e_valid;
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wire _rob_io_canAllocate;
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wire [5:0] _freeList_io_allocPhys_0;
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wire [5:0] _freeList_io_allocPhys_1;
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wire _freeList_io_canAllocate;
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wire [5:0] _table_io_prs1_0;
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wire [5:0] _table_io_prs1_1;
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wire [5:0] _table_io_prs2_0;
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wire [5:0] _table_io_prs2_1;
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wire [5:0] _table_io_oldPrd_0;
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wire [5:0] _table_io_oldPrd_1;
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wire [5:0] _table_io_committedPhys_0;
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wire [5:0] _table_io_committedPhys_1;
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wire [5:0] _table_io_committedPhys_2;
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wire [5:0] _table_io_committedPhys_3;
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wire [5:0] _table_io_committedPhys_4;
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wire [5:0] _table_io_committedPhys_5;
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wire [5:0] _table_io_committedPhys_6;
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wire [5:0] _table_io_committedPhys_7;
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wire [5:0] _table_io_committedPhys_8;
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wire [5:0] _table_io_committedPhys_9;
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wire [5:0] _table_io_committedPhys_10;
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wire [5:0] _table_io_committedPhys_11;
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wire [5:0] _table_io_committedPhys_12;
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wire [5:0] _table_io_committedPhys_13;
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wire [5:0] _table_io_committedPhys_14;
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wire [5:0] _table_io_committedPhys_15;
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wire [5:0] _table_io_committedPhys_16;
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wire [5:0] _table_io_committedPhys_17;
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wire [5:0] _table_io_committedPhys_18;
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wire [5:0] _table_io_committedPhys_19;
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wire [5:0] _table_io_committedPhys_20;
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wire [5:0] _table_io_committedPhys_21;
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wire [5:0] _table_io_committedPhys_22;
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wire [5:0] _table_io_committedPhys_23;
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wire [5:0] _table_io_committedPhys_24;
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wire [5:0] _table_io_committedPhys_25;
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wire [5:0] _table_io_committedPhys_26;
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wire [5:0] _table_io_committedPhys_27;
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wire [5:0] _table_io_committedPhys_28;
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wire [5:0] _table_io_committedPhys_29;
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wire [5:0] _table_io_committedPhys_30;
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wire [5:0] _table_io_committedPhys_31;
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wire table_io_wen_0 = e_valid & io_in_0_writesRd;
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wire table_io_wen_1 = e_1_valid & io_in_1_writesRd;
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wire canRename = _freeList_io_canAllocate & _rob_io_canAllocate;
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reg readyReg_0;
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reg readyReg_1;
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reg readyReg_2;
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reg readyReg_3;
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reg readyReg_4;
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reg readyReg_5;
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reg readyReg_6;
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reg readyReg_7;
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reg readyReg_8;
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reg readyReg_9;
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reg readyReg_10;
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reg readyReg_11;
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reg readyReg_12;
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reg readyReg_13;
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reg readyReg_14;
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reg readyReg_15;
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reg readyReg_16;
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reg readyReg_17;
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reg readyReg_18;
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reg readyReg_19;
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reg readyReg_20;
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reg readyReg_21;
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reg readyReg_22;
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reg readyReg_23;
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reg readyReg_24;
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reg readyReg_25;
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reg readyReg_26;
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reg readyReg_27;
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reg readyReg_28;
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reg readyReg_29;
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reg readyReg_30;
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reg readyReg_31;
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reg readyReg_32;
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reg readyReg_33;
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reg readyReg_34;
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reg readyReg_35;
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reg readyReg_36;
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reg readyReg_37;
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reg readyReg_38;
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reg readyReg_39;
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reg readyReg_40;
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reg readyReg_41;
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reg readyReg_42;
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reg readyReg_43;
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reg readyReg_44;
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reg readyReg_45;
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reg readyReg_46;
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reg readyReg_47;
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reg readyReg_48;
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reg readyReg_49;
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reg readyReg_50;
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reg readyReg_51;
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reg readyReg_52;
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reg readyReg_53;
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reg readyReg_54;
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reg readyReg_55;
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reg readyReg_56;
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reg readyReg_57;
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reg readyReg_58;
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reg readyReg_59;
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reg readyReg_60;
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reg readyReg_61;
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reg readyReg_62;
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reg readyReg_63;
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assign e_valid = io_inValid_0 & canRename;
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assign e_1_valid = io_inValid_1 & canRename;
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wire [5:0] e_dest = io_in_0_writesRd ? _freeList_io_allocPhys_0 : _table_io_oldPrd_0;
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wire [5:0] e_1_dest = io_in_1_writesRd ? _freeList_io_allocPhys_1 : _table_io_oldPrd_1;
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wire [63:0] _GEN =
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{{readyReg_63},
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{readyReg_62},
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{readyReg_61},
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{readyReg_60},
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{readyReg_59},
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{readyReg_58},
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{readyReg_57},
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{readyReg_56},
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{readyReg_55},
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{readyReg_54},
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{readyReg_53},
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{readyReg_52},
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{readyReg_51},
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{readyReg_50},
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{readyReg_49},
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{readyReg_48},
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{readyReg_47},
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{readyReg_46},
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{readyReg_45},
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{readyReg_44},
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{readyReg_43},
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{readyReg_42},
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{readyReg_41},
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{readyReg_40},
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{readyReg_39},
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{readyReg_38},
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{readyReg_37},
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{readyReg_36},
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{readyReg_35},
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{readyReg_34},
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{readyReg_33},
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{readyReg_32},
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{readyReg_31},
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{readyReg_30},
|
|
{readyReg_29},
|
|
{readyReg_28},
|
|
{readyReg_27},
|
|
{readyReg_26},
|
|
{readyReg_25},
|
|
{readyReg_24},
|
|
{readyReg_23},
|
|
{readyReg_22},
|
|
{readyReg_21},
|
|
{readyReg_20},
|
|
{readyReg_19},
|
|
{readyReg_18},
|
|
{readyReg_17},
|
|
{readyReg_16},
|
|
{readyReg_15},
|
|
{readyReg_14},
|
|
{readyReg_13},
|
|
{readyReg_12},
|
|
{readyReg_11},
|
|
{readyReg_10},
|
|
{readyReg_9},
|
|
{readyReg_8},
|
|
{readyReg_7},
|
|
{readyReg_6},
|
|
{readyReg_5},
|
|
{readyReg_4},
|
|
{readyReg_3},
|
|
{readyReg_2},
|
|
{readyReg_1},
|
|
{readyReg_0}};
|
|
always @(posedge clock) begin
|
|
if (reset) begin
|
|
readyReg_0 <= 1'h1;
|
|
readyReg_1 <= 1'h1;
|
|
readyReg_2 <= 1'h1;
|
|
readyReg_3 <= 1'h1;
|
|
readyReg_4 <= 1'h1;
|
|
readyReg_5 <= 1'h1;
|
|
readyReg_6 <= 1'h1;
|
|
readyReg_7 <= 1'h1;
|
|
readyReg_8 <= 1'h1;
|
|
readyReg_9 <= 1'h1;
|
|
readyReg_10 <= 1'h1;
|
|
readyReg_11 <= 1'h1;
|
|
readyReg_12 <= 1'h1;
|
|
readyReg_13 <= 1'h1;
|
|
readyReg_14 <= 1'h1;
|
|
readyReg_15 <= 1'h1;
|
|
readyReg_16 <= 1'h1;
|
|
readyReg_17 <= 1'h1;
|
|
readyReg_18 <= 1'h1;
|
|
readyReg_19 <= 1'h1;
|
|
readyReg_20 <= 1'h1;
|
|
readyReg_21 <= 1'h1;
|
|
readyReg_22 <= 1'h1;
|
|
readyReg_23 <= 1'h1;
|
|
readyReg_24 <= 1'h1;
|
|
readyReg_25 <= 1'h1;
|
|
readyReg_26 <= 1'h1;
|
|
readyReg_27 <= 1'h1;
|
|
readyReg_28 <= 1'h1;
|
|
readyReg_29 <= 1'h1;
|
|
readyReg_30 <= 1'h1;
|
|
readyReg_31 <= 1'h1;
|
|
readyReg_32 <= 1'h1;
|
|
readyReg_33 <= 1'h1;
|
|
readyReg_34 <= 1'h1;
|
|
readyReg_35 <= 1'h1;
|
|
readyReg_36 <= 1'h1;
|
|
readyReg_37 <= 1'h1;
|
|
readyReg_38 <= 1'h1;
|
|
readyReg_39 <= 1'h1;
|
|
readyReg_40 <= 1'h1;
|
|
readyReg_41 <= 1'h1;
|
|
readyReg_42 <= 1'h1;
|
|
readyReg_43 <= 1'h1;
|
|
readyReg_44 <= 1'h1;
|
|
readyReg_45 <= 1'h1;
|
|
readyReg_46 <= 1'h1;
|
|
readyReg_47 <= 1'h1;
|
|
readyReg_48 <= 1'h1;
|
|
readyReg_49 <= 1'h1;
|
|
readyReg_50 <= 1'h1;
|
|
readyReg_51 <= 1'h1;
|
|
readyReg_52 <= 1'h1;
|
|
readyReg_53 <= 1'h1;
|
|
readyReg_54 <= 1'h1;
|
|
readyReg_55 <= 1'h1;
|
|
readyReg_56 <= 1'h1;
|
|
readyReg_57 <= 1'h1;
|
|
readyReg_58 <= 1'h1;
|
|
readyReg_59 <= 1'h1;
|
|
readyReg_60 <= 1'h1;
|
|
readyReg_61 <= 1'h1;
|
|
readyReg_62 <= 1'h1;
|
|
readyReg_63 <= 1'h1;
|
|
end
|
|
else begin
|
|
readyReg_0 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h0)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h0
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h0)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h0 | readyReg_0));
|
|
readyReg_1 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h1)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h1
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h1)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h1 | readyReg_1));
|
|
readyReg_2 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h2)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h2
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h2)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h2 | readyReg_2));
|
|
readyReg_3 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h3)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h3
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h3)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h3 | readyReg_3));
|
|
readyReg_4 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h4)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h4
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h4)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h4 | readyReg_4));
|
|
readyReg_5 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h5)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h5
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h5)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h5 | readyReg_5));
|
|
readyReg_6 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h6)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h6
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h6)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h6 | readyReg_6));
|
|
readyReg_7 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h7)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h7
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h7)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h7 | readyReg_7));
|
|
readyReg_8 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h8)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h8
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h8)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h8 | readyReg_8));
|
|
readyReg_9 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h9)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h9
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h9)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h9 | readyReg_9));
|
|
readyReg_10 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'hA)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'hA
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'hA)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'hA | readyReg_10));
|
|
readyReg_11 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'hB)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'hB
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'hB)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'hB | readyReg_11));
|
|
readyReg_12 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'hC)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'hC
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'hC)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'hC | readyReg_12));
|
|
readyReg_13 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'hD)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'hD
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'hD)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'hD | readyReg_13));
|
|
readyReg_14 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'hE)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'hE
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'hE)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'hE | readyReg_14));
|
|
readyReg_15 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'hF)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'hF
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'hF)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'hF | readyReg_15));
|
|
readyReg_16 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h10)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h10
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h10)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h10 | readyReg_16));
|
|
readyReg_17 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h11)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h11
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h11)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h11 | readyReg_17));
|
|
readyReg_18 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h12)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h12
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h12)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h12 | readyReg_18));
|
|
readyReg_19 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h13)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h13
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h13)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h13 | readyReg_19));
|
|
readyReg_20 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h14)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h14
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h14)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h14 | readyReg_20));
|
|
readyReg_21 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h15)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h15
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h15)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h15 | readyReg_21));
|
|
readyReg_22 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h16)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h16
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h16)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h16 | readyReg_22));
|
|
readyReg_23 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h17)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h17
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h17)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h17 | readyReg_23));
|
|
readyReg_24 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h18)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h18
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h18)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h18 | readyReg_24));
|
|
readyReg_25 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h19)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h19
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h19)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h19 | readyReg_25));
|
|
readyReg_26 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h1A)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h1A
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h1A)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h1A | readyReg_26));
|
|
readyReg_27 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h1B)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h1B
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h1B)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h1B | readyReg_27));
|
|
readyReg_28 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h1C)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h1C
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h1C)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h1C | readyReg_28));
|
|
readyReg_29 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h1D)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h1D
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h1D)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h1D | readyReg_29));
|
|
readyReg_30 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h1E)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h1E
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h1E)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h1E | readyReg_30));
|
|
readyReg_31 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h1F)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h1F
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h1F)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h1F | readyReg_31));
|
|
readyReg_32 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h20)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h20
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h20)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h20 | readyReg_32));
|
|
readyReg_33 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h21)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h21
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h21)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h21 | readyReg_33));
|
|
readyReg_34 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h22)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h22
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h22)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h22 | readyReg_34));
|
|
readyReg_35 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h23)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h23
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h23)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h23 | readyReg_35));
|
|
readyReg_36 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h24)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h24
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h24)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h24 | readyReg_36));
|
|
readyReg_37 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h25)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h25
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h25)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h25 | readyReg_37));
|
|
readyReg_38 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h26)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h26
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h26)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h26 | readyReg_38));
|
|
readyReg_39 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h27)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h27
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h27)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h27 | readyReg_39));
|
|
readyReg_40 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h28)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h28
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h28)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h28 | readyReg_40));
|
|
readyReg_41 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h29)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h29
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h29)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h29 | readyReg_41));
|
|
readyReg_42 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h2A)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h2A
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h2A)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h2A | readyReg_42));
|
|
readyReg_43 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h2B)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h2B
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h2B)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h2B | readyReg_43));
|
|
readyReg_44 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h2C)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h2C
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h2C)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h2C | readyReg_44));
|
|
readyReg_45 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h2D)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h2D
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h2D)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h2D | readyReg_45));
|
|
readyReg_46 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h2E)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h2E
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h2E)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h2E | readyReg_46));
|
|
readyReg_47 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h2F)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h2F
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h2F)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h2F | readyReg_47));
|
|
readyReg_48 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h30)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h30
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h30)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h30 | readyReg_48));
|
|
readyReg_49 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h31)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h31
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h31)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h31 | readyReg_49));
|
|
readyReg_50 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h32)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h32
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h32)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h32 | readyReg_50));
|
|
readyReg_51 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h33)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h33
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h33)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h33 | readyReg_51));
|
|
readyReg_52 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h34)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h34
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h34)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h34 | readyReg_52));
|
|
readyReg_53 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h35)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h35
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h35)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h35 | readyReg_53));
|
|
readyReg_54 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h36)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h36
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h36)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h36 | readyReg_54));
|
|
readyReg_55 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h37)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h37
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h37)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h37 | readyReg_55));
|
|
readyReg_56 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h38)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h38
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h38)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h38 | readyReg_56));
|
|
readyReg_57 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h39)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h39
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h39)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h39 | readyReg_57));
|
|
readyReg_58 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h3A)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h3A
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h3A)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h3A | readyReg_58));
|
|
readyReg_59 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h3B)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h3B
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h3B)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h3B | readyReg_59));
|
|
readyReg_60 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h3C)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h3C
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h3C)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h3C | readyReg_60));
|
|
readyReg_61 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h3D)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h3D
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h3D)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h3D | readyReg_61));
|
|
readyReg_62 <=
|
|
io_flush | ~(table_io_wen_1 & _freeList_io_allocPhys_1 == 6'h3E)
|
|
& (io_wbValid_1 & io_wbPhys_1 == 6'h3E
|
|
| ~(table_io_wen_0 & _freeList_io_allocPhys_0 == 6'h3E)
|
|
& (io_wbValid_0 & io_wbPhys_0 == 6'h3E | readyReg_62));
|
|
readyReg_63 <=
|
|
io_flush | ~(table_io_wen_1 & (&_freeList_io_allocPhys_1))
|
|
& (io_wbValid_1 & (&io_wbPhys_1) | ~(table_io_wen_0 & (&_freeList_io_allocPhys_0))
|
|
& (io_wbValid_0 & (&io_wbPhys_0) | readyReg_63));
|
|
end
|
|
end // always @(posedge)
|
|
RenameTable table_0 (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_rs1_0 (io_in_0_rs1),
|
|
.io_rs1_1 (io_in_1_rs1),
|
|
.io_rs2_0 (io_in_0_rs2),
|
|
.io_rs2_1 (io_in_1_rs2),
|
|
.io_rd_0 (io_in_0_rd),
|
|
.io_rd_1 (io_in_1_rd),
|
|
.io_newPhys_0 (_freeList_io_allocPhys_0),
|
|
.io_newPhys_1 (_freeList_io_allocPhys_1),
|
|
.io_wen_0 (table_io_wen_0),
|
|
.io_wen_1 (table_io_wen_1),
|
|
.io_prs1_0 (_table_io_prs1_0),
|
|
.io_prs1_1 (_table_io_prs1_1),
|
|
.io_prs2_0 (_table_io_prs2_0),
|
|
.io_prs2_1 (_table_io_prs2_1),
|
|
.io_oldPrd_0 (_table_io_oldPrd_0),
|
|
.io_oldPrd_1 (_table_io_oldPrd_1),
|
|
.io_commitWen_0 (io_commitMapValid_0),
|
|
.io_commitWen_1 (io_commitMapValid_1),
|
|
.io_commitRd_0 (io_commitArch_0),
|
|
.io_commitRd_1 (io_commitArch_1),
|
|
.io_commitPhys_0 (io_commitPhys_0),
|
|
.io_commitPhys_1 (io_commitPhys_1),
|
|
.io_recover (io_flush),
|
|
.io_committedPhys_0 (_table_io_committedPhys_0),
|
|
.io_committedPhys_1 (_table_io_committedPhys_1),
|
|
.io_committedPhys_2 (_table_io_committedPhys_2),
|
|
.io_committedPhys_3 (_table_io_committedPhys_3),
|
|
.io_committedPhys_4 (_table_io_committedPhys_4),
|
|
.io_committedPhys_5 (_table_io_committedPhys_5),
|
|
.io_committedPhys_6 (_table_io_committedPhys_6),
|
|
.io_committedPhys_7 (_table_io_committedPhys_7),
|
|
.io_committedPhys_8 (_table_io_committedPhys_8),
|
|
.io_committedPhys_9 (_table_io_committedPhys_9),
|
|
.io_committedPhys_10 (_table_io_committedPhys_10),
|
|
.io_committedPhys_11 (_table_io_committedPhys_11),
|
|
.io_committedPhys_12 (_table_io_committedPhys_12),
|
|
.io_committedPhys_13 (_table_io_committedPhys_13),
|
|
.io_committedPhys_14 (_table_io_committedPhys_14),
|
|
.io_committedPhys_15 (_table_io_committedPhys_15),
|
|
.io_committedPhys_16 (_table_io_committedPhys_16),
|
|
.io_committedPhys_17 (_table_io_committedPhys_17),
|
|
.io_committedPhys_18 (_table_io_committedPhys_18),
|
|
.io_committedPhys_19 (_table_io_committedPhys_19),
|
|
.io_committedPhys_20 (_table_io_committedPhys_20),
|
|
.io_committedPhys_21 (_table_io_committedPhys_21),
|
|
.io_committedPhys_22 (_table_io_committedPhys_22),
|
|
.io_committedPhys_23 (_table_io_committedPhys_23),
|
|
.io_committedPhys_24 (_table_io_committedPhys_24),
|
|
.io_committedPhys_25 (_table_io_committedPhys_25),
|
|
.io_committedPhys_26 (_table_io_committedPhys_26),
|
|
.io_committedPhys_27 (_table_io_committedPhys_27),
|
|
.io_committedPhys_28 (_table_io_committedPhys_28),
|
|
.io_committedPhys_29 (_table_io_committedPhys_29),
|
|
.io_committedPhys_30 (_table_io_committedPhys_30),
|
|
.io_committedPhys_31 (_table_io_committedPhys_31)
|
|
);
|
|
FreeList freeList (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_allocReq_0 (io_inValid_0 & io_in_0_writesRd),
|
|
.io_allocReq_1 (io_inValid_1 & io_in_1_writesRd),
|
|
.io_allocPhys_0 (_freeList_io_allocPhys_0),
|
|
.io_allocPhys_1 (_freeList_io_allocPhys_1),
|
|
.io_canAllocate (_freeList_io_canAllocate),
|
|
.io_freeReq_0 (io_commitFreeOld_0),
|
|
.io_freeReq_1 (io_commitFreeOld_1),
|
|
.io_freePhys_0 (io_commitOldPhys_0),
|
|
.io_freePhys_1 (io_commitOldPhys_1),
|
|
.io_recover (io_flush),
|
|
.io_committedPhys_0 (_table_io_committedPhys_0),
|
|
.io_committedPhys_1 (_table_io_committedPhys_1),
|
|
.io_committedPhys_2 (_table_io_committedPhys_2),
|
|
.io_committedPhys_3 (_table_io_committedPhys_3),
|
|
.io_committedPhys_4 (_table_io_committedPhys_4),
|
|
.io_committedPhys_5 (_table_io_committedPhys_5),
|
|
.io_committedPhys_6 (_table_io_committedPhys_6),
|
|
.io_committedPhys_7 (_table_io_committedPhys_7),
|
|
.io_committedPhys_8 (_table_io_committedPhys_8),
|
|
.io_committedPhys_9 (_table_io_committedPhys_9),
|
|
.io_committedPhys_10 (_table_io_committedPhys_10),
|
|
.io_committedPhys_11 (_table_io_committedPhys_11),
|
|
.io_committedPhys_12 (_table_io_committedPhys_12),
|
|
.io_committedPhys_13 (_table_io_committedPhys_13),
|
|
.io_committedPhys_14 (_table_io_committedPhys_14),
|
|
.io_committedPhys_15 (_table_io_committedPhys_15),
|
|
.io_committedPhys_16 (_table_io_committedPhys_16),
|
|
.io_committedPhys_17 (_table_io_committedPhys_17),
|
|
.io_committedPhys_18 (_table_io_committedPhys_18),
|
|
.io_committedPhys_19 (_table_io_committedPhys_19),
|
|
.io_committedPhys_20 (_table_io_committedPhys_20),
|
|
.io_committedPhys_21 (_table_io_committedPhys_21),
|
|
.io_committedPhys_22 (_table_io_committedPhys_22),
|
|
.io_committedPhys_23 (_table_io_committedPhys_23),
|
|
.io_committedPhys_24 (_table_io_committedPhys_24),
|
|
.io_committedPhys_25 (_table_io_committedPhys_25),
|
|
.io_committedPhys_26 (_table_io_committedPhys_26),
|
|
.io_committedPhys_27 (_table_io_committedPhys_27),
|
|
.io_committedPhys_28 (_table_io_committedPhys_28),
|
|
.io_committedPhys_29 (_table_io_committedPhys_29),
|
|
.io_committedPhys_30 (_table_io_committedPhys_30),
|
|
.io_committedPhys_31 (_table_io_committedPhys_31)
|
|
);
|
|
ROB rob (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_allocateValid_0 (e_valid),
|
|
.io_allocateValid_1 (e_1_valid),
|
|
.io_allocateEntry_0_pc (io_in_0_pc),
|
|
.io_allocateEntry_0_archDest (io_in_0_rd),
|
|
.io_allocateEntry_0_writesDest (io_in_0_writesRd),
|
|
.io_allocateEntry_0_opClass (io_in_0_opClass),
|
|
.io_allocateEntry_0_dest (e_dest),
|
|
.io_allocateEntry_0_oldDest (_table_io_oldPrd_0),
|
|
.io_allocateEntry_0_fenceI (io_in_0_isFenceI),
|
|
.io_allocateEntry_0_sfenceVma (io_in_0_isSfenceVma),
|
|
.io_allocateEntry_0_xret (io_in_0_isXret),
|
|
.io_allocateEntry_0_xretIsMret (io_in_0_isMret),
|
|
.io_allocateEntry_1_pc (io_in_1_pc),
|
|
.io_allocateEntry_1_archDest (io_in_1_rd),
|
|
.io_allocateEntry_1_writesDest (io_in_1_writesRd),
|
|
.io_allocateEntry_1_opClass (io_in_1_opClass),
|
|
.io_allocateEntry_1_dest (e_1_dest),
|
|
.io_allocateEntry_1_oldDest (_table_io_oldPrd_1),
|
|
.io_allocateEntry_1_fenceI (io_in_1_isFenceI),
|
|
.io_allocateEntry_1_sfenceVma (io_in_1_isSfenceVma),
|
|
.io_allocateEntry_1_xret (io_in_1_isXret),
|
|
.io_allocateEntry_1_xretIsMret (io_in_1_isMret),
|
|
.io_allocateIdx_0 (io_out_0_robIdx),
|
|
.io_allocateIdx_1 (io_out_1_robIdx),
|
|
.io_canAllocate (_rob_io_canAllocate),
|
|
.io_completeValid_0 (io_completeValid_0),
|
|
.io_completeValid_1 (io_completeValid_1),
|
|
.io_completeIdx_0 (io_completeIdx_0),
|
|
.io_completeIdx_1 (io_completeIdx_1),
|
|
.io_completeException_0 (io_completeException_0),
|
|
.io_completeException_1 (io_completeException_1),
|
|
.io_completeCause_0 (io_completeCause_0),
|
|
.io_completeCause_1 (io_completeCause_1),
|
|
.io_completeBadAddr_0 (io_completeBadAddr_0),
|
|
.io_completeBadAddr_1 (io_completeBadAddr_1),
|
|
.io_completeMispredict_0 (io_completeMispredict_0),
|
|
.io_completeMispredict_1 (io_completeMispredict_1),
|
|
.io_completeRedirectPc_0 (io_completeRedirectPc_0),
|
|
.io_completeRedirectPc_1 (io_completeRedirectPc_1),
|
|
.io_completeCsrValid_0 (io_completeCsrValid_0),
|
|
.io_completeCsrValid_1 (io_completeCsrValid_1),
|
|
.io_completeCsrAddr_0 (io_completeCsrAddr_0),
|
|
.io_completeCsrAddr_1 (io_completeCsrAddr_1),
|
|
.io_completeCsrCmd_0 (io_completeCsrCmd_0),
|
|
.io_completeCsrCmd_1 (io_completeCsrCmd_1),
|
|
.io_completeCsrRs1_0 (io_completeCsrRs1_0),
|
|
.io_completeCsrRs1_1 (io_completeCsrRs1_1),
|
|
.io_completeCsrZimm_0 (io_completeCsrZimm_0),
|
|
.io_completeCsrZimm_1 (io_completeCsrZimm_1),
|
|
.io_completeFenceI_0 (io_completeFenceI_0),
|
|
.io_completeFenceI_1 (io_completeFenceI_1),
|
|
.io_completeSfenceVma_0 (io_completeSfenceVma_0),
|
|
.io_completeSfenceVma_1 (io_completeSfenceVma_1),
|
|
.io_completeXret_0 (io_completeXret_0),
|
|
.io_completeXret_1 (io_completeXret_1),
|
|
.io_completeXretIsMret_0 (io_completeXretIsMret_0),
|
|
.io_completeXretIsMret_1 (io_completeXretIsMret_1),
|
|
.io_commitValid_0 (io_commitValid_0),
|
|
.io_commitValid_1 (io_commitValid_1),
|
|
.io_commit_0_valid (io_commitEntry_0_valid),
|
|
.io_commit_0_robIdx (io_commitEntry_0_robIdx),
|
|
.io_commit_0_pc (io_commitEntry_0_pc),
|
|
.io_commit_0_archDest (io_commitEntry_0_archDest),
|
|
.io_commit_0_writesDest (io_commitEntry_0_writesDest),
|
|
.io_commit_0_opClass (io_commitEntry_0_opClass),
|
|
.io_commit_0_dest (io_commitEntry_0_dest),
|
|
.io_commit_0_oldDest (io_commitEntry_0_oldDest),
|
|
.io_commit_0_exception (io_commitEntry_0_exception),
|
|
.io_commit_0_exceptionCause (io_commitEntry_0_exceptionCause),
|
|
.io_commit_0_badAddr (io_commitEntry_0_badAddr),
|
|
.io_commit_0_branchMispredict (io_commitEntry_0_branchMispredict),
|
|
.io_commit_0_redirectPc (io_commitEntry_0_redirectPc),
|
|
.io_commit_0_csrValid (io_commitEntry_0_csrValid),
|
|
.io_commit_0_csrAddr (io_commitEntry_0_csrAddr),
|
|
.io_commit_0_csrCmd (io_commitEntry_0_csrCmd),
|
|
.io_commit_0_csrRs1 (io_commitEntry_0_csrRs1),
|
|
.io_commit_0_csrZimm (io_commitEntry_0_csrZimm),
|
|
.io_commit_0_fenceI (io_commitEntry_0_fenceI),
|
|
.io_commit_0_sfenceVma (io_commitEntry_0_sfenceVma),
|
|
.io_commit_0_xret (io_commitEntry_0_xret),
|
|
.io_commit_0_xretIsMret (io_commitEntry_0_xretIsMret),
|
|
.io_commit_1_robIdx (io_commitEntry_1_robIdx),
|
|
.io_commit_1_pc (io_commitEntry_1_pc),
|
|
.io_commit_1_archDest (io_commitEntry_1_archDest),
|
|
.io_commit_1_writesDest (io_commitEntry_1_writesDest),
|
|
.io_commit_1_opClass (io_commitEntry_1_opClass),
|
|
.io_commit_1_dest (io_commitEntry_1_dest),
|
|
.io_commit_1_oldDest (io_commitEntry_1_oldDest),
|
|
.io_commit_1_exception (io_commitEntry_1_exception),
|
|
.io_commit_1_exceptionCause (io_commitEntry_1_exceptionCause),
|
|
.io_commit_1_badAddr (io_commitEntry_1_badAddr),
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.io_commit_1_branchMispredict (io_commitEntry_1_branchMispredict),
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.io_commit_1_redirectPc (io_commitEntry_1_redirectPc),
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.io_commit_1_csrValid (io_commitEntry_1_csrValid),
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.io_commit_1_csrAddr (io_commitEntry_1_csrAddr),
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.io_commit_1_csrCmd (io_commitEntry_1_csrCmd),
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.io_commit_1_csrRs1 (io_commitEntry_1_csrRs1),
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.io_commit_1_csrZimm (io_commitEntry_1_csrZimm),
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.io_commit_1_fenceI (io_commitEntry_1_fenceI),
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.io_commit_1_sfenceVma (io_commitEntry_1_sfenceVma),
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.io_commit_1_xret (io_commitEntry_1_xret),
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.io_commit_1_xretIsMret (io_commitEntry_1_xretIsMret),
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.io_commitReady_0 (io_commitReady_0),
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.io_commitReady_1 (io_commitReady_1),
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.io_flush (io_flush)
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);
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assign io_outValid_0 = e_valid;
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assign io_outValid_1 = e_1_valid;
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assign io_out_0_decoded_pc = io_in_0_pc;
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assign io_out_0_decoded_inst = io_in_0_inst;
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assign io_out_0_decoded_rs1 = io_in_0_rs1;
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assign io_out_0_decoded_rs2 = io_in_0_rs2;
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assign io_out_0_decoded_funct3 = io_in_0_funct3;
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assign io_out_0_decoded_immI = io_in_0_immI;
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assign io_out_0_decoded_immS = io_in_0_immS;
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assign io_out_0_decoded_immB = io_in_0_immB;
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assign io_out_0_decoded_immU = io_in_0_immU;
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assign io_out_0_decoded_immJ = io_in_0_immJ;
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assign io_out_0_decoded_aluFn = io_in_0_aluFn;
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assign io_out_0_decoded_memWidth = io_in_0_memWidth;
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assign io_out_0_decoded_memSigned = io_in_0_memSigned;
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assign io_out_0_decoded_isLoad = io_in_0_isLoad;
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assign io_out_0_decoded_isStore = io_in_0_isStore;
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assign io_out_0_decoded_isBranch = io_in_0_isBranch;
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assign io_out_0_decoded_isJal = io_in_0_isJal;
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assign io_out_0_decoded_isJalr = io_in_0_isJalr;
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assign io_out_0_decoded_isLui = io_in_0_isLui;
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assign io_out_0_decoded_isAuipc = io_in_0_isAuipc;
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assign io_out_0_decoded_isOpImm = io_in_0_isOpImm;
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assign io_out_0_decoded_isWord = io_in_0_isWord;
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assign io_out_0_decoded_isSystem = io_in_0_isSystem;
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assign io_out_0_decoded_isFenceI = io_in_0_isFenceI;
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assign io_out_0_decoded_isEcall = io_in_0_isEcall;
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assign io_out_0_decoded_isEbreak = io_in_0_isEbreak;
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assign io_out_0_decoded_isMret = io_in_0_isMret;
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assign io_out_0_decoded_isSret = io_in_0_isSret;
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assign io_out_0_decoded_isSfenceVma = io_in_0_isSfenceVma;
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assign io_out_0_decoded_isXret = io_in_0_isXret;
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assign io_out_0_decoded_isWfi = io_in_0_isWfi;
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assign io_out_0_decoded_isAmo = io_in_0_isAmo;
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assign io_out_0_decoded_amoOp = io_in_0_amoOp;
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assign io_out_0_decoded_writesRd = io_in_0_writesRd;
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assign io_out_0_decoded_illegal = io_in_0_illegal;
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assign io_out_0_decoded_fetchException = io_in_0_fetchException;
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|
assign io_out_0_decoded_fetchExceptionCause = io_in_0_fetchExceptionCause;
|
|
assign io_out_0_decoded_fetchExceptionTval = io_in_0_fetchExceptionTval;
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|
assign io_out_0_prs1 = _table_io_prs1_0;
|
|
assign io_out_0_prs2 = _table_io_prs2_0;
|
|
assign io_out_0_src1Ready =
|
|
|{io_in_0_rs1 == 5'h0,
|
|
_GEN[_table_io_prs1_0],
|
|
io_wbValid_1 & io_wbPhys_1 == _table_io_prs1_0,
|
|
io_wbValid_0 & io_wbPhys_0 == _table_io_prs1_0};
|
|
assign io_out_0_src2Ready =
|
|
|{io_in_0_rs2 == 5'h0,
|
|
_GEN[_table_io_prs2_0],
|
|
io_wbValid_1 & io_wbPhys_1 == _table_io_prs2_0,
|
|
io_wbValid_0 & io_wbPhys_0 == _table_io_prs2_0};
|
|
assign io_out_0_prd = e_dest;
|
|
assign io_out_1_decoded_pc = io_in_1_pc;
|
|
assign io_out_1_decoded_inst = io_in_1_inst;
|
|
assign io_out_1_decoded_rs1 = io_in_1_rs1;
|
|
assign io_out_1_decoded_rs2 = io_in_1_rs2;
|
|
assign io_out_1_decoded_funct3 = io_in_1_funct3;
|
|
assign io_out_1_decoded_immI = io_in_1_immI;
|
|
assign io_out_1_decoded_immS = io_in_1_immS;
|
|
assign io_out_1_decoded_immB = io_in_1_immB;
|
|
assign io_out_1_decoded_immU = io_in_1_immU;
|
|
assign io_out_1_decoded_immJ = io_in_1_immJ;
|
|
assign io_out_1_decoded_aluFn = io_in_1_aluFn;
|
|
assign io_out_1_decoded_memWidth = io_in_1_memWidth;
|
|
assign io_out_1_decoded_memSigned = io_in_1_memSigned;
|
|
assign io_out_1_decoded_isLoad = io_in_1_isLoad;
|
|
assign io_out_1_decoded_isStore = io_in_1_isStore;
|
|
assign io_out_1_decoded_isBranch = io_in_1_isBranch;
|
|
assign io_out_1_decoded_isJal = io_in_1_isJal;
|
|
assign io_out_1_decoded_isJalr = io_in_1_isJalr;
|
|
assign io_out_1_decoded_isLui = io_in_1_isLui;
|
|
assign io_out_1_decoded_isAuipc = io_in_1_isAuipc;
|
|
assign io_out_1_decoded_isOpImm = io_in_1_isOpImm;
|
|
assign io_out_1_decoded_isWord = io_in_1_isWord;
|
|
assign io_out_1_decoded_isSystem = io_in_1_isSystem;
|
|
assign io_out_1_decoded_isFenceI = io_in_1_isFenceI;
|
|
assign io_out_1_decoded_isEcall = io_in_1_isEcall;
|
|
assign io_out_1_decoded_isEbreak = io_in_1_isEbreak;
|
|
assign io_out_1_decoded_isMret = io_in_1_isMret;
|
|
assign io_out_1_decoded_isSret = io_in_1_isSret;
|
|
assign io_out_1_decoded_isSfenceVma = io_in_1_isSfenceVma;
|
|
assign io_out_1_decoded_isXret = io_in_1_isXret;
|
|
assign io_out_1_decoded_isWfi = io_in_1_isWfi;
|
|
assign io_out_1_decoded_isAmo = io_in_1_isAmo;
|
|
assign io_out_1_decoded_amoOp = io_in_1_amoOp;
|
|
assign io_out_1_decoded_writesRd = io_in_1_writesRd;
|
|
assign io_out_1_decoded_illegal = io_in_1_illegal;
|
|
assign io_out_1_decoded_fetchException = io_in_1_fetchException;
|
|
assign io_out_1_decoded_fetchExceptionCause = io_in_1_fetchExceptionCause;
|
|
assign io_out_1_decoded_fetchExceptionTval = io_in_1_fetchExceptionTval;
|
|
assign io_out_1_prs1 = _table_io_prs1_1;
|
|
assign io_out_1_prs2 = _table_io_prs2_1;
|
|
assign io_out_1_src1Ready =
|
|
io_in_1_rs1 == 5'h0 | ~(table_io_wen_0 & (|io_in_0_rd) & io_in_0_rd == io_in_1_rs1)
|
|
& (|{_GEN[_table_io_prs1_1],
|
|
io_wbValid_1 & io_wbPhys_1 == _table_io_prs1_1,
|
|
io_wbValid_0 & io_wbPhys_0 == _table_io_prs1_1});
|
|
assign io_out_1_src2Ready =
|
|
io_in_1_rs2 == 5'h0 | ~(table_io_wen_0 & (|io_in_0_rd) & io_in_0_rd == io_in_1_rs2)
|
|
& (|{_GEN[_table_io_prs2_1],
|
|
io_wbValid_1 & io_wbPhys_1 == _table_io_prs2_1,
|
|
io_wbValid_0 & io_wbPhys_0 == _table_io_prs2_1});
|
|
assign io_out_1_prd = e_1_dest;
|
|
assign io_canAccept = {1'h0, io_inValid_0} + {1'h0, io_inValid_1} == 2'h0 | canRename;
|
|
endmodule
|
|
|