// Generated by CIRCT firtool-1.139.0 module CSRFile( input clock, reset, io_cmd_valid, input [11:0] io_cmd_addr, input [2:0] io_cmd_cmd, input [63:0] io_cmd_rs1, input [4:0] io_cmd_zimm, input [11:0] io_readAddr, input [1:0] io_currentPriv, output [63:0] io_rdata, output io_readIllegal, input io_trap, input [63:0] io_trapPc, io_trapCause, io_trapTval, input [1:0] io_trapTargetPriv, output [63:0] io_trapVector, input io_xret, io_xretIsMret, output [63:0] io_satp, io_mepc, io_sepc, io_medeleg, io_mstatus ); reg [63:0] cycle; reg [63:0] instret; reg [63:0] mcountinhibit; reg suppressInstretAfterWrite; reg [63:0] mstatus; reg [63:0] mtvecReg; reg [63:0] mscratch; reg [63:0] mepcReg; reg [63:0] mcause; reg [63:0] mtval; reg [63:0] medeleg; reg [63:0] mideleg; reg [63:0] mie; reg [63:0] mip; reg [63:0] mcounteren; reg [63:0] pmpcfg0; reg [63:0] pmpaddr0; reg [63:0] tdata1; reg [63:0] tdata2; reg [63:0] tcontrol; reg [63:0] mnstatus; reg [63:0] scounteren; reg [63:0] stvec; reg [63:0] sepc; reg [63:0] scause; reg [63:0] stval; reg [63:0] sscratch; reg [63:0] satpReg; wire _readAllowed_T_75 = io_readAddr == 12'h300; wire _readAllowed_T_76 = io_readAddr == 12'h301; wire _readAllowed_T_78 = io_readAddr == 12'h302; wire _readAllowed_T_80 = io_readAddr == 12'h303; wire _readAllowed_T_82 = io_readAddr == 12'h304; wire _readAllowed_T_84 = io_readAddr == 12'h305; wire _readAllowed_T_86 = io_readAddr == 12'h306; wire _readAllowed_T_88 = io_readAddr == 12'h340; wire _readAllowed_T_90 = io_readAddr == 12'h341; wire _readAllowed_T_92 = io_readAddr == 12'h342; wire _readAllowed_T_94 = io_readAddr == 12'h343; wire _readAllowed_T_96 = io_readAddr == 12'h344; wire _readAllowed_T_98 = io_readAddr == 12'h3A0; wire _readAllowed_T_100 = io_readAddr == 12'h3B0; wire _readAllowed_T_102 = io_readAddr == 12'h7A0; wire _readAllowed_T_104 = io_readAddr == 12'h7A1; wire _readAllowed_T_106 = io_readAddr == 12'h7A2; wire _readAllowed_T_108 = io_readAddr == 12'h7A5; wire _readAllowed_T_110 = io_readAddr == 12'h744; wire _readAllowed_T_112 = io_readAddr == 12'h320; wire _readAllowed_T_114 = io_readAddr == 12'hB02; wire _readAllowed_T_116 = io_readAddr == 12'hF11; wire _readAllowed_T_118 = io_readAddr == 12'hF12; wire _readAllowed_T_120 = io_readAddr == 12'hF13; wire _readAllowed_T_122 = io_readAddr == 12'hF14; wire _readAllowed_T_125 = io_readAddr == 12'h100; wire _readAllowed_T_126 = io_readAddr == 12'h104; wire _readAllowed_T_128 = io_readAddr == 12'h105; wire _readAllowed_T_130 = io_readAddr == 12'h140; wire _readAllowed_T_132 = io_readAddr == 12'h106; wire _readAllowed_T_134 = io_readAddr == 12'h141; wire _readAllowed_T_136 = io_readAddr == 12'h142; wire _readAllowed_T_138 = io_readAddr == 12'h143; wire _readAllowed_T_140 = io_readAddr == 12'h144; wire _readAllowed_T_142 = io_readAddr == 12'h180; wire _readAllowed_T_69 = io_readAddr == 12'hC00; wire _readAllowed_T_70 = io_readAddr == 12'hC01; wire _readAllowed_T_72 = io_readAddr == 12'hC02; wire readAllowed = (_readAllowed_T_75 | _readAllowed_T_76 | _readAllowed_T_78 | _readAllowed_T_80 | _readAllowed_T_82 | _readAllowed_T_84 | _readAllowed_T_86 | _readAllowed_T_88 | _readAllowed_T_90 | _readAllowed_T_92 | _readAllowed_T_94 | _readAllowed_T_96 | _readAllowed_T_98 | _readAllowed_T_100 | _readAllowed_T_102 | _readAllowed_T_104 | _readAllowed_T_106 | _readAllowed_T_108 | _readAllowed_T_110 | _readAllowed_T_112 | _readAllowed_T_114 | _readAllowed_T_116 | _readAllowed_T_118 | _readAllowed_T_120 | _readAllowed_T_122 | _readAllowed_T_125 | _readAllowed_T_126 | _readAllowed_T_128 | _readAllowed_T_130 | _readAllowed_T_132 | _readAllowed_T_134 | _readAllowed_T_136 | _readAllowed_T_138 | _readAllowed_T_140 | _readAllowed_T_142 | _readAllowed_T_69 | _readAllowed_T_70 | _readAllowed_T_72) & (_readAllowed_T_75 | _readAllowed_T_76 | _readAllowed_T_78 | _readAllowed_T_80 | _readAllowed_T_82 | _readAllowed_T_84 | _readAllowed_T_86 | _readAllowed_T_88 | _readAllowed_T_90 | _readAllowed_T_92 | _readAllowed_T_94 | _readAllowed_T_96 | _readAllowed_T_98 | _readAllowed_T_100 | _readAllowed_T_102 | _readAllowed_T_104 | _readAllowed_T_106 | _readAllowed_T_108 | _readAllowed_T_110 | _readAllowed_T_112 | _readAllowed_T_114 | _readAllowed_T_116 | _readAllowed_T_118 | _readAllowed_T_120 | _readAllowed_T_122 ? (&io_currentPriv) : ~(_readAllowed_T_125 | _readAllowed_T_126 | _readAllowed_T_128 | _readAllowed_T_130 | _readAllowed_T_132 | _readAllowed_T_134 | _readAllowed_T_136 | _readAllowed_T_138 | _readAllowed_T_140 | _readAllowed_T_142) | (|io_currentPriv)); wire _writeAllowed_T_75 = io_cmd_addr == 12'h300; wire _writeAllowed_T_76 = io_cmd_addr == 12'h301; wire _writeAllowed_T_78 = io_cmd_addr == 12'h302; wire _writeAllowed_T_80 = io_cmd_addr == 12'h303; wire _writeAllowed_T_82 = io_cmd_addr == 12'h304; wire _writeAllowed_T_84 = io_cmd_addr == 12'h305; wire _writeAllowed_T_86 = io_cmd_addr == 12'h306; wire _writeAllowed_T_88 = io_cmd_addr == 12'h340; wire _writeAllowed_T_90 = io_cmd_addr == 12'h341; wire _writeAllowed_T_92 = io_cmd_addr == 12'h342; wire _writeAllowed_T_94 = io_cmd_addr == 12'h343; wire _writeAllowed_T_96 = io_cmd_addr == 12'h344; wire _writeAllowed_T_98 = io_cmd_addr == 12'h3A0; wire _writeAllowed_T_100 = io_cmd_addr == 12'h3B0; wire _writeAllowed_T_102 = io_cmd_addr == 12'h7A0; wire _writeAllowed_T_104 = io_cmd_addr == 12'h7A1; wire _writeAllowed_T_106 = io_cmd_addr == 12'h7A2; wire _writeAllowed_T_108 = io_cmd_addr == 12'h7A5; wire _writeAllowed_T_110 = io_cmd_addr == 12'h744; wire _writeAllowed_T_112 = io_cmd_addr == 12'h320; wire _writeAllowed_T_114 = io_cmd_addr == 12'hB02; wire _writeAllowed_T_148 = io_cmd_addr == 12'hF11; wire _writeAllowed_T_149 = io_cmd_addr == 12'hF12; wire _writeAllowed_T_151 = io_cmd_addr == 12'hF13; wire _writeAllowed_T_153 = io_cmd_addr == 12'hF14; wire _writeAllowed_T_125 = io_cmd_addr == 12'h100; wire _writeAllowed_T_126 = io_cmd_addr == 12'h104; wire _writeAllowed_T_128 = io_cmd_addr == 12'h105; wire _writeAllowed_T_130 = io_cmd_addr == 12'h140; wire _writeAllowed_T_132 = io_cmd_addr == 12'h106; wire _writeAllowed_T_134 = io_cmd_addr == 12'h141; wire _writeAllowed_T_136 = io_cmd_addr == 12'h142; wire _writeAllowed_T_138 = io_cmd_addr == 12'h143; wire _writeAllowed_T_140 = io_cmd_addr == 12'h144; wire _writeAllowed_T_142 = io_cmd_addr == 12'h180; wire _writeAllowed_T_155 = io_cmd_addr == 12'hC00; wire _writeAllowed_T_156 = io_cmd_addr == 12'hC01; wire _writeAllowed_T_158 = io_cmd_addr == 12'hC02; wire [63:0] mstatusView = mstatus & 64'hFFFFFFF0FFFFFFFF | 64'hA00000000; wire [63:0] sstatusView = {30'h0, mstatusView[33:1] & 33'h10006F0B1, 1'h0}; wire _GEN = io_cmd_valid & (|io_cmd_cmd) & (_writeAllowed_T_75 | _writeAllowed_T_76 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96 | _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_102 | _writeAllowed_T_104 | _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110 | _writeAllowed_T_112 | _writeAllowed_T_114 | _writeAllowed_T_148 | _writeAllowed_T_149 | _writeAllowed_T_151 | _writeAllowed_T_153 | _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128 | _writeAllowed_T_130 | _writeAllowed_T_132 | _writeAllowed_T_134 | _writeAllowed_T_136 | _writeAllowed_T_138 | _writeAllowed_T_140 | _writeAllowed_T_142 | _writeAllowed_T_155 | _writeAllowed_T_156 | _writeAllowed_T_158) & (_writeAllowed_T_75 | _writeAllowed_T_76 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96 | _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_102 | _writeAllowed_T_104 | _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110 | _writeAllowed_T_112 | _writeAllowed_T_114 | _writeAllowed_T_148 | _writeAllowed_T_149 | _writeAllowed_T_151 | _writeAllowed_T_153 ? (&io_currentPriv) : ~(_writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128 | _writeAllowed_T_130 | _writeAllowed_T_132 | _writeAllowed_T_134 | _writeAllowed_T_136 | _writeAllowed_T_138 | _writeAllowed_T_140 | _writeAllowed_T_142) | (|io_currentPriv)) & ~(_writeAllowed_T_148 | _writeAllowed_T_149 | _writeAllowed_T_151 | _writeAllowed_T_153 | _writeAllowed_T_155 | _writeAllowed_T_156 | _writeAllowed_T_158); wire _GEN_0 = _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96 | _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104 | _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110 | _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128 | _writeAllowed_T_132 | _writeAllowed_T_130 | _writeAllowed_T_134 | _writeAllowed_T_136 | _writeAllowed_T_138 | _writeAllowed_T_140 | _writeAllowed_T_142; wire suppressInstretIncrement = _GEN & ~_GEN_0 & _writeAllowed_T_114; wire trapToS = io_trapTargetPriv == 2'h1; always @(posedge clock) begin if (reset) begin cycle <= 64'h0; instret <= 64'h0; mcountinhibit <= 64'h0; suppressInstretAfterWrite <= 1'h0; mstatus <= 64'h0; mtvecReg <= 64'h0; mscratch <= 64'h0; mepcReg <= 64'h0; mcause <= 64'h0; mtval <= 64'h0; medeleg <= 64'h0; mideleg <= 64'h0; mie <= 64'h0; mip <= 64'h0; mcounteren <= 64'h0; pmpcfg0 <= 64'h0; pmpaddr0 <= 64'h0; tdata1 <= 64'h0; tdata2 <= 64'h0; tcontrol <= 64'h0; mnstatus <= 64'h0; scounteren <= 64'h0; stvec <= 64'h0; sepc <= 64'h0; scause <= 64'h0; stval <= 64'h0; sscratch <= 64'h0; satpReg <= 64'h0; end else begin automatic logic [63:0] writeOld = _writeAllowed_T_75 ? mstatusView : _writeAllowed_T_76 ? 64'h8000000000141101 : _writeAllowed_T_78 ? medeleg : _writeAllowed_T_80 ? mideleg : _writeAllowed_T_82 ? mie : _writeAllowed_T_84 ? mtvecReg : _writeAllowed_T_86 ? mcounteren : _writeAllowed_T_112 ? mcountinhibit : _writeAllowed_T_88 ? mscratch : _writeAllowed_T_90 ? mepcReg : _writeAllowed_T_92 ? mcause : _writeAllowed_T_94 ? mtval : _writeAllowed_T_96 ? mip : _writeAllowed_T_98 ? pmpcfg0 : _writeAllowed_T_100 ? pmpaddr0 : _writeAllowed_T_102 ? 64'h1 : _writeAllowed_T_104 ? tdata1 : _writeAllowed_T_106 ? tdata2 : _writeAllowed_T_108 ? tcontrol : _writeAllowed_T_110 ? mnstatus : _writeAllowed_T_125 ? sstatusView : _writeAllowed_T_126 ? mie & mideleg : _writeAllowed_T_128 ? stvec : _writeAllowed_T_132 ? scounteren : _writeAllowed_T_130 ? sscratch : _writeAllowed_T_134 ? sepc : _writeAllowed_T_136 ? scause : _writeAllowed_T_138 ? stval : _writeAllowed_T_140 ? mip & mideleg : _writeAllowed_T_142 ? satpReg : _writeAllowed_T_148 | _writeAllowed_T_149 | _writeAllowed_T_151 | _writeAllowed_T_153 ? 64'h0 : _writeAllowed_T_114 ? instret : _writeAllowed_T_155 | _writeAllowed_T_156 ? cycle : _writeAllowed_T_158 ? instret : 64'h0; automatic logic [63:0] operand; automatic logic [63:0] _next_T_1; automatic logic [63:0] _next_T_3; automatic logic [3:0][63:0] _GEN_1; automatic logic [63:0] next; operand = io_cmd_cmd[2] ? {59'h0, io_cmd_zimm} : io_cmd_rs1; _next_T_1 = writeOld | operand; _next_T_3 = writeOld & ~operand; _GEN_1 = {{_next_T_3}, {_next_T_1}, {operand}, {writeOld}}; next = _GEN_1[io_cmd_cmd[1:0]]; cycle <= cycle + 64'h1; if (~_GEN | _GEN_0 | ~_writeAllowed_T_114) begin if (mcountinhibit[2] | suppressInstretIncrement | suppressInstretAfterWrite) begin end else instret <= instret + 64'h1; end else instret <= next; if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | ~_writeAllowed_T_112) begin end else mcountinhibit <= {61'h0, next[2], 2'h0}; suppressInstretAfterWrite <= ~suppressInstretAfterWrite & (suppressInstretIncrement | suppressInstretAfterWrite); if (io_trap) begin automatic logic [63:0] _GEN_2 = mstatus[1] ? mstatus | 64'h20 : mstatus & 64'hFFFFFFFFFFFFFFDF; mstatus <= trapToS ? (io_currentPriv == 2'h1 ? _GEN_2 & 64'hFFFFFFFFFFFFFFFD | 64'h100 : _GEN_2 & 64'hFFFFFFFFFFFFFEFD) : (mstatus[3] ? mstatus | 64'h80 : mstatus & 64'hFFFFFFFFFFFFFF7F) & 64'hFFFFFFFFFFFFE7F7 | {51'h0, io_currentPriv, 11'h0}; end else if (io_xret) mstatus <= io_xretIsMret ? ((mstatus[7] ? mstatus | 64'h8 : mstatus & 64'hFFFFFFFFFFFFFFF7) | 64'h80) & 64'hFFFFFFFFFFFFE7FF : ((mstatus[5] ? mstatus | 64'h2 : mstatus & 64'hFFFFFFFFFFFFFFFD) | 64'h20) & 64'hFFFFFFFFFFFFFEFF; else if (_GEN) begin if (_writeAllowed_T_75) begin automatic logic [3:0][63:0] _GEN_3; _GEN_3 = {{_next_T_3}, {_next_T_1}, {operand}, {mstatusView}}; mstatus <= _GEN_3[io_cmd_cmd[1:0]]; end else if (_writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96 | _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104 | _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110 | ~_writeAllowed_T_125) begin end else mstatus <= mstatus & 64'hFFFFFFFDFFF21E9D | {30'h0, next[33:1] & 33'h10006F0B1, 1'h0}; end if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | ~_writeAllowed_T_84) begin end else mtvecReg <= next; if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | ~_writeAllowed_T_88) begin end else mscratch <= next; if (~io_trap | trapToS) begin if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | _writeAllowed_T_88 | ~_writeAllowed_T_90) begin end else mepcReg <= next; if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90 | ~_writeAllowed_T_92) begin end else mcause <= next; if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92 | ~_writeAllowed_T_94) begin end else mtval <= next; end else begin mepcReg <= io_trapPc; mcause <= io_trapCause; mtval <= io_trapTval; end if (~_GEN | _writeAllowed_T_75 | ~_writeAllowed_T_78) begin end else begin automatic logic [3:0][63:0] _GEN_4; _GEN_4 = {{_next_T_3}, {_next_T_1}, {operand}, {_writeAllowed_T_76 ? 64'h8000000000141101 : medeleg}}; medeleg <= _GEN_4[io_cmd_cmd[1:0]]; end if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | ~_writeAllowed_T_80) begin end else begin automatic logic [3:0][63:0] _GEN_5; _GEN_5 = {{_next_T_3}, {_next_T_1}, {operand}, {_writeAllowed_T_75 ? mstatusView : _writeAllowed_T_76 ? 64'h8000000000141101 : _writeAllowed_T_78 ? medeleg : mideleg}}; mideleg <= _GEN_5[io_cmd_cmd[1:0]]; end if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80) begin end else if (_writeAllowed_T_82) mie <= next; else if (_writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96 | _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104 | _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110 | _writeAllowed_T_125 | ~_writeAllowed_T_126) begin end else mie <= mie & ~mideleg | next & mideleg; if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94) begin end else if (_writeAllowed_T_96) mip <= next; else if (_writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104 | _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110 | _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128 | _writeAllowed_T_132 | _writeAllowed_T_130 | _writeAllowed_T_134 | _writeAllowed_T_136 | _writeAllowed_T_138 | ~_writeAllowed_T_140) begin end else mip <= mip & ~mideleg | next & mideleg; if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | ~_writeAllowed_T_86) begin end else mcounteren <= next; if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96 | ~_writeAllowed_T_98) begin end else pmpcfg0 <= next; if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96 | _writeAllowed_T_98 | ~_writeAllowed_T_100) begin end else pmpaddr0 <= next; if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96 | _writeAllowed_T_98 | _writeAllowed_T_100 | ~_writeAllowed_T_104) begin end else tdata1 <= next; if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96 | _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104 | ~_writeAllowed_T_106) begin end else tdata2 <= next; if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96 | _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104 | _writeAllowed_T_106 | ~_writeAllowed_T_108) begin end else tcontrol <= next; if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96 | _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104 | _writeAllowed_T_106 | _writeAllowed_T_108 | ~_writeAllowed_T_110) begin end else mnstatus <= next; if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96 | _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104 | _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110 | _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128 | ~_writeAllowed_T_132) begin end else scounteren <= next; if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96 | _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104 | _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110 | _writeAllowed_T_125 | _writeAllowed_T_126 | ~_writeAllowed_T_128) begin end else stvec <= next; if (io_trap & trapToS) begin sepc <= io_trapPc; scause <= io_trapCause; stval <= io_trapTval; end else begin if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96 | _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104 | _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110 | _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128 | _writeAllowed_T_132 | _writeAllowed_T_130 | ~_writeAllowed_T_134) begin end else sepc <= next; if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96 | _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104 | _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110 | _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128 | _writeAllowed_T_132 | _writeAllowed_T_130 | _writeAllowed_T_134 | ~_writeAllowed_T_136) begin end else scause <= next; if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96 | _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104 | _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110 | _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128 | _writeAllowed_T_132 | _writeAllowed_T_130 | _writeAllowed_T_134 | _writeAllowed_T_136 | ~_writeAllowed_T_138) begin end else stval <= next; end if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96 | _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104 | _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110 | _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128 | _writeAllowed_T_132 | ~_writeAllowed_T_130) begin end else sscratch <= next; if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96 | _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104 | _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110 | _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128 | _writeAllowed_T_132 | _writeAllowed_T_130 | _writeAllowed_T_134 | _writeAllowed_T_136 | _writeAllowed_T_138 | _writeAllowed_T_140 | ~_writeAllowed_T_142) begin end else satpReg <= next; end end // always @(posedge) assign io_rdata = readAllowed ? (_readAllowed_T_75 ? mstatusView : _readAllowed_T_76 ? 64'h8000000000141101 : _readAllowed_T_78 ? medeleg : _readAllowed_T_80 ? mideleg : _readAllowed_T_82 ? mie : _readAllowed_T_84 ? mtvecReg : _readAllowed_T_86 ? mcounteren : _readAllowed_T_112 ? mcountinhibit : _readAllowed_T_88 ? mscratch : _readAllowed_T_90 ? mepcReg : _readAllowed_T_92 ? mcause : _readAllowed_T_94 ? mtval : _readAllowed_T_96 ? mip : _readAllowed_T_98 ? pmpcfg0 : _readAllowed_T_100 ? pmpaddr0 : _readAllowed_T_102 ? 64'h1 : _readAllowed_T_104 ? tdata1 : _readAllowed_T_106 ? tdata2 : _readAllowed_T_108 ? tcontrol : _readAllowed_T_110 ? mnstatus : _readAllowed_T_125 ? sstatusView : _readAllowed_T_126 ? mie & mideleg : _readAllowed_T_128 ? stvec : _readAllowed_T_132 ? scounteren : _readAllowed_T_130 ? sscratch : _readAllowed_T_134 ? sepc : _readAllowed_T_136 ? scause : _readAllowed_T_138 ? stval : _readAllowed_T_140 ? mip & mideleg : _readAllowed_T_142 ? satpReg : _readAllowed_T_116 | _readAllowed_T_118 | _readAllowed_T_120 | _readAllowed_T_122 ? 64'h0 : _readAllowed_T_114 ? instret : _readAllowed_T_69 | _readAllowed_T_70 ? cycle : _readAllowed_T_72 ? instret : 64'h0) : 64'h0; assign io_readIllegal = ~readAllowed; assign io_trapVector = trapToS ? stvec : mtvecReg; assign io_satp = satpReg; assign io_mepc = mepcReg; assign io_sepc = sepc; assign io_medeleg = medeleg; assign io_mstatus = mstatus; endmodule