VERILATOR = verilator
JOBS ?= 8
TRACE ?= 0
FAST ?= 1
SPLIT ?= 20000
SPLIT_CFUNCS ?= 20000
VERILATE_JOBS ?= $(JOBS)
BUILD_JOBS ?= $(JOBS)

VERILATOR_FLAGS = --cc --exe --build --verilate-jobs $(VERILATE_JOBS) --build-jobs $(BUILD_JOBS) -Wall -Wno-fatal
VERILATOR_FLAGS += --output-split $(SPLIT) --output-split-cfuncs $(SPLIT_CFUNCS)
ifeq ($(TRACE),1)
VERILATOR_FLAGS += --trace
endif
ifeq ($(FAST),1)
VERILATOR_FLAGS += -CFLAGS "-std=c++14 -O0"
else
VERILATOR_FLAGS += -CFLAGS "-std=c++14 -O2"
endif
SBT = env SBT_OPTS="-Dsbt.boot.directory=/tmp/sbt-boot -Dsbt.ivy.home=/tmp/sbt-ivy" COURSIER_CACHE=/tmp/coursier-cache sbt

CHISEL_DIR = ../..
OOO ?= 0
ifeq ($(OOO),1)
RUN_MAIN = CoreOoO
GENERATED_DIR = $(CHISEL_DIR)/generated-ooo
else
RUN_MAIN = Core
GENERATED_DIR = $(CHISEL_DIR)/generated
endif
SRC_FILES = testbench.cpp memory.cpp

VERILOG_FILES = $(GENERATED_DIR)/Core.sv
VERILOG_STAMP = $(GENERATED_DIR)/.Core.sv.stamp
SCALA_SOURCES = $(shell find $(CHISEL_DIR)/src/main/scala -name '*.scala')

TARGET = obj_dir/VCore

.PHONY: all verilog compile run clean regenerate

all: compile

verilog: $(VERILOG_STAMP)

$(VERILOG_STAMP): $(SCALA_SOURCES) $(CHISEL_DIR)/build.sbt
	@echo "Generating Verilog from Chisel..."
	cd $(CHISEL_DIR) && $(SBT) "runMain $(RUN_MAIN)"
	@touch $@

$(VERILOG_FILES): $(VERILOG_STAMP)
	@test -f $@

compile: $(VERILOG_FILES)
	@echo "Compiling with Verilator..."
	$(VERILATOR) $(VERILATOR_FLAGS) \
		-I$(GENERATED_DIR) \
		--top-module Core \
		-o VCore \
		$(VERILOG_FILES) $(SRC_FILES)

run: compile
	@if [ -z "$(TEST)" ]; then \
		echo "Usage: make run TEST=<path/to/test>"; \
		exit 1; \
	fi
	./$(TARGET) $(TEST)

test-simple: compile
	@echo "Running simple test..."
	./$(TARGET) ../../riscv-tests/isa/rv64ui-p-simple

regenerate:
	rm -f $(VERILOG_STAMP)
	$(MAKE) verilog OOO=$(OOO)

clean:
	rm -rf obj_dir
	rm -rf $(GENERATED_DIR)