// Generated by CIRCT firtool-1.139.0 module RenameTable( input clock, reset, input [4:0] io_rs1_0, io_rs1_1, io_rs2_0, io_rs2_1, io_rd_0, io_rd_1, input [5:0] io_newPhys_0, io_newPhys_1, input io_wen_0, io_wen_1, output [5:0] io_prs1_0, io_prs1_1, io_prs2_0, io_prs2_1, io_oldPrd_0, io_oldPrd_1, input io_commitWen_0, io_commitWen_1, input [4:0] io_commitRd_0, io_commitRd_1, input [5:0] io_commitPhys_0, io_commitPhys_1, input io_recover, output [5:0] io_committedPhys_0, io_committedPhys_1, io_committedPhys_2, io_committedPhys_3, io_committedPhys_4, io_committedPhys_5, io_committedPhys_6, io_committedPhys_7, io_committedPhys_8, io_committedPhys_9, io_committedPhys_10, io_committedPhys_11, io_committedPhys_12, io_committedPhys_13, io_committedPhys_14, io_committedPhys_15, io_committedPhys_16, io_committedPhys_17, io_committedPhys_18, io_committedPhys_19, io_committedPhys_20, io_committedPhys_21, io_committedPhys_22, io_committedPhys_23, io_committedPhys_24, io_committedPhys_25, io_committedPhys_26, io_committedPhys_27, io_committedPhys_28, io_committedPhys_29, io_committedPhys_30, io_committedPhys_31 ); reg [5:0] speculative_0; reg [5:0] speculative_1; reg [5:0] speculative_2; reg [5:0] speculative_3; reg [5:0] speculative_4; reg [5:0] speculative_5; reg [5:0] speculative_6; reg [5:0] speculative_7; reg [5:0] speculative_8; reg [5:0] speculative_9; reg [5:0] speculative_10; reg [5:0] speculative_11; reg [5:0] speculative_12; reg [5:0] speculative_13; reg [5:0] speculative_14; reg [5:0] speculative_15; reg [5:0] speculative_16; reg [5:0] speculative_17; reg [5:0] speculative_18; reg [5:0] speculative_19; reg [5:0] speculative_20; reg [5:0] speculative_21; reg [5:0] speculative_22; reg [5:0] speculative_23; reg [5:0] speculative_24; reg [5:0] speculative_25; reg [5:0] speculative_26; reg [5:0] speculative_27; reg [5:0] speculative_28; reg [5:0] speculative_29; reg [5:0] speculative_30; reg [5:0] speculative_31; reg [5:0] committed_0; reg [5:0] committed_1; reg [5:0] committed_2; reg [5:0] committed_3; reg [5:0] committed_4; reg [5:0] committed_5; reg [5:0] committed_6; reg [5:0] committed_7; reg [5:0] committed_8; reg [5:0] committed_9; reg [5:0] committed_10; reg [5:0] committed_11; reg [5:0] committed_12; reg [5:0] committed_13; reg [5:0] committed_14; reg [5:0] committed_15; reg [5:0] committed_16; reg [5:0] committed_17; reg [5:0] committed_18; reg [5:0] committed_19; reg [5:0] committed_20; reg [5:0] committed_21; reg [5:0] committed_22; reg [5:0] committed_23; reg [5:0] committed_24; reg [5:0] committed_25; reg [5:0] committed_26; reg [5:0] committed_27; reg [5:0] committed_28; reg [5:0] committed_29; reg [5:0] committed_30; reg [5:0] committed_31; wire [31:0][5:0] _GEN = {{speculative_31}, {speculative_30}, {speculative_29}, {speculative_28}, {speculative_27}, {speculative_26}, {speculative_25}, {speculative_24}, {speculative_23}, {speculative_22}, {speculative_21}, {speculative_20}, {speculative_19}, {speculative_18}, {speculative_17}, {speculative_16}, {speculative_15}, {speculative_14}, {speculative_13}, {speculative_12}, {speculative_11}, {speculative_10}, {speculative_9}, {speculative_8}, {speculative_7}, {speculative_6}, {speculative_5}, {speculative_4}, {speculative_3}, {speculative_2}, {speculative_1}, {speculative_0}}; wire slot0Writes = io_wen_0 & (|io_rd_0); always @(posedge clock) begin if (reset) begin speculative_0 <= 6'h0; speculative_1 <= 6'h1; speculative_2 <= 6'h2; speculative_3 <= 6'h3; speculative_4 <= 6'h4; speculative_5 <= 6'h5; speculative_6 <= 6'h6; speculative_7 <= 6'h7; speculative_8 <= 6'h8; speculative_9 <= 6'h9; speculative_10 <= 6'hA; speculative_11 <= 6'hB; speculative_12 <= 6'hC; speculative_13 <= 6'hD; speculative_14 <= 6'hE; speculative_15 <= 6'hF; speculative_16 <= 6'h10; speculative_17 <= 6'h11; speculative_18 <= 6'h12; speculative_19 <= 6'h13; speculative_20 <= 6'h14; speculative_21 <= 6'h15; speculative_22 <= 6'h16; speculative_23 <= 6'h17; speculative_24 <= 6'h18; speculative_25 <= 6'h19; speculative_26 <= 6'h1A; speculative_27 <= 6'h1B; speculative_28 <= 6'h1C; speculative_29 <= 6'h1D; speculative_30 <= 6'h1E; speculative_31 <= 6'h1F; committed_0 <= 6'h0; committed_1 <= 6'h1; committed_2 <= 6'h2; committed_3 <= 6'h3; committed_4 <= 6'h4; committed_5 <= 6'h5; committed_6 <= 6'h6; committed_7 <= 6'h7; committed_8 <= 6'h8; committed_9 <= 6'h9; committed_10 <= 6'hA; committed_11 <= 6'hB; committed_12 <= 6'hC; committed_13 <= 6'hD; committed_14 <= 6'hE; committed_15 <= 6'hF; committed_16 <= 6'h10; committed_17 <= 6'h11; committed_18 <= 6'h12; committed_19 <= 6'h13; committed_20 <= 6'h14; committed_21 <= 6'h15; committed_22 <= 6'h16; committed_23 <= 6'h17; committed_24 <= 6'h18; committed_25 <= 6'h19; committed_26 <= 6'h1A; committed_27 <= 6'h1B; committed_28 <= 6'h1C; committed_29 <= 6'h1D; committed_30 <= 6'h1E; committed_31 <= 6'h1F; end else if (io_recover) begin speculative_0 <= committed_0; speculative_1 <= committed_1; speculative_2 <= committed_2; speculative_3 <= committed_3; speculative_4 <= committed_4; speculative_5 <= committed_5; speculative_6 <= committed_6; speculative_7 <= committed_7; speculative_8 <= committed_8; speculative_9 <= committed_9; speculative_10 <= committed_10; speculative_11 <= committed_11; speculative_12 <= committed_12; speculative_13 <= committed_13; speculative_14 <= committed_14; speculative_15 <= committed_15; speculative_16 <= committed_16; speculative_17 <= committed_17; speculative_18 <= committed_18; speculative_19 <= committed_19; speculative_20 <= committed_20; speculative_21 <= committed_21; speculative_22 <= committed_22; speculative_23 <= committed_23; speculative_24 <= committed_24; speculative_25 <= committed_25; speculative_26 <= committed_26; speculative_27 <= committed_27; speculative_28 <= committed_28; speculative_29 <= committed_29; speculative_30 <= committed_30; speculative_31 <= committed_31; end else begin automatic logic _GEN_0; automatic logic _GEN_1; automatic logic _GEN_2 = io_wen_1 & (|io_rd_1); automatic logic _GEN_3 = io_commitWen_1 & (|io_commitRd_1); _GEN_0 = io_wen_0 & (|io_rd_0); _GEN_1 = io_commitWen_0 & (|io_commitRd_0); if (_GEN_2 & ~(|io_rd_1)) speculative_0 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h0) speculative_0 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h1) speculative_1 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h1) speculative_1 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h2) speculative_2 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h2) speculative_2 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h3) speculative_3 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h3) speculative_3 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h4) speculative_4 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h4) speculative_4 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h5) speculative_5 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h5) speculative_5 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h6) speculative_6 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h6) speculative_6 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h7) speculative_7 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h7) speculative_7 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h8) speculative_8 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h8) speculative_8 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h9) speculative_9 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h9) speculative_9 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'hA) speculative_10 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'hA) speculative_10 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'hB) speculative_11 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'hB) speculative_11 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'hC) speculative_12 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'hC) speculative_12 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'hD) speculative_13 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'hD) speculative_13 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'hE) speculative_14 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'hE) speculative_14 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'hF) speculative_15 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'hF) speculative_15 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h10) speculative_16 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h10) speculative_16 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h11) speculative_17 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h11) speculative_17 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h12) speculative_18 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h12) speculative_18 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h13) speculative_19 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h13) speculative_19 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h14) speculative_20 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h14) speculative_20 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h15) speculative_21 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h15) speculative_21 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h16) speculative_22 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h16) speculative_22 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h17) speculative_23 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h17) speculative_23 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h18) speculative_24 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h18) speculative_24 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h19) speculative_25 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h19) speculative_25 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h1A) speculative_26 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h1A) speculative_26 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h1B) speculative_27 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h1B) speculative_27 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h1C) speculative_28 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h1C) speculative_28 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h1D) speculative_29 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h1D) speculative_29 <= io_newPhys_0; if (_GEN_2 & io_rd_1 == 5'h1E) speculative_30 <= io_newPhys_1; else if (_GEN_0 & io_rd_0 == 5'h1E) speculative_30 <= io_newPhys_0; if (_GEN_2 & (&io_rd_1)) speculative_31 <= io_newPhys_1; else if (_GEN_0 & (&io_rd_0)) speculative_31 <= io_newPhys_0; if (_GEN_3 & ~(|io_commitRd_1)) committed_0 <= io_commitPhys_1; else if (_GEN_1 & ~(|io_commitRd_0)) committed_0 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h1) committed_1 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h1) committed_1 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h2) committed_2 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h2) committed_2 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h3) committed_3 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h3) committed_3 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h4) committed_4 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h4) committed_4 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h5) committed_5 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h5) committed_5 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h6) committed_6 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h6) committed_6 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h7) committed_7 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h7) committed_7 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h8) committed_8 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h8) committed_8 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h9) committed_9 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h9) committed_9 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'hA) committed_10 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'hA) committed_10 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'hB) committed_11 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'hB) committed_11 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'hC) committed_12 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'hC) committed_12 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'hD) committed_13 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'hD) committed_13 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'hE) committed_14 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'hE) committed_14 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'hF) committed_15 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'hF) committed_15 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h10) committed_16 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h10) committed_16 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h11) committed_17 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h11) committed_17 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h12) committed_18 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h12) committed_18 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h13) committed_19 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h13) committed_19 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h14) committed_20 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h14) committed_20 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h15) committed_21 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h15) committed_21 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h16) committed_22 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h16) committed_22 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h17) committed_23 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h17) committed_23 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h18) committed_24 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h18) committed_24 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h19) committed_25 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h19) committed_25 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h1A) committed_26 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h1A) committed_26 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h1B) committed_27 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h1B) committed_27 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h1C) committed_28 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h1C) committed_28 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h1D) committed_29 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h1D) committed_29 <= io_commitPhys_0; if (_GEN_3 & io_commitRd_1 == 5'h1E) committed_30 <= io_commitPhys_1; else if (_GEN_1 & io_commitRd_0 == 5'h1E) committed_30 <= io_commitPhys_0; if (_GEN_3 & (&io_commitRd_1)) committed_31 <= io_commitPhys_1; else if (_GEN_1 & (&io_commitRd_0)) committed_31 <= io_commitPhys_0; end end // always @(posedge) assign io_prs1_0 = _GEN[io_rs1_0]; assign io_prs1_1 = slot0Writes & io_rd_0 == io_rs1_1 ? io_newPhys_0 : _GEN[io_rs1_1]; assign io_prs2_0 = _GEN[io_rs2_0]; assign io_prs2_1 = slot0Writes & io_rd_0 == io_rs2_1 ? io_newPhys_0 : _GEN[io_rs2_1]; assign io_oldPrd_0 = _GEN[io_rd_0]; assign io_oldPrd_1 = slot0Writes & io_rd_0 == io_rd_1 ? io_newPhys_0 : _GEN[io_rd_1]; assign io_committedPhys_0 = committed_0; assign io_committedPhys_1 = committed_1; assign io_committedPhys_2 = committed_2; assign io_committedPhys_3 = committed_3; assign io_committedPhys_4 = committed_4; assign io_committedPhys_5 = committed_5; assign io_committedPhys_6 = committed_6; assign io_committedPhys_7 = committed_7; assign io_committedPhys_8 = committed_8; assign io_committedPhys_9 = committed_9; assign io_committedPhys_10 = committed_10; assign io_committedPhys_11 = committed_11; assign io_committedPhys_12 = committed_12; assign io_committedPhys_13 = committed_13; assign io_committedPhys_14 = committed_14; assign io_committedPhys_15 = committed_15; assign io_committedPhys_16 = committed_16; assign io_committedPhys_17 = committed_17; assign io_committedPhys_18 = committed_18; assign io_committedPhys_19 = committed_19; assign io_committedPhys_20 = committed_20; assign io_committedPhys_21 = committed_21; assign io_committedPhys_22 = committed_22; assign io_committedPhys_23 = committed_23; assign io_committedPhys_24 = committed_24; assign io_committedPhys_25 = committed_25; assign io_committedPhys_26 = committed_26; assign io_committedPhys_27 = committed_27; assign io_committedPhys_28 = committed_28; assign io_committedPhys_29 = committed_29; assign io_committedPhys_30 = committed_30; assign io_committedPhys_31 = committed_31; endmodule