// Generated by CIRCT firtool-1.139.0 module LoadQueue( input clock, reset, io_enqValid, input [5:0] io_enqRobIdx, output [3:0] io_enqIdx, input io_addrValid, input [3:0] io_addrIdx, input [63:0] io_addr, input [2:0] io_size, input io_complete, input [3:0] io_completeIdx, input io_storeAddrValid, input [5:0] io_storeRobIdx, input [63:0] io_storeAddr, input [2:0] io_storeSize, output io_violation, input io_flush ); reg entries_0_valid; reg [5:0] entries_0_robIdx; reg entries_0_addrValid; reg [63:0] entries_0_addr; reg [2:0] entries_0_size; reg entries_0_completed; reg entries_1_valid; reg [5:0] entries_1_robIdx; reg entries_1_addrValid; reg [63:0] entries_1_addr; reg [2:0] entries_1_size; reg entries_1_completed; reg entries_2_valid; reg [5:0] entries_2_robIdx; reg entries_2_addrValid; reg [63:0] entries_2_addr; reg [2:0] entries_2_size; reg entries_2_completed; reg entries_3_valid; reg [5:0] entries_3_robIdx; reg entries_3_addrValid; reg [63:0] entries_3_addr; reg [2:0] entries_3_size; reg entries_3_completed; reg entries_4_valid; reg [5:0] entries_4_robIdx; reg entries_4_addrValid; reg [63:0] entries_4_addr; reg [2:0] entries_4_size; reg entries_4_completed; reg entries_5_valid; reg [5:0] entries_5_robIdx; reg entries_5_addrValid; reg [63:0] entries_5_addr; reg [2:0] entries_5_size; reg entries_5_completed; reg entries_6_valid; reg [5:0] entries_6_robIdx; reg entries_6_addrValid; reg [63:0] entries_6_addr; reg [2:0] entries_6_size; reg entries_6_completed; reg entries_7_valid; reg [5:0] entries_7_robIdx; reg entries_7_addrValid; reg [63:0] entries_7_addr; reg [2:0] entries_7_size; reg entries_7_completed; reg entries_8_valid; reg [5:0] entries_8_robIdx; reg entries_8_addrValid; reg [63:0] entries_8_addr; reg [2:0] entries_8_size; reg entries_8_completed; reg entries_9_valid; reg [5:0] entries_9_robIdx; reg entries_9_addrValid; reg [63:0] entries_9_addr; reg [2:0] entries_9_size; reg entries_9_completed; reg entries_10_valid; reg [5:0] entries_10_robIdx; reg entries_10_addrValid; reg [63:0] entries_10_addr; reg [2:0] entries_10_size; reg entries_10_completed; reg entries_11_valid; reg [5:0] entries_11_robIdx; reg entries_11_addrValid; reg [63:0] entries_11_addr; reg [2:0] entries_11_size; reg entries_11_completed; reg entries_12_valid; reg [5:0] entries_12_robIdx; reg entries_12_addrValid; reg [63:0] entries_12_addr; reg [2:0] entries_12_size; reg entries_12_completed; reg entries_13_valid; reg [5:0] entries_13_robIdx; reg entries_13_addrValid; reg [63:0] entries_13_addr; reg [2:0] entries_13_size; reg entries_13_completed; reg entries_14_valid; reg [5:0] entries_14_robIdx; reg entries_14_addrValid; reg [63:0] entries_14_addr; reg [2:0] entries_14_size; reg entries_14_completed; reg entries_15_valid; reg [5:0] entries_15_robIdx; reg entries_15_addrValid; reg [63:0] entries_15_addr; reg [2:0] entries_15_size; reg entries_15_completed; wire [14:0] enqOH = entries_0_valid ? (entries_1_valid ? (entries_2_valid ? (entries_3_valid ? (entries_4_valid ? (entries_5_valid ? (entries_6_valid ? (entries_7_valid ? (entries_8_valid ? (entries_9_valid ? (entries_10_valid ? (entries_11_valid ? (entries_12_valid ? (entries_13_valid ? (entries_14_valid ? {~entries_15_valid, 14'h0} : 15'h2000) : 15'h1000) : 15'h800) : 15'h400) : 15'h200) : 15'h100) : 15'h80) : 15'h40) : 15'h20) : 15'h10) : 15'h8) : 15'h4) : 15'h2) : 15'h1) : 15'h0; wire [6:0] _enqIdx_T_1 = enqOH[14:8] | enqOH[6:0]; wire [2:0] _enqIdx_T_3 = _enqIdx_T_1[6:4] | _enqIdx_T_1[2:0]; wire [3:0] enqIdx = {|(enqOH[14:7]), |(_enqIdx_T_1[6:3]), |(_enqIdx_T_3[2:1]), _enqIdx_T_3[2] | _enqIdx_T_3[0]}; wire _violationVec_15_bm_T = io_storeSize == 3'h0; wire _violationVec_15_bm_T_2 = io_storeSize == 3'h1; wire _violationVec_15_bm_T_4 = io_storeSize == 3'h2; wire _violationVec_15_bm_T_6 = io_storeSize == 3'h3; wire [15:0] _io_violation_T = {io_storeAddrValid & entries_15_valid & entries_15_completed & entries_15_addrValid & entries_15_robIdx > io_storeRobIdx & entries_15_addr[63:3] == io_storeAddr[63:3] & (entries_15_addr[2:0] | (entries_15_size == 3'h3 ? 3'h7 : entries_15_size == 3'h2 ? 3'h3 : entries_15_size == 3'h1 ? 3'h1 : entries_15_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0] & (io_storeAddr[2:0] | (_violationVec_15_bm_T_6 ? 3'h7 : _violationVec_15_bm_T_4 ? 3'h3 : _violationVec_15_bm_T_2 ? 3'h1 : _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_15_addr[2:0], io_storeAddrValid & entries_14_valid & entries_14_completed & entries_14_addrValid & entries_14_robIdx > io_storeRobIdx & entries_14_addr[63:3] == io_storeAddr[63:3] & (entries_14_addr[2:0] | (entries_14_size == 3'h3 ? 3'h7 : entries_14_size == 3'h2 ? 3'h3 : entries_14_size == 3'h1 ? 3'h1 : entries_14_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0] & (io_storeAddr[2:0] | (_violationVec_15_bm_T_6 ? 3'h7 : _violationVec_15_bm_T_4 ? 3'h3 : _violationVec_15_bm_T_2 ? 3'h1 : _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_14_addr[2:0], io_storeAddrValid & entries_13_valid & entries_13_completed & entries_13_addrValid & entries_13_robIdx > io_storeRobIdx & entries_13_addr[63:3] == io_storeAddr[63:3] & (entries_13_addr[2:0] | (entries_13_size == 3'h3 ? 3'h7 : entries_13_size == 3'h2 ? 3'h3 : entries_13_size == 3'h1 ? 3'h1 : entries_13_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0] & (io_storeAddr[2:0] | (_violationVec_15_bm_T_6 ? 3'h7 : _violationVec_15_bm_T_4 ? 3'h3 : _violationVec_15_bm_T_2 ? 3'h1 : _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_13_addr[2:0], io_storeAddrValid & entries_12_valid & entries_12_completed & entries_12_addrValid & entries_12_robIdx > io_storeRobIdx & entries_12_addr[63:3] == io_storeAddr[63:3] & (entries_12_addr[2:0] | (entries_12_size == 3'h3 ? 3'h7 : entries_12_size == 3'h2 ? 3'h3 : entries_12_size == 3'h1 ? 3'h1 : entries_12_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0] & (io_storeAddr[2:0] | (_violationVec_15_bm_T_6 ? 3'h7 : _violationVec_15_bm_T_4 ? 3'h3 : _violationVec_15_bm_T_2 ? 3'h1 : _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_12_addr[2:0], io_storeAddrValid & entries_11_valid & entries_11_completed & entries_11_addrValid & entries_11_robIdx > io_storeRobIdx & entries_11_addr[63:3] == io_storeAddr[63:3] & (entries_11_addr[2:0] | (entries_11_size == 3'h3 ? 3'h7 : entries_11_size == 3'h2 ? 3'h3 : entries_11_size == 3'h1 ? 3'h1 : entries_11_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0] & (io_storeAddr[2:0] | (_violationVec_15_bm_T_6 ? 3'h7 : _violationVec_15_bm_T_4 ? 3'h3 : _violationVec_15_bm_T_2 ? 3'h1 : _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_11_addr[2:0], io_storeAddrValid & entries_10_valid & entries_10_completed & entries_10_addrValid & entries_10_robIdx > io_storeRobIdx & entries_10_addr[63:3] == io_storeAddr[63:3] & (entries_10_addr[2:0] | (entries_10_size == 3'h3 ? 3'h7 : entries_10_size == 3'h2 ? 3'h3 : entries_10_size == 3'h1 ? 3'h1 : entries_10_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0] & (io_storeAddr[2:0] | (_violationVec_15_bm_T_6 ? 3'h7 : _violationVec_15_bm_T_4 ? 3'h3 : _violationVec_15_bm_T_2 ? 3'h1 : _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_10_addr[2:0], io_storeAddrValid & entries_9_valid & entries_9_completed & entries_9_addrValid & entries_9_robIdx > io_storeRobIdx & entries_9_addr[63:3] == io_storeAddr[63:3] & (entries_9_addr[2:0] | (entries_9_size == 3'h3 ? 3'h7 : entries_9_size == 3'h2 ? 3'h3 : entries_9_size == 3'h1 ? 3'h1 : entries_9_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0] & (io_storeAddr[2:0] | (_violationVec_15_bm_T_6 ? 3'h7 : _violationVec_15_bm_T_4 ? 3'h3 : _violationVec_15_bm_T_2 ? 3'h1 : _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_9_addr[2:0], io_storeAddrValid & entries_8_valid & entries_8_completed & entries_8_addrValid & entries_8_robIdx > io_storeRobIdx & entries_8_addr[63:3] == io_storeAddr[63:3] & (entries_8_addr[2:0] | (entries_8_size == 3'h3 ? 3'h7 : entries_8_size == 3'h2 ? 3'h3 : entries_8_size == 3'h1 ? 3'h1 : entries_8_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0] & (io_storeAddr[2:0] | (_violationVec_15_bm_T_6 ? 3'h7 : _violationVec_15_bm_T_4 ? 3'h3 : _violationVec_15_bm_T_2 ? 3'h1 : _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_8_addr[2:0], io_storeAddrValid & entries_7_valid & entries_7_completed & entries_7_addrValid & entries_7_robIdx > io_storeRobIdx & entries_7_addr[63:3] == io_storeAddr[63:3] & (entries_7_addr[2:0] | (entries_7_size == 3'h3 ? 3'h7 : entries_7_size == 3'h2 ? 3'h3 : entries_7_size == 3'h1 ? 3'h1 : entries_7_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0] & (io_storeAddr[2:0] | (_violationVec_15_bm_T_6 ? 3'h7 : _violationVec_15_bm_T_4 ? 3'h3 : _violationVec_15_bm_T_2 ? 3'h1 : _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_7_addr[2:0], io_storeAddrValid & entries_6_valid & entries_6_completed & entries_6_addrValid & entries_6_robIdx > io_storeRobIdx & entries_6_addr[63:3] == io_storeAddr[63:3] & (entries_6_addr[2:0] | (entries_6_size == 3'h3 ? 3'h7 : entries_6_size == 3'h2 ? 3'h3 : entries_6_size == 3'h1 ? 3'h1 : entries_6_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0] & (io_storeAddr[2:0] | (_violationVec_15_bm_T_6 ? 3'h7 : _violationVec_15_bm_T_4 ? 3'h3 : _violationVec_15_bm_T_2 ? 3'h1 : _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_6_addr[2:0], io_storeAddrValid & entries_5_valid & entries_5_completed & entries_5_addrValid & entries_5_robIdx > io_storeRobIdx & entries_5_addr[63:3] == io_storeAddr[63:3] & (entries_5_addr[2:0] | (entries_5_size == 3'h3 ? 3'h7 : entries_5_size == 3'h2 ? 3'h3 : entries_5_size == 3'h1 ? 3'h1 : entries_5_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0] & (io_storeAddr[2:0] | (_violationVec_15_bm_T_6 ? 3'h7 : _violationVec_15_bm_T_4 ? 3'h3 : _violationVec_15_bm_T_2 ? 3'h1 : _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_5_addr[2:0], io_storeAddrValid & entries_4_valid & entries_4_completed & entries_4_addrValid & entries_4_robIdx > io_storeRobIdx & entries_4_addr[63:3] == io_storeAddr[63:3] & (entries_4_addr[2:0] | (entries_4_size == 3'h3 ? 3'h7 : entries_4_size == 3'h2 ? 3'h3 : entries_4_size == 3'h1 ? 3'h1 : entries_4_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0] & (io_storeAddr[2:0] | (_violationVec_15_bm_T_6 ? 3'h7 : _violationVec_15_bm_T_4 ? 3'h3 : _violationVec_15_bm_T_2 ? 3'h1 : _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_4_addr[2:0], io_storeAddrValid & entries_3_valid & entries_3_completed & entries_3_addrValid & entries_3_robIdx > io_storeRobIdx & entries_3_addr[63:3] == io_storeAddr[63:3] & (entries_3_addr[2:0] | (entries_3_size == 3'h3 ? 3'h7 : entries_3_size == 3'h2 ? 3'h3 : entries_3_size == 3'h1 ? 3'h1 : entries_3_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0] & (io_storeAddr[2:0] | (_violationVec_15_bm_T_6 ? 3'h7 : _violationVec_15_bm_T_4 ? 3'h3 : _violationVec_15_bm_T_2 ? 3'h1 : _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_3_addr[2:0], io_storeAddrValid & entries_2_valid & entries_2_completed & entries_2_addrValid & entries_2_robIdx > io_storeRobIdx & entries_2_addr[63:3] == io_storeAddr[63:3] & (entries_2_addr[2:0] | (entries_2_size == 3'h3 ? 3'h7 : entries_2_size == 3'h2 ? 3'h3 : entries_2_size == 3'h1 ? 3'h1 : entries_2_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0] & (io_storeAddr[2:0] | (_violationVec_15_bm_T_6 ? 3'h7 : _violationVec_15_bm_T_4 ? 3'h3 : _violationVec_15_bm_T_2 ? 3'h1 : _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_2_addr[2:0], io_storeAddrValid & entries_1_valid & entries_1_completed & entries_1_addrValid & entries_1_robIdx > io_storeRobIdx & entries_1_addr[63:3] == io_storeAddr[63:3] & (entries_1_addr[2:0] | (entries_1_size == 3'h3 ? 3'h7 : entries_1_size == 3'h2 ? 3'h3 : entries_1_size == 3'h1 ? 3'h1 : entries_1_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0] & (io_storeAddr[2:0] | (_violationVec_15_bm_T_6 ? 3'h7 : _violationVec_15_bm_T_4 ? 3'h3 : _violationVec_15_bm_T_2 ? 3'h1 : _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_1_addr[2:0], io_storeAddrValid & entries_0_valid & entries_0_completed & entries_0_addrValid & entries_0_robIdx > io_storeRobIdx & entries_0_addr[63:3] == io_storeAddr[63:3] & (entries_0_addr[2:0] | (entries_0_size == 3'h3 ? 3'h7 : entries_0_size == 3'h2 ? 3'h3 : entries_0_size == 3'h1 ? 3'h1 : entries_0_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0] & (io_storeAddr[2:0] | (_violationVec_15_bm_T_6 ? 3'h7 : _violationVec_15_bm_T_4 ? 3'h3 : _violationVec_15_bm_T_2 ? 3'h1 : _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_0_addr[2:0]}; always @(posedge clock) begin if (reset) begin entries_0_valid <= 1'h0; entries_0_robIdx <= 6'h0; entries_0_addrValid <= 1'h0; entries_0_addr <= 64'h0; entries_0_size <= 3'h0; entries_0_completed <= 1'h0; entries_1_valid <= 1'h0; entries_1_robIdx <= 6'h0; entries_1_addrValid <= 1'h0; entries_1_addr <= 64'h0; entries_1_size <= 3'h0; entries_1_completed <= 1'h0; entries_2_valid <= 1'h0; entries_2_robIdx <= 6'h0; entries_2_addrValid <= 1'h0; entries_2_addr <= 64'h0; entries_2_size <= 3'h0; entries_2_completed <= 1'h0; entries_3_valid <= 1'h0; entries_3_robIdx <= 6'h0; entries_3_addrValid <= 1'h0; entries_3_addr <= 64'h0; entries_3_size <= 3'h0; entries_3_completed <= 1'h0; entries_4_valid <= 1'h0; entries_4_robIdx <= 6'h0; entries_4_addrValid <= 1'h0; entries_4_addr <= 64'h0; entries_4_size <= 3'h0; entries_4_completed <= 1'h0; entries_5_valid <= 1'h0; entries_5_robIdx <= 6'h0; entries_5_addrValid <= 1'h0; entries_5_addr <= 64'h0; entries_5_size <= 3'h0; entries_5_completed <= 1'h0; entries_6_valid <= 1'h0; entries_6_robIdx <= 6'h0; entries_6_addrValid <= 1'h0; entries_6_addr <= 64'h0; entries_6_size <= 3'h0; entries_6_completed <= 1'h0; entries_7_valid <= 1'h0; entries_7_robIdx <= 6'h0; entries_7_addrValid <= 1'h0; entries_7_addr <= 64'h0; entries_7_size <= 3'h0; entries_7_completed <= 1'h0; entries_8_valid <= 1'h0; entries_8_robIdx <= 6'h0; entries_8_addrValid <= 1'h0; entries_8_addr <= 64'h0; entries_8_size <= 3'h0; entries_8_completed <= 1'h0; entries_9_valid <= 1'h0; entries_9_robIdx <= 6'h0; entries_9_addrValid <= 1'h0; entries_9_addr <= 64'h0; entries_9_size <= 3'h0; entries_9_completed <= 1'h0; entries_10_valid <= 1'h0; entries_10_robIdx <= 6'h0; entries_10_addrValid <= 1'h0; entries_10_addr <= 64'h0; entries_10_size <= 3'h0; entries_10_completed <= 1'h0; entries_11_valid <= 1'h0; entries_11_robIdx <= 6'h0; entries_11_addrValid <= 1'h0; entries_11_addr <= 64'h0; entries_11_size <= 3'h0; entries_11_completed <= 1'h0; entries_12_valid <= 1'h0; entries_12_robIdx <= 6'h0; entries_12_addrValid <= 1'h0; entries_12_addr <= 64'h0; entries_12_size <= 3'h0; entries_12_completed <= 1'h0; entries_13_valid <= 1'h0; entries_13_robIdx <= 6'h0; entries_13_addrValid <= 1'h0; entries_13_addr <= 64'h0; entries_13_size <= 3'h0; entries_13_completed <= 1'h0; entries_14_valid <= 1'h0; entries_14_robIdx <= 6'h0; entries_14_addrValid <= 1'h0; entries_14_addr <= 64'h0; entries_14_size <= 3'h0; entries_14_completed <= 1'h0; entries_15_valid <= 1'h0; entries_15_robIdx <= 6'h0; entries_15_addrValid <= 1'h0; entries_15_addr <= 64'h0; entries_15_size <= 3'h0; entries_15_completed <= 1'h0; end else begin automatic logic _GEN = io_enqValid & (|{~entries_15_valid, ~entries_14_valid, ~entries_13_valid, ~entries_12_valid, ~entries_11_valid, ~entries_10_valid, ~entries_9_valid, ~entries_8_valid, ~entries_7_valid, ~entries_6_valid, ~entries_5_valid, ~entries_4_valid, ~entries_3_valid, ~entries_2_valid, ~entries_1_valid, ~entries_0_valid}); automatic logic _GEN_0; automatic logic _GEN_1; automatic logic _GEN_2; automatic logic _GEN_3; automatic logic _GEN_4; automatic logic _GEN_5; automatic logic _GEN_6; automatic logic _GEN_7; automatic logic _GEN_8; automatic logic _GEN_9; automatic logic _GEN_10; automatic logic _GEN_11; automatic logic _GEN_12; automatic logic _GEN_13; automatic logic _GEN_14; automatic logic _GEN_15; automatic logic _GEN_16; automatic logic _GEN_17; automatic logic _GEN_18; automatic logic _GEN_19; automatic logic _GEN_20; automatic logic _GEN_21; automatic logic _GEN_22; automatic logic _GEN_23; automatic logic _GEN_24; automatic logic _GEN_25; automatic logic _GEN_26; automatic logic _GEN_27; automatic logic _GEN_28; automatic logic _GEN_29; automatic logic _GEN_30; automatic logic _GEN_31; _GEN_0 = _GEN & enqIdx == 4'h0; _GEN_1 = _GEN & enqIdx == 4'h1; _GEN_2 = _GEN & enqIdx == 4'h2; _GEN_3 = _GEN & enqIdx == 4'h3; _GEN_4 = _GEN & enqIdx == 4'h4; _GEN_5 = _GEN & enqIdx == 4'h5; _GEN_6 = _GEN & enqIdx == 4'h6; _GEN_7 = _GEN & enqIdx == 4'h7; _GEN_8 = _GEN & enqIdx == 4'h8; _GEN_9 = _GEN & enqIdx == 4'h9; _GEN_10 = _GEN & enqIdx == 4'hA; _GEN_11 = _GEN & enqIdx == 4'hB; _GEN_12 = _GEN & enqIdx == 4'hC; _GEN_13 = _GEN & enqIdx == 4'hD; _GEN_14 = _GEN & enqIdx == 4'hE; _GEN_15 = _GEN & (&enqIdx); _GEN_16 = io_addrValid & io_addrIdx == 4'h0; _GEN_17 = io_addrValid & io_addrIdx == 4'h1; _GEN_18 = io_addrValid & io_addrIdx == 4'h2; _GEN_19 = io_addrValid & io_addrIdx == 4'h3; _GEN_20 = io_addrValid & io_addrIdx == 4'h4; _GEN_21 = io_addrValid & io_addrIdx == 4'h5; _GEN_22 = io_addrValid & io_addrIdx == 4'h6; _GEN_23 = io_addrValid & io_addrIdx == 4'h7; _GEN_24 = io_addrValid & io_addrIdx == 4'h8; _GEN_25 = io_addrValid & io_addrIdx == 4'h9; _GEN_26 = io_addrValid & io_addrIdx == 4'hA; _GEN_27 = io_addrValid & io_addrIdx == 4'hB; _GEN_28 = io_addrValid & io_addrIdx == 4'hC; _GEN_29 = io_addrValid & io_addrIdx == 4'hD; _GEN_30 = io_addrValid & io_addrIdx == 4'hE; _GEN_31 = io_addrValid & (&io_addrIdx); entries_0_valid <= ~io_flush & (_GEN_0 | entries_0_valid); if (io_flush) begin entries_0_robIdx <= 6'h0; entries_0_addr <= 64'h0; entries_0_size <= 3'h0; entries_1_robIdx <= 6'h0; entries_1_addr <= 64'h0; entries_1_size <= 3'h0; entries_2_robIdx <= 6'h0; entries_2_addr <= 64'h0; entries_2_size <= 3'h0; entries_3_robIdx <= 6'h0; entries_3_addr <= 64'h0; entries_3_size <= 3'h0; entries_4_robIdx <= 6'h0; entries_4_addr <= 64'h0; entries_4_size <= 3'h0; entries_5_robIdx <= 6'h0; entries_5_addr <= 64'h0; entries_5_size <= 3'h0; entries_6_robIdx <= 6'h0; entries_6_addr <= 64'h0; entries_6_size <= 3'h0; entries_7_robIdx <= 6'h0; entries_7_addr <= 64'h0; entries_7_size <= 3'h0; entries_8_robIdx <= 6'h0; entries_8_addr <= 64'h0; entries_8_size <= 3'h0; entries_9_robIdx <= 6'h0; entries_9_addr <= 64'h0; entries_9_size <= 3'h0; entries_10_robIdx <= 6'h0; entries_10_addr <= 64'h0; entries_10_size <= 3'h0; entries_11_robIdx <= 6'h0; entries_11_addr <= 64'h0; entries_11_size <= 3'h0; entries_12_robIdx <= 6'h0; entries_12_addr <= 64'h0; entries_12_size <= 3'h0; entries_13_robIdx <= 6'h0; entries_13_addr <= 64'h0; entries_13_size <= 3'h0; entries_14_robIdx <= 6'h0; entries_14_addr <= 64'h0; entries_14_size <= 3'h0; entries_15_robIdx <= 6'h0; entries_15_addr <= 64'h0; entries_15_size <= 3'h0; end else begin if (_GEN_0) entries_0_robIdx <= io_enqRobIdx; if (_GEN_16) begin entries_0_addr <= io_addr; entries_0_size <= io_size; end if (_GEN_1) entries_1_robIdx <= io_enqRobIdx; if (_GEN_17) begin entries_1_addr <= io_addr; entries_1_size <= io_size; end if (_GEN_2) entries_2_robIdx <= io_enqRobIdx; if (_GEN_18) begin entries_2_addr <= io_addr; entries_2_size <= io_size; end if (_GEN_3) entries_3_robIdx <= io_enqRobIdx; if (_GEN_19) begin entries_3_addr <= io_addr; entries_3_size <= io_size; end if (_GEN_4) entries_4_robIdx <= io_enqRobIdx; if (_GEN_20) begin entries_4_addr <= io_addr; entries_4_size <= io_size; end if (_GEN_5) entries_5_robIdx <= io_enqRobIdx; if (_GEN_21) begin entries_5_addr <= io_addr; entries_5_size <= io_size; end if (_GEN_6) entries_6_robIdx <= io_enqRobIdx; if (_GEN_22) begin entries_6_addr <= io_addr; entries_6_size <= io_size; end if (_GEN_7) entries_7_robIdx <= io_enqRobIdx; if (_GEN_23) begin entries_7_addr <= io_addr; entries_7_size <= io_size; end if (_GEN_8) entries_8_robIdx <= io_enqRobIdx; if (_GEN_24) begin entries_8_addr <= io_addr; entries_8_size <= io_size; end if (_GEN_9) entries_9_robIdx <= io_enqRobIdx; if (_GEN_25) begin entries_9_addr <= io_addr; entries_9_size <= io_size; end if (_GEN_10) entries_10_robIdx <= io_enqRobIdx; if (_GEN_26) begin entries_10_addr <= io_addr; entries_10_size <= io_size; end if (_GEN_11) entries_11_robIdx <= io_enqRobIdx; if (_GEN_27) begin entries_11_addr <= io_addr; entries_11_size <= io_size; end if (_GEN_12) entries_12_robIdx <= io_enqRobIdx; if (_GEN_28) begin entries_12_addr <= io_addr; entries_12_size <= io_size; end if (_GEN_13) entries_13_robIdx <= io_enqRobIdx; if (_GEN_29) begin entries_13_addr <= io_addr; entries_13_size <= io_size; end if (_GEN_14) entries_14_robIdx <= io_enqRobIdx; if (_GEN_30) begin entries_14_addr <= io_addr; entries_14_size <= io_size; end if (_GEN_15) entries_15_robIdx <= io_enqRobIdx; if (_GEN_31) begin entries_15_addr <= io_addr; entries_15_size <= io_size; end end entries_0_addrValid <= ~io_flush & (_GEN_16 | ~_GEN_0 & entries_0_addrValid); entries_0_completed <= ~io_flush & (io_complete & io_completeIdx == 4'h0 | ~_GEN_0 & entries_0_completed); entries_1_valid <= ~io_flush & (_GEN_1 | entries_1_valid); entries_1_addrValid <= ~io_flush & (_GEN_17 | ~_GEN_1 & entries_1_addrValid); entries_1_completed <= ~io_flush & (io_complete & io_completeIdx == 4'h1 | ~_GEN_1 & entries_1_completed); entries_2_valid <= ~io_flush & (_GEN_2 | entries_2_valid); entries_2_addrValid <= ~io_flush & (_GEN_18 | ~_GEN_2 & entries_2_addrValid); entries_2_completed <= ~io_flush & (io_complete & io_completeIdx == 4'h2 | ~_GEN_2 & entries_2_completed); entries_3_valid <= ~io_flush & (_GEN_3 | entries_3_valid); entries_3_addrValid <= ~io_flush & (_GEN_19 | ~_GEN_3 & entries_3_addrValid); entries_3_completed <= ~io_flush & (io_complete & io_completeIdx == 4'h3 | ~_GEN_3 & entries_3_completed); entries_4_valid <= ~io_flush & (_GEN_4 | entries_4_valid); entries_4_addrValid <= ~io_flush & (_GEN_20 | ~_GEN_4 & entries_4_addrValid); entries_4_completed <= ~io_flush & (io_complete & io_completeIdx == 4'h4 | ~_GEN_4 & entries_4_completed); entries_5_valid <= ~io_flush & (_GEN_5 | entries_5_valid); entries_5_addrValid <= ~io_flush & (_GEN_21 | ~_GEN_5 & entries_5_addrValid); entries_5_completed <= ~io_flush & (io_complete & io_completeIdx == 4'h5 | ~_GEN_5 & entries_5_completed); entries_6_valid <= ~io_flush & (_GEN_6 | entries_6_valid); entries_6_addrValid <= ~io_flush & (_GEN_22 | ~_GEN_6 & entries_6_addrValid); entries_6_completed <= ~io_flush & (io_complete & io_completeIdx == 4'h6 | ~_GEN_6 & entries_6_completed); entries_7_valid <= ~io_flush & (_GEN_7 | entries_7_valid); entries_7_addrValid <= ~io_flush & (_GEN_23 | ~_GEN_7 & entries_7_addrValid); entries_7_completed <= ~io_flush & (io_complete & io_completeIdx == 4'h7 | ~_GEN_7 & entries_7_completed); entries_8_valid <= ~io_flush & (_GEN_8 | entries_8_valid); entries_8_addrValid <= ~io_flush & (_GEN_24 | ~_GEN_8 & entries_8_addrValid); entries_8_completed <= ~io_flush & (io_complete & io_completeIdx == 4'h8 | ~_GEN_8 & entries_8_completed); entries_9_valid <= ~io_flush & (_GEN_9 | entries_9_valid); entries_9_addrValid <= ~io_flush & (_GEN_25 | ~_GEN_9 & entries_9_addrValid); entries_9_completed <= ~io_flush & (io_complete & io_completeIdx == 4'h9 | ~_GEN_9 & entries_9_completed); entries_10_valid <= ~io_flush & (_GEN_10 | entries_10_valid); entries_10_addrValid <= ~io_flush & (_GEN_26 | ~_GEN_10 & entries_10_addrValid); entries_10_completed <= ~io_flush & (io_complete & io_completeIdx == 4'hA | ~_GEN_10 & entries_10_completed); entries_11_valid <= ~io_flush & (_GEN_11 | entries_11_valid); entries_11_addrValid <= ~io_flush & (_GEN_27 | ~_GEN_11 & entries_11_addrValid); entries_11_completed <= ~io_flush & (io_complete & io_completeIdx == 4'hB | ~_GEN_11 & entries_11_completed); entries_12_valid <= ~io_flush & (_GEN_12 | entries_12_valid); entries_12_addrValid <= ~io_flush & (_GEN_28 | ~_GEN_12 & entries_12_addrValid); entries_12_completed <= ~io_flush & (io_complete & io_completeIdx == 4'hC | ~_GEN_12 & entries_12_completed); entries_13_valid <= ~io_flush & (_GEN_13 | entries_13_valid); entries_13_addrValid <= ~io_flush & (_GEN_29 | ~_GEN_13 & entries_13_addrValid); entries_13_completed <= ~io_flush & (io_complete & io_completeIdx == 4'hD | ~_GEN_13 & entries_13_completed); entries_14_valid <= ~io_flush & (_GEN_14 | entries_14_valid); entries_14_addrValid <= ~io_flush & (_GEN_30 | ~_GEN_14 & entries_14_addrValid); entries_14_completed <= ~io_flush & (io_complete & io_completeIdx == 4'hE | ~_GEN_14 & entries_14_completed); entries_15_valid <= ~io_flush & (_GEN_15 | entries_15_valid); entries_15_addrValid <= ~io_flush & (_GEN_31 | ~_GEN_15 & entries_15_addrValid); entries_15_completed <= ~io_flush & (io_complete & (&io_completeIdx) | ~_GEN_15 & entries_15_completed); end end // always @(posedge) assign io_enqIdx = enqIdx; assign io_violation = |_io_violation_T; endmodule