// Generated by CIRCT firtool-1.139.0 module ReservationStation( input clock, reset, io_enqValid_0, io_enqValid_1, input [63:0] io_enq_0_decoded_pc, input [31:0] io_enq_0_decoded_inst, input [4:0] io_enq_0_decoded_rs1, io_enq_0_decoded_rs2, input [2:0] io_enq_0_decoded_funct3, input [63:0] io_enq_0_decoded_immI, io_enq_0_decoded_immS, io_enq_0_decoded_immB, io_enq_0_decoded_immU, io_enq_0_decoded_immJ, input [4:0] io_enq_0_decoded_aluFn, input [2:0] io_enq_0_decoded_memWidth, input io_enq_0_decoded_memSigned, io_enq_0_decoded_isLoad, io_enq_0_decoded_isStore, io_enq_0_decoded_isBranch, io_enq_0_decoded_isJal, io_enq_0_decoded_isJalr, io_enq_0_decoded_isLui, io_enq_0_decoded_isAuipc, io_enq_0_decoded_isOpImm, io_enq_0_decoded_isWord, io_enq_0_decoded_isSystem, io_enq_0_decoded_isFenceI, io_enq_0_decoded_isEcall, io_enq_0_decoded_isEbreak, io_enq_0_decoded_isMret, io_enq_0_decoded_isSret, io_enq_0_decoded_isSfenceVma, io_enq_0_decoded_isXret, io_enq_0_decoded_isWfi, io_enq_0_decoded_isAmo, input [4:0] io_enq_0_decoded_amoOp, input io_enq_0_decoded_writesRd, io_enq_0_decoded_illegal, io_enq_0_decoded_fetchException, input [63:0] io_enq_0_decoded_fetchExceptionCause, io_enq_0_decoded_fetchExceptionTval, input [5:0] io_enq_0_prs1, io_enq_0_prs2, input io_enq_0_src1Ready, io_enq_0_src2Ready, input [5:0] io_enq_0_prd, io_enq_0_robIdx, input [63:0] io_enq_1_decoded_pc, input [31:0] io_enq_1_decoded_inst, input [4:0] io_enq_1_decoded_rs1, io_enq_1_decoded_rs2, input [2:0] io_enq_1_decoded_funct3, input [63:0] io_enq_1_decoded_immI, io_enq_1_decoded_immS, io_enq_1_decoded_immB, io_enq_1_decoded_immU, io_enq_1_decoded_immJ, input [4:0] io_enq_1_decoded_aluFn, input [2:0] io_enq_1_decoded_memWidth, input io_enq_1_decoded_memSigned, io_enq_1_decoded_isLoad, io_enq_1_decoded_isStore, io_enq_1_decoded_isBranch, io_enq_1_decoded_isJal, io_enq_1_decoded_isJalr, io_enq_1_decoded_isLui, io_enq_1_decoded_isAuipc, io_enq_1_decoded_isOpImm, io_enq_1_decoded_isWord, io_enq_1_decoded_isSystem, io_enq_1_decoded_isFenceI, io_enq_1_decoded_isEcall, io_enq_1_decoded_isEbreak, io_enq_1_decoded_isMret, io_enq_1_decoded_isSret, io_enq_1_decoded_isSfenceVma, io_enq_1_decoded_isXret, io_enq_1_decoded_isWfi, io_enq_1_decoded_isAmo, input [4:0] io_enq_1_decoded_amoOp, input io_enq_1_decoded_writesRd, io_enq_1_decoded_illegal, io_enq_1_decoded_fetchException, input [63:0] io_enq_1_decoded_fetchExceptionCause, io_enq_1_decoded_fetchExceptionTval, input [5:0] io_enq_1_prs1, io_enq_1_prs2, input io_enq_1_src1Ready, io_enq_1_src2Ready, input [5:0] io_enq_1_prd, io_enq_1_robIdx, output io_enqReady_0, io_enqReady_1, input io_wakeup_0_valid, input [5:0] io_wakeup_0_phys, input io_wakeup_1_valid, input [5:0] io_wakeup_1_phys, output io_issueValid_0, io_issueValid_1, output [63:0] io_issue_0_decoded_pc, output [31:0] io_issue_0_decoded_inst, output [4:0] io_issue_0_decoded_rs1, output [2:0] io_issue_0_decoded_funct3, output [63:0] io_issue_0_decoded_immI, io_issue_0_decoded_immS, io_issue_0_decoded_immB, io_issue_0_decoded_immU, io_issue_0_decoded_immJ, output [4:0] io_issue_0_decoded_aluFn, output [2:0] io_issue_0_decoded_memWidth, output io_issue_0_decoded_memSigned, io_issue_0_decoded_isLoad, io_issue_0_decoded_isStore, io_issue_0_decoded_isBranch, io_issue_0_decoded_isJal, io_issue_0_decoded_isJalr, io_issue_0_decoded_isLui, io_issue_0_decoded_isAuipc, io_issue_0_decoded_isOpImm, io_issue_0_decoded_isWord, io_issue_0_decoded_isSystem, io_issue_0_decoded_isFenceI, io_issue_0_decoded_isEcall, io_issue_0_decoded_isEbreak, io_issue_0_decoded_isMret, io_issue_0_decoded_isSret, io_issue_0_decoded_isSfenceVma, io_issue_0_decoded_isXret, io_issue_0_decoded_isWfi, io_issue_0_decoded_isAmo, output [4:0] io_issue_0_decoded_amoOp, output io_issue_0_decoded_writesRd, io_issue_0_decoded_illegal, io_issue_0_decoded_fetchException, output [63:0] io_issue_0_decoded_fetchExceptionCause, io_issue_0_decoded_fetchExceptionTval, output [5:0] io_issue_0_prs1, io_issue_0_prs2, io_issue_0_prd, io_issue_0_robIdx, output [63:0] io_issue_1_decoded_pc, output [31:0] io_issue_1_decoded_inst, output [4:0] io_issue_1_decoded_rs1, output [2:0] io_issue_1_decoded_funct3, output [63:0] io_issue_1_decoded_immI, io_issue_1_decoded_immS, io_issue_1_decoded_immB, io_issue_1_decoded_immU, io_issue_1_decoded_immJ, output [4:0] io_issue_1_decoded_aluFn, output [2:0] io_issue_1_decoded_memWidth, output io_issue_1_decoded_memSigned, io_issue_1_decoded_isLoad, io_issue_1_decoded_isStore, io_issue_1_decoded_isBranch, io_issue_1_decoded_isJal, io_issue_1_decoded_isJalr, io_issue_1_decoded_isLui, io_issue_1_decoded_isAuipc, io_issue_1_decoded_isOpImm, io_issue_1_decoded_isWord, io_issue_1_decoded_isSystem, io_issue_1_decoded_isFenceI, io_issue_1_decoded_isEcall, io_issue_1_decoded_isEbreak, io_issue_1_decoded_isMret, io_issue_1_decoded_isSret, io_issue_1_decoded_isSfenceVma, io_issue_1_decoded_isXret, io_issue_1_decoded_isWfi, io_issue_1_decoded_isAmo, output [4:0] io_issue_1_decoded_amoOp, output io_issue_1_decoded_writesRd, io_issue_1_decoded_illegal, io_issue_1_decoded_fetchException, output [63:0] io_issue_1_decoded_fetchExceptionCause, io_issue_1_decoded_fetchExceptionTval, output [5:0] io_issue_1_prs1, io_issue_1_prs2, io_issue_1_prd, io_issue_1_robIdx, input io_issueReady_0, io_issueReady_1, io_robHeadValid, input [5:0] io_robHeadIdx, input io_flush ); reg valid_0; reg valid_1; reg valid_2; reg valid_3; reg valid_4; reg valid_5; reg valid_6; reg valid_7; reg valid_8; reg valid_9; reg valid_10; reg valid_11; reg valid_12; reg valid_13; reg valid_14; reg valid_15; reg [63:0] slots_0_decoded_pc; reg [31:0] slots_0_decoded_inst; reg [4:0] slots_0_decoded_rs1; reg [4:0] slots_0_decoded_rs2; reg [2:0] slots_0_decoded_funct3; reg [63:0] slots_0_decoded_immI; reg [63:0] slots_0_decoded_immS; reg [63:0] slots_0_decoded_immB; reg [63:0] slots_0_decoded_immU; reg [63:0] slots_0_decoded_immJ; reg [4:0] slots_0_decoded_aluFn; reg [2:0] slots_0_decoded_memWidth; reg slots_0_decoded_memSigned; reg slots_0_decoded_isLoad; reg slots_0_decoded_isStore; reg slots_0_decoded_isBranch; reg slots_0_decoded_isJal; reg slots_0_decoded_isJalr; reg slots_0_decoded_isLui; reg slots_0_decoded_isAuipc; reg slots_0_decoded_isOpImm; reg slots_0_decoded_isWord; reg slots_0_decoded_isSystem; reg slots_0_decoded_isFenceI; reg slots_0_decoded_isEcall; reg slots_0_decoded_isEbreak; reg slots_0_decoded_isMret; reg slots_0_decoded_isSret; reg slots_0_decoded_isSfenceVma; reg slots_0_decoded_isXret; reg slots_0_decoded_isWfi; reg slots_0_decoded_isAmo; reg [4:0] slots_0_decoded_amoOp; reg slots_0_decoded_writesRd; reg slots_0_decoded_illegal; reg slots_0_decoded_fetchException; reg [63:0] slots_0_decoded_fetchExceptionCause; reg [63:0] slots_0_decoded_fetchExceptionTval; reg [5:0] slots_0_prs1; reg [5:0] slots_0_prs2; reg slots_0_src1Ready; reg slots_0_src2Ready; reg [5:0] slots_0_prd; reg [5:0] slots_0_robIdx; reg [63:0] slots_1_decoded_pc; reg [31:0] slots_1_decoded_inst; reg [4:0] slots_1_decoded_rs1; reg [4:0] slots_1_decoded_rs2; reg [2:0] slots_1_decoded_funct3; reg [63:0] slots_1_decoded_immI; reg [63:0] slots_1_decoded_immS; reg [63:0] slots_1_decoded_immB; reg [63:0] slots_1_decoded_immU; reg [63:0] slots_1_decoded_immJ; reg [4:0] slots_1_decoded_aluFn; reg [2:0] slots_1_decoded_memWidth; reg slots_1_decoded_memSigned; reg slots_1_decoded_isLoad; reg slots_1_decoded_isStore; reg slots_1_decoded_isBranch; reg slots_1_decoded_isJal; reg slots_1_decoded_isJalr; reg slots_1_decoded_isLui; reg slots_1_decoded_isAuipc; reg slots_1_decoded_isOpImm; reg slots_1_decoded_isWord; reg slots_1_decoded_isSystem; reg slots_1_decoded_isFenceI; reg slots_1_decoded_isEcall; reg slots_1_decoded_isEbreak; reg slots_1_decoded_isMret; reg slots_1_decoded_isSret; reg slots_1_decoded_isSfenceVma; reg slots_1_decoded_isXret; reg slots_1_decoded_isWfi; reg slots_1_decoded_isAmo; reg [4:0] slots_1_decoded_amoOp; reg slots_1_decoded_writesRd; reg slots_1_decoded_illegal; reg slots_1_decoded_fetchException; reg [63:0] slots_1_decoded_fetchExceptionCause; reg [63:0] slots_1_decoded_fetchExceptionTval; reg [5:0] slots_1_prs1; reg [5:0] slots_1_prs2; reg slots_1_src1Ready; reg slots_1_src2Ready; reg [5:0] slots_1_prd; reg [5:0] slots_1_robIdx; reg [63:0] slots_2_decoded_pc; reg [31:0] slots_2_decoded_inst; reg [4:0] slots_2_decoded_rs1; reg [4:0] slots_2_decoded_rs2; reg [2:0] slots_2_decoded_funct3; reg [63:0] slots_2_decoded_immI; reg [63:0] slots_2_decoded_immS; reg [63:0] slots_2_decoded_immB; reg [63:0] slots_2_decoded_immU; reg [63:0] slots_2_decoded_immJ; reg [4:0] slots_2_decoded_aluFn; reg [2:0] slots_2_decoded_memWidth; reg slots_2_decoded_memSigned; reg slots_2_decoded_isLoad; reg slots_2_decoded_isStore; reg slots_2_decoded_isBranch; reg slots_2_decoded_isJal; reg slots_2_decoded_isJalr; reg slots_2_decoded_isLui; reg slots_2_decoded_isAuipc; reg slots_2_decoded_isOpImm; reg slots_2_decoded_isWord; reg slots_2_decoded_isSystem; reg slots_2_decoded_isFenceI; reg slots_2_decoded_isEcall; reg slots_2_decoded_isEbreak; reg slots_2_decoded_isMret; reg slots_2_decoded_isSret; reg slots_2_decoded_isSfenceVma; reg slots_2_decoded_isXret; reg slots_2_decoded_isWfi; reg slots_2_decoded_isAmo; reg [4:0] slots_2_decoded_amoOp; reg slots_2_decoded_writesRd; reg slots_2_decoded_illegal; reg slots_2_decoded_fetchException; reg [63:0] slots_2_decoded_fetchExceptionCause; reg [63:0] slots_2_decoded_fetchExceptionTval; reg [5:0] slots_2_prs1; reg [5:0] slots_2_prs2; reg slots_2_src1Ready; reg slots_2_src2Ready; reg [5:0] slots_2_prd; reg [5:0] slots_2_robIdx; reg [63:0] slots_3_decoded_pc; reg [31:0] slots_3_decoded_inst; reg [4:0] slots_3_decoded_rs1; reg [4:0] slots_3_decoded_rs2; reg [2:0] slots_3_decoded_funct3; reg [63:0] slots_3_decoded_immI; reg [63:0] slots_3_decoded_immS; reg [63:0] slots_3_decoded_immB; reg [63:0] slots_3_decoded_immU; reg [63:0] slots_3_decoded_immJ; reg [4:0] slots_3_decoded_aluFn; reg [2:0] slots_3_decoded_memWidth; reg slots_3_decoded_memSigned; reg slots_3_decoded_isLoad; reg slots_3_decoded_isStore; reg slots_3_decoded_isBranch; reg slots_3_decoded_isJal; reg slots_3_decoded_isJalr; reg slots_3_decoded_isLui; reg slots_3_decoded_isAuipc; reg slots_3_decoded_isOpImm; reg slots_3_decoded_isWord; reg slots_3_decoded_isSystem; reg slots_3_decoded_isFenceI; reg slots_3_decoded_isEcall; reg slots_3_decoded_isEbreak; reg slots_3_decoded_isMret; reg slots_3_decoded_isSret; reg slots_3_decoded_isSfenceVma; reg slots_3_decoded_isXret; reg slots_3_decoded_isWfi; reg slots_3_decoded_isAmo; reg [4:0] slots_3_decoded_amoOp; reg slots_3_decoded_writesRd; reg slots_3_decoded_illegal; reg slots_3_decoded_fetchException; reg [63:0] slots_3_decoded_fetchExceptionCause; reg [63:0] slots_3_decoded_fetchExceptionTval; reg [5:0] slots_3_prs1; reg [5:0] slots_3_prs2; reg slots_3_src1Ready; reg slots_3_src2Ready; reg [5:0] slots_3_prd; reg [5:0] slots_3_robIdx; reg [63:0] slots_4_decoded_pc; reg [31:0] slots_4_decoded_inst; reg [4:0] slots_4_decoded_rs1; reg [4:0] slots_4_decoded_rs2; reg [2:0] slots_4_decoded_funct3; reg [63:0] slots_4_decoded_immI; reg [63:0] slots_4_decoded_immS; reg [63:0] slots_4_decoded_immB; reg [63:0] slots_4_decoded_immU; reg [63:0] slots_4_decoded_immJ; reg [4:0] slots_4_decoded_aluFn; reg [2:0] slots_4_decoded_memWidth; reg slots_4_decoded_memSigned; reg slots_4_decoded_isLoad; reg slots_4_decoded_isStore; reg slots_4_decoded_isBranch; reg slots_4_decoded_isJal; reg slots_4_decoded_isJalr; reg slots_4_decoded_isLui; reg slots_4_decoded_isAuipc; reg slots_4_decoded_isOpImm; reg slots_4_decoded_isWord; reg slots_4_decoded_isSystem; reg slots_4_decoded_isFenceI; reg slots_4_decoded_isEcall; reg slots_4_decoded_isEbreak; reg slots_4_decoded_isMret; reg slots_4_decoded_isSret; reg slots_4_decoded_isSfenceVma; reg slots_4_decoded_isXret; reg slots_4_decoded_isWfi; reg slots_4_decoded_isAmo; reg [4:0] slots_4_decoded_amoOp; reg slots_4_decoded_writesRd; reg slots_4_decoded_illegal; reg slots_4_decoded_fetchException; reg [63:0] slots_4_decoded_fetchExceptionCause; reg [63:0] slots_4_decoded_fetchExceptionTval; reg [5:0] slots_4_prs1; reg [5:0] slots_4_prs2; reg slots_4_src1Ready; reg slots_4_src2Ready; reg [5:0] slots_4_prd; reg [5:0] slots_4_robIdx; reg [63:0] slots_5_decoded_pc; reg [31:0] slots_5_decoded_inst; reg [4:0] slots_5_decoded_rs1; reg [4:0] slots_5_decoded_rs2; reg [2:0] slots_5_decoded_funct3; reg [63:0] slots_5_decoded_immI; reg [63:0] slots_5_decoded_immS; reg [63:0] slots_5_decoded_immB; reg [63:0] slots_5_decoded_immU; reg [63:0] slots_5_decoded_immJ; reg [4:0] slots_5_decoded_aluFn; reg [2:0] slots_5_decoded_memWidth; reg slots_5_decoded_memSigned; reg slots_5_decoded_isLoad; reg slots_5_decoded_isStore; reg slots_5_decoded_isBranch; reg slots_5_decoded_isJal; reg slots_5_decoded_isJalr; reg slots_5_decoded_isLui; reg slots_5_decoded_isAuipc; reg slots_5_decoded_isOpImm; reg slots_5_decoded_isWord; reg slots_5_decoded_isSystem; reg slots_5_decoded_isFenceI; reg slots_5_decoded_isEcall; reg slots_5_decoded_isEbreak; reg slots_5_decoded_isMret; reg slots_5_decoded_isSret; reg slots_5_decoded_isSfenceVma; reg slots_5_decoded_isXret; reg slots_5_decoded_isWfi; reg slots_5_decoded_isAmo; reg [4:0] slots_5_decoded_amoOp; reg slots_5_decoded_writesRd; reg slots_5_decoded_illegal; reg slots_5_decoded_fetchException; reg [63:0] slots_5_decoded_fetchExceptionCause; reg [63:0] slots_5_decoded_fetchExceptionTval; reg [5:0] slots_5_prs1; reg [5:0] slots_5_prs2; reg slots_5_src1Ready; reg slots_5_src2Ready; reg [5:0] slots_5_prd; reg [5:0] slots_5_robIdx; reg [63:0] slots_6_decoded_pc; reg [31:0] slots_6_decoded_inst; reg [4:0] slots_6_decoded_rs1; reg [4:0] slots_6_decoded_rs2; reg [2:0] slots_6_decoded_funct3; reg [63:0] slots_6_decoded_immI; reg [63:0] slots_6_decoded_immS; reg [63:0] slots_6_decoded_immB; reg [63:0] slots_6_decoded_immU; reg [63:0] slots_6_decoded_immJ; reg [4:0] slots_6_decoded_aluFn; reg [2:0] slots_6_decoded_memWidth; reg slots_6_decoded_memSigned; reg slots_6_decoded_isLoad; reg slots_6_decoded_isStore; reg slots_6_decoded_isBranch; reg slots_6_decoded_isJal; reg slots_6_decoded_isJalr; reg slots_6_decoded_isLui; reg slots_6_decoded_isAuipc; reg slots_6_decoded_isOpImm; reg slots_6_decoded_isWord; reg slots_6_decoded_isSystem; reg slots_6_decoded_isFenceI; reg slots_6_decoded_isEcall; reg slots_6_decoded_isEbreak; reg slots_6_decoded_isMret; reg slots_6_decoded_isSret; reg slots_6_decoded_isSfenceVma; reg slots_6_decoded_isXret; reg slots_6_decoded_isWfi; reg slots_6_decoded_isAmo; reg [4:0] slots_6_decoded_amoOp; reg slots_6_decoded_writesRd; reg slots_6_decoded_illegal; reg slots_6_decoded_fetchException; reg [63:0] slots_6_decoded_fetchExceptionCause; reg [63:0] slots_6_decoded_fetchExceptionTval; reg [5:0] slots_6_prs1; reg [5:0] slots_6_prs2; reg slots_6_src1Ready; reg slots_6_src2Ready; reg [5:0] slots_6_prd; reg [5:0] slots_6_robIdx; reg [63:0] slots_7_decoded_pc; reg [31:0] slots_7_decoded_inst; reg [4:0] slots_7_decoded_rs1; reg [4:0] slots_7_decoded_rs2; reg [2:0] slots_7_decoded_funct3; reg [63:0] slots_7_decoded_immI; reg [63:0] slots_7_decoded_immS; reg [63:0] slots_7_decoded_immB; reg [63:0] slots_7_decoded_immU; reg [63:0] slots_7_decoded_immJ; reg [4:0] slots_7_decoded_aluFn; reg [2:0] slots_7_decoded_memWidth; reg slots_7_decoded_memSigned; reg slots_7_decoded_isLoad; reg slots_7_decoded_isStore; reg slots_7_decoded_isBranch; reg slots_7_decoded_isJal; reg slots_7_decoded_isJalr; reg slots_7_decoded_isLui; reg slots_7_decoded_isAuipc; reg slots_7_decoded_isOpImm; reg slots_7_decoded_isWord; reg slots_7_decoded_isSystem; reg slots_7_decoded_isFenceI; reg slots_7_decoded_isEcall; reg slots_7_decoded_isEbreak; reg slots_7_decoded_isMret; reg slots_7_decoded_isSret; reg slots_7_decoded_isSfenceVma; reg slots_7_decoded_isXret; reg slots_7_decoded_isWfi; reg slots_7_decoded_isAmo; reg [4:0] slots_7_decoded_amoOp; reg slots_7_decoded_writesRd; reg slots_7_decoded_illegal; reg slots_7_decoded_fetchException; reg [63:0] slots_7_decoded_fetchExceptionCause; reg [63:0] slots_7_decoded_fetchExceptionTval; reg [5:0] slots_7_prs1; reg [5:0] slots_7_prs2; reg slots_7_src1Ready; reg slots_7_src2Ready; reg [5:0] slots_7_prd; reg [5:0] slots_7_robIdx; reg [63:0] slots_8_decoded_pc; reg [31:0] slots_8_decoded_inst; reg [4:0] slots_8_decoded_rs1; reg [4:0] slots_8_decoded_rs2; reg [2:0] slots_8_decoded_funct3; reg [63:0] slots_8_decoded_immI; reg [63:0] slots_8_decoded_immS; reg [63:0] slots_8_decoded_immB; reg [63:0] slots_8_decoded_immU; reg [63:0] slots_8_decoded_immJ; reg [4:0] slots_8_decoded_aluFn; reg [2:0] slots_8_decoded_memWidth; reg slots_8_decoded_memSigned; reg slots_8_decoded_isLoad; reg slots_8_decoded_isStore; reg slots_8_decoded_isBranch; reg slots_8_decoded_isJal; reg slots_8_decoded_isJalr; reg slots_8_decoded_isLui; reg slots_8_decoded_isAuipc; reg slots_8_decoded_isOpImm; reg slots_8_decoded_isWord; reg slots_8_decoded_isSystem; reg slots_8_decoded_isFenceI; reg slots_8_decoded_isEcall; reg slots_8_decoded_isEbreak; reg slots_8_decoded_isMret; reg slots_8_decoded_isSret; reg slots_8_decoded_isSfenceVma; reg slots_8_decoded_isXret; reg slots_8_decoded_isWfi; reg slots_8_decoded_isAmo; reg [4:0] slots_8_decoded_amoOp; reg slots_8_decoded_writesRd; reg slots_8_decoded_illegal; reg slots_8_decoded_fetchException; reg [63:0] slots_8_decoded_fetchExceptionCause; reg [63:0] slots_8_decoded_fetchExceptionTval; reg [5:0] slots_8_prs1; reg [5:0] slots_8_prs2; reg slots_8_src1Ready; reg slots_8_src2Ready; reg [5:0] slots_8_prd; reg [5:0] slots_8_robIdx; reg [63:0] slots_9_decoded_pc; reg [31:0] slots_9_decoded_inst; reg [4:0] slots_9_decoded_rs1; reg [4:0] slots_9_decoded_rs2; reg [2:0] slots_9_decoded_funct3; reg [63:0] slots_9_decoded_immI; reg [63:0] slots_9_decoded_immS; reg [63:0] slots_9_decoded_immB; reg [63:0] slots_9_decoded_immU; reg [63:0] slots_9_decoded_immJ; reg [4:0] slots_9_decoded_aluFn; reg [2:0] slots_9_decoded_memWidth; reg slots_9_decoded_memSigned; reg slots_9_decoded_isLoad; reg slots_9_decoded_isStore; reg slots_9_decoded_isBranch; reg slots_9_decoded_isJal; reg slots_9_decoded_isJalr; reg slots_9_decoded_isLui; reg slots_9_decoded_isAuipc; reg slots_9_decoded_isOpImm; reg slots_9_decoded_isWord; reg slots_9_decoded_isSystem; reg slots_9_decoded_isFenceI; reg slots_9_decoded_isEcall; reg slots_9_decoded_isEbreak; reg slots_9_decoded_isMret; reg slots_9_decoded_isSret; reg slots_9_decoded_isSfenceVma; reg slots_9_decoded_isXret; reg slots_9_decoded_isWfi; reg slots_9_decoded_isAmo; reg [4:0] slots_9_decoded_amoOp; reg slots_9_decoded_writesRd; reg slots_9_decoded_illegal; reg slots_9_decoded_fetchException; reg [63:0] slots_9_decoded_fetchExceptionCause; reg [63:0] slots_9_decoded_fetchExceptionTval; reg [5:0] slots_9_prs1; reg [5:0] slots_9_prs2; reg slots_9_src1Ready; reg slots_9_src2Ready; reg [5:0] slots_9_prd; reg [5:0] slots_9_robIdx; reg [63:0] slots_10_decoded_pc; reg [31:0] slots_10_decoded_inst; reg [4:0] slots_10_decoded_rs1; reg [4:0] slots_10_decoded_rs2; reg [2:0] slots_10_decoded_funct3; reg [63:0] slots_10_decoded_immI; reg [63:0] slots_10_decoded_immS; reg [63:0] slots_10_decoded_immB; reg [63:0] slots_10_decoded_immU; reg [63:0] slots_10_decoded_immJ; reg [4:0] slots_10_decoded_aluFn; reg [2:0] slots_10_decoded_memWidth; reg slots_10_decoded_memSigned; reg slots_10_decoded_isLoad; reg slots_10_decoded_isStore; reg slots_10_decoded_isBranch; reg slots_10_decoded_isJal; reg slots_10_decoded_isJalr; reg slots_10_decoded_isLui; reg slots_10_decoded_isAuipc; reg slots_10_decoded_isOpImm; reg slots_10_decoded_isWord; reg slots_10_decoded_isSystem; reg slots_10_decoded_isFenceI; reg slots_10_decoded_isEcall; reg slots_10_decoded_isEbreak; reg slots_10_decoded_isMret; reg slots_10_decoded_isSret; reg slots_10_decoded_isSfenceVma; reg slots_10_decoded_isXret; reg slots_10_decoded_isWfi; reg slots_10_decoded_isAmo; reg [4:0] slots_10_decoded_amoOp; reg slots_10_decoded_writesRd; reg slots_10_decoded_illegal; reg slots_10_decoded_fetchException; reg [63:0] slots_10_decoded_fetchExceptionCause; reg [63:0] slots_10_decoded_fetchExceptionTval; reg [5:0] slots_10_prs1; reg [5:0] slots_10_prs2; reg slots_10_src1Ready; reg slots_10_src2Ready; reg [5:0] slots_10_prd; reg [5:0] slots_10_robIdx; reg [63:0] slots_11_decoded_pc; reg [31:0] slots_11_decoded_inst; reg [4:0] slots_11_decoded_rs1; reg [4:0] slots_11_decoded_rs2; reg [2:0] slots_11_decoded_funct3; reg [63:0] slots_11_decoded_immI; reg [63:0] slots_11_decoded_immS; reg [63:0] slots_11_decoded_immB; reg [63:0] slots_11_decoded_immU; reg [63:0] slots_11_decoded_immJ; reg [4:0] slots_11_decoded_aluFn; reg [2:0] slots_11_decoded_memWidth; reg slots_11_decoded_memSigned; reg slots_11_decoded_isLoad; reg slots_11_decoded_isStore; reg slots_11_decoded_isBranch; reg slots_11_decoded_isJal; reg slots_11_decoded_isJalr; reg slots_11_decoded_isLui; reg slots_11_decoded_isAuipc; reg slots_11_decoded_isOpImm; reg slots_11_decoded_isWord; reg slots_11_decoded_isSystem; reg slots_11_decoded_isFenceI; reg slots_11_decoded_isEcall; reg slots_11_decoded_isEbreak; reg slots_11_decoded_isMret; reg slots_11_decoded_isSret; reg slots_11_decoded_isSfenceVma; reg slots_11_decoded_isXret; reg slots_11_decoded_isWfi; reg slots_11_decoded_isAmo; reg [4:0] slots_11_decoded_amoOp; reg slots_11_decoded_writesRd; reg slots_11_decoded_illegal; reg slots_11_decoded_fetchException; reg [63:0] slots_11_decoded_fetchExceptionCause; reg [63:0] slots_11_decoded_fetchExceptionTval; reg [5:0] slots_11_prs1; reg [5:0] slots_11_prs2; reg slots_11_src1Ready; reg slots_11_src2Ready; reg [5:0] slots_11_prd; reg [5:0] slots_11_robIdx; reg [63:0] slots_12_decoded_pc; reg [31:0] slots_12_decoded_inst; reg [4:0] slots_12_decoded_rs1; reg [4:0] slots_12_decoded_rs2; reg [2:0] slots_12_decoded_funct3; reg [63:0] slots_12_decoded_immI; reg [63:0] slots_12_decoded_immS; reg [63:0] slots_12_decoded_immB; reg [63:0] slots_12_decoded_immU; reg [63:0] slots_12_decoded_immJ; reg [4:0] slots_12_decoded_aluFn; reg [2:0] slots_12_decoded_memWidth; reg slots_12_decoded_memSigned; reg slots_12_decoded_isLoad; reg slots_12_decoded_isStore; reg slots_12_decoded_isBranch; reg slots_12_decoded_isJal; reg slots_12_decoded_isJalr; reg slots_12_decoded_isLui; reg slots_12_decoded_isAuipc; reg slots_12_decoded_isOpImm; reg slots_12_decoded_isWord; reg slots_12_decoded_isSystem; reg slots_12_decoded_isFenceI; reg slots_12_decoded_isEcall; reg slots_12_decoded_isEbreak; reg slots_12_decoded_isMret; reg slots_12_decoded_isSret; reg slots_12_decoded_isSfenceVma; reg slots_12_decoded_isXret; reg slots_12_decoded_isWfi; reg slots_12_decoded_isAmo; reg [4:0] slots_12_decoded_amoOp; reg slots_12_decoded_writesRd; reg slots_12_decoded_illegal; reg slots_12_decoded_fetchException; reg [63:0] slots_12_decoded_fetchExceptionCause; reg [63:0] slots_12_decoded_fetchExceptionTval; reg [5:0] slots_12_prs1; reg [5:0] slots_12_prs2; reg slots_12_src1Ready; reg slots_12_src2Ready; reg [5:0] slots_12_prd; reg [5:0] slots_12_robIdx; reg [63:0] slots_13_decoded_pc; reg [31:0] slots_13_decoded_inst; reg [4:0] slots_13_decoded_rs1; reg [4:0] slots_13_decoded_rs2; reg [2:0] slots_13_decoded_funct3; reg [63:0] slots_13_decoded_immI; reg [63:0] slots_13_decoded_immS; reg [63:0] slots_13_decoded_immB; reg [63:0] slots_13_decoded_immU; reg [63:0] slots_13_decoded_immJ; reg [4:0] slots_13_decoded_aluFn; reg [2:0] slots_13_decoded_memWidth; reg slots_13_decoded_memSigned; reg slots_13_decoded_isLoad; reg slots_13_decoded_isStore; reg slots_13_decoded_isBranch; reg slots_13_decoded_isJal; reg slots_13_decoded_isJalr; reg slots_13_decoded_isLui; reg slots_13_decoded_isAuipc; reg slots_13_decoded_isOpImm; reg slots_13_decoded_isWord; reg slots_13_decoded_isSystem; reg slots_13_decoded_isFenceI; reg slots_13_decoded_isEcall; reg slots_13_decoded_isEbreak; reg slots_13_decoded_isMret; reg slots_13_decoded_isSret; reg slots_13_decoded_isSfenceVma; reg slots_13_decoded_isXret; reg slots_13_decoded_isWfi; reg slots_13_decoded_isAmo; reg [4:0] slots_13_decoded_amoOp; reg slots_13_decoded_writesRd; reg slots_13_decoded_illegal; reg slots_13_decoded_fetchException; reg [63:0] slots_13_decoded_fetchExceptionCause; reg [63:0] slots_13_decoded_fetchExceptionTval; reg [5:0] slots_13_prs1; reg [5:0] slots_13_prs2; reg slots_13_src1Ready; reg slots_13_src2Ready; reg [5:0] slots_13_prd; reg [5:0] slots_13_robIdx; reg [63:0] slots_14_decoded_pc; reg [31:0] slots_14_decoded_inst; reg [4:0] slots_14_decoded_rs1; reg [4:0] slots_14_decoded_rs2; reg [2:0] slots_14_decoded_funct3; reg [63:0] slots_14_decoded_immI; reg [63:0] slots_14_decoded_immS; reg [63:0] slots_14_decoded_immB; reg [63:0] slots_14_decoded_immU; reg [63:0] slots_14_decoded_immJ; reg [4:0] slots_14_decoded_aluFn; reg [2:0] slots_14_decoded_memWidth; reg slots_14_decoded_memSigned; reg slots_14_decoded_isLoad; reg slots_14_decoded_isStore; reg slots_14_decoded_isBranch; reg slots_14_decoded_isJal; reg slots_14_decoded_isJalr; reg slots_14_decoded_isLui; reg slots_14_decoded_isAuipc; reg slots_14_decoded_isOpImm; reg slots_14_decoded_isWord; reg slots_14_decoded_isSystem; reg slots_14_decoded_isFenceI; reg slots_14_decoded_isEcall; reg slots_14_decoded_isEbreak; reg slots_14_decoded_isMret; reg slots_14_decoded_isSret; reg slots_14_decoded_isSfenceVma; reg slots_14_decoded_isXret; reg slots_14_decoded_isWfi; reg slots_14_decoded_isAmo; reg [4:0] slots_14_decoded_amoOp; reg slots_14_decoded_writesRd; reg slots_14_decoded_illegal; reg slots_14_decoded_fetchException; reg [63:0] slots_14_decoded_fetchExceptionCause; reg [63:0] slots_14_decoded_fetchExceptionTval; reg [5:0] slots_14_prs1; reg [5:0] slots_14_prs2; reg slots_14_src1Ready; reg slots_14_src2Ready; reg [5:0] slots_14_prd; reg [5:0] slots_14_robIdx; reg [63:0] slots_15_decoded_pc; reg [31:0] slots_15_decoded_inst; reg [4:0] slots_15_decoded_rs1; reg [4:0] slots_15_decoded_rs2; reg [2:0] slots_15_decoded_funct3; reg [63:0] slots_15_decoded_immI; reg [63:0] slots_15_decoded_immS; reg [63:0] slots_15_decoded_immB; reg [63:0] slots_15_decoded_immU; reg [63:0] slots_15_decoded_immJ; reg [4:0] slots_15_decoded_aluFn; reg [2:0] slots_15_decoded_memWidth; reg slots_15_decoded_memSigned; reg slots_15_decoded_isLoad; reg slots_15_decoded_isStore; reg slots_15_decoded_isBranch; reg slots_15_decoded_isJal; reg slots_15_decoded_isJalr; reg slots_15_decoded_isLui; reg slots_15_decoded_isAuipc; reg slots_15_decoded_isOpImm; reg slots_15_decoded_isWord; reg slots_15_decoded_isSystem; reg slots_15_decoded_isFenceI; reg slots_15_decoded_isEcall; reg slots_15_decoded_isEbreak; reg slots_15_decoded_isMret; reg slots_15_decoded_isSret; reg slots_15_decoded_isSfenceVma; reg slots_15_decoded_isXret; reg slots_15_decoded_isWfi; reg slots_15_decoded_isAmo; reg [4:0] slots_15_decoded_amoOp; reg slots_15_decoded_writesRd; reg slots_15_decoded_illegal; reg slots_15_decoded_fetchException; reg [63:0] slots_15_decoded_fetchExceptionCause; reg [63:0] slots_15_decoded_fetchExceptionTval; reg [5:0] slots_15_prs1; reg [5:0] slots_15_prs2; reg slots_15_src1Ready; reg slots_15_src2Ready; reg [5:0] slots_15_prd; reg [5:0] slots_15_robIdx; wire [15:0] freeMask = {~valid_15, ~valid_14, ~valid_13, ~valid_12, ~valid_11, ~valid_10, ~valid_9, ~valid_8, ~valid_7, ~valid_6, ~valid_5, ~valid_4, ~valid_3, ~valid_2, ~valid_1, ~valid_0}; wire [15:0] enq0OH = valid_0 ? (valid_1 ? (valid_2 ? (valid_3 ? (valid_4 ? (valid_5 ? (valid_6 ? (valid_7 ? (valid_8 ? (valid_9 ? (valid_10 ? (valid_11 ? (valid_12 ? (valid_13 ? (valid_14 ? {~valid_15, 15'h0} : 16'h4000) : 16'h2000) : 16'h1000) : 16'h800) : 16'h400) : 16'h200) : 16'h100) : 16'h80) : 16'h40) : 16'h20) : 16'h10) : 16'h8) : 16'h4) : 16'h2) : 16'h1; wire [15:0] _io_enqReady_1_T = ~enq0OH; wire [15:0] _io_enqReady_1_T_1 = freeMask & _io_enqReady_1_T; wire _src1Wake_T = io_wakeup_0_phys == slots_0_prs1; wire _src1Wake_T_2 = io_wakeup_1_phys == slots_0_prs1; wire _src2Wake_T = io_wakeup_0_phys == slots_0_prs2; wire _src2Wake_T_2 = io_wakeup_1_phys == slots_0_prs2; wire _olderStorePending_T_1455 = valid_0 & slots_0_decoded_isStore; wire _olderStorePending_T_1461 = valid_1 & slots_1_decoded_isStore; wire [5:0] _olderStorePending_diff_T_1 = slots_0_robIdx - slots_1_robIdx; wire _olderStorePending_T_1467 = valid_2 & slots_2_decoded_isStore; wire [5:0] _olderStorePending_diff_T_2 = slots_0_robIdx - slots_2_robIdx; wire _olderStorePending_T_1473 = valid_3 & slots_3_decoded_isStore; wire [5:0] _olderStorePending_diff_T_3 = slots_0_robIdx - slots_3_robIdx; wire _olderStorePending_T_1479 = valid_4 & slots_4_decoded_isStore; wire [5:0] _olderStorePending_diff_T_4 = slots_0_robIdx - slots_4_robIdx; wire _olderStorePending_T_1485 = valid_5 & slots_5_decoded_isStore; wire [5:0] _olderStorePending_diff_T_5 = slots_0_robIdx - slots_5_robIdx; wire _olderStorePending_T_1491 = valid_6 & slots_6_decoded_isStore; wire [5:0] _olderStorePending_diff_T_6 = slots_0_robIdx - slots_6_robIdx; wire _olderStorePending_T_1497 = valid_7 & slots_7_decoded_isStore; wire [5:0] _olderStorePending_diff_T_7 = slots_0_robIdx - slots_7_robIdx; wire _olderStorePending_T_1503 = valid_8 & slots_8_decoded_isStore; wire [5:0] _olderStorePending_diff_T_8 = slots_0_robIdx - slots_8_robIdx; wire _olderStorePending_T_1509 = valid_9 & slots_9_decoded_isStore; wire [5:0] _olderStorePending_diff_T_9 = slots_0_robIdx - slots_9_robIdx; wire _olderStorePending_T_1515 = valid_10 & slots_10_decoded_isStore; wire [5:0] _olderStorePending_diff_T_10 = slots_0_robIdx - slots_10_robIdx; wire _olderStorePending_T_1521 = valid_11 & slots_11_decoded_isStore; wire [5:0] _olderStorePending_diff_T_11 = slots_0_robIdx - slots_11_robIdx; wire _olderStorePending_T_1527 = valid_12 & slots_12_decoded_isStore; wire [5:0] _olderStorePending_diff_T_12 = slots_0_robIdx - slots_12_robIdx; wire _olderStorePending_T_1533 = valid_13 & slots_13_decoded_isStore; wire [5:0] _olderStorePending_diff_T_13 = slots_0_robIdx - slots_13_robIdx; wire _olderStorePending_T_1539 = valid_14 & slots_14_decoded_isStore; wire [5:0] _olderStorePending_diff_T_14 = slots_0_robIdx - slots_14_robIdx; wire _olderStorePending_T_1545 = valid_15 & slots_15_decoded_isStore; wire [5:0] _olderStorePending_diff_T_15 = slots_0_robIdx - slots_15_robIdx; wire readyVec_0 = valid_0 & (slots_0_src1Ready | io_wakeup_0_valid & _src1Wake_T | io_wakeup_1_valid & _src1Wake_T_2 | slots_0_decoded_rs1 == 5'h0) & (slots_0_src2Ready | io_wakeup_0_valid & _src2Wake_T | io_wakeup_1_valid & _src2Wake_T_2 | slots_0_decoded_rs2 == 5'h0) & ~((slots_0_decoded_isLoad | slots_0_decoded_isAmo) & (|{_olderStorePending_T_1545 & (|_olderStorePending_diff_T_15) & ~(_olderStorePending_diff_T_15[5]), _olderStorePending_T_1539 & (|_olderStorePending_diff_T_14) & ~(_olderStorePending_diff_T_14[5]), _olderStorePending_T_1533 & (|_olderStorePending_diff_T_13) & ~(_olderStorePending_diff_T_13[5]), _olderStorePending_T_1527 & (|_olderStorePending_diff_T_12) & ~(_olderStorePending_diff_T_12[5]), _olderStorePending_T_1521 & (|_olderStorePending_diff_T_11) & ~(_olderStorePending_diff_T_11[5]), _olderStorePending_T_1515 & (|_olderStorePending_diff_T_10) & ~(_olderStorePending_diff_T_10[5]), _olderStorePending_T_1509 & (|_olderStorePending_diff_T_9) & ~(_olderStorePending_diff_T_9[5]), _olderStorePending_T_1503 & (|_olderStorePending_diff_T_8) & ~(_olderStorePending_diff_T_8[5]), _olderStorePending_T_1497 & (|_olderStorePending_diff_T_7) & ~(_olderStorePending_diff_T_7[5]), _olderStorePending_T_1491 & (|_olderStorePending_diff_T_6) & ~(_olderStorePending_diff_T_6[5]), _olderStorePending_T_1485 & (|_olderStorePending_diff_T_5) & ~(_olderStorePending_diff_T_5[5]), _olderStorePending_T_1479 & (|_olderStorePending_diff_T_4) & ~(_olderStorePending_diff_T_4[5]), _olderStorePending_T_1473 & (|_olderStorePending_diff_T_3) & ~(_olderStorePending_diff_T_3[5]), _olderStorePending_T_1467 & (|_olderStorePending_diff_T_2) & ~(_olderStorePending_diff_T_2[5]), _olderStorePending_T_1461 & (|_olderStorePending_diff_T_1) & ~(_olderStorePending_diff_T_1[5])})) & (~(slots_0_decoded_isSystem | slots_0_decoded_isFenceI | slots_0_decoded_isSfenceVma | slots_0_decoded_isWfi) | io_robHeadValid & slots_0_robIdx == io_robHeadIdx); wire _src1Wake_T_4 = io_wakeup_0_phys == slots_1_prs1; wire _src1Wake_T_6 = io_wakeup_1_phys == slots_1_prs1; wire _src2Wake_T_4 = io_wakeup_0_phys == slots_1_prs2; wire _src2Wake_T_6 = io_wakeup_1_phys == slots_1_prs2; wire [5:0] _olderStorePending_diff_T_16 = slots_1_robIdx - slots_0_robIdx; wire [5:0] _olderStorePending_diff_T_18 = slots_1_robIdx - slots_2_robIdx; wire [5:0] _olderStorePending_diff_T_19 = slots_1_robIdx - slots_3_robIdx; wire [5:0] _olderStorePending_diff_T_20 = slots_1_robIdx - slots_4_robIdx; wire [5:0] _olderStorePending_diff_T_21 = slots_1_robIdx - slots_5_robIdx; wire [5:0] _olderStorePending_diff_T_22 = slots_1_robIdx - slots_6_robIdx; wire [5:0] _olderStorePending_diff_T_23 = slots_1_robIdx - slots_7_robIdx; wire [5:0] _olderStorePending_diff_T_24 = slots_1_robIdx - slots_8_robIdx; wire [5:0] _olderStorePending_diff_T_25 = slots_1_robIdx - slots_9_robIdx; wire [5:0] _olderStorePending_diff_T_26 = slots_1_robIdx - slots_10_robIdx; wire [5:0] _olderStorePending_diff_T_27 = slots_1_robIdx - slots_11_robIdx; wire [5:0] _olderStorePending_diff_T_28 = slots_1_robIdx - slots_12_robIdx; wire [5:0] _olderStorePending_diff_T_29 = slots_1_robIdx - slots_13_robIdx; wire [5:0] _olderStorePending_diff_T_30 = slots_1_robIdx - slots_14_robIdx; wire [5:0] _olderStorePending_diff_T_31 = slots_1_robIdx - slots_15_robIdx; wire readyVec_1 = valid_1 & (slots_1_src1Ready | io_wakeup_0_valid & _src1Wake_T_4 | io_wakeup_1_valid & _src1Wake_T_6 | slots_1_decoded_rs1 == 5'h0) & (slots_1_src2Ready | io_wakeup_0_valid & _src2Wake_T_4 | io_wakeup_1_valid & _src2Wake_T_6 | slots_1_decoded_rs2 == 5'h0) & ~((slots_1_decoded_isLoad | slots_1_decoded_isAmo) & (|{_olderStorePending_T_1545 & (|_olderStorePending_diff_T_31) & ~(_olderStorePending_diff_T_31[5]), _olderStorePending_T_1539 & (|_olderStorePending_diff_T_30) & ~(_olderStorePending_diff_T_30[5]), _olderStorePending_T_1533 & (|_olderStorePending_diff_T_29) & ~(_olderStorePending_diff_T_29[5]), _olderStorePending_T_1527 & (|_olderStorePending_diff_T_28) & ~(_olderStorePending_diff_T_28[5]), _olderStorePending_T_1521 & (|_olderStorePending_diff_T_27) & ~(_olderStorePending_diff_T_27[5]), _olderStorePending_T_1515 & (|_olderStorePending_diff_T_26) & ~(_olderStorePending_diff_T_26[5]), _olderStorePending_T_1509 & (|_olderStorePending_diff_T_25) & ~(_olderStorePending_diff_T_25[5]), _olderStorePending_T_1503 & (|_olderStorePending_diff_T_24) & ~(_olderStorePending_diff_T_24[5]), _olderStorePending_T_1497 & (|_olderStorePending_diff_T_23) & ~(_olderStorePending_diff_T_23[5]), _olderStorePending_T_1491 & (|_olderStorePending_diff_T_22) & ~(_olderStorePending_diff_T_22[5]), _olderStorePending_T_1485 & (|_olderStorePending_diff_T_21) & ~(_olderStorePending_diff_T_21[5]), _olderStorePending_T_1479 & (|_olderStorePending_diff_T_20) & ~(_olderStorePending_diff_T_20[5]), _olderStorePending_T_1473 & (|_olderStorePending_diff_T_19) & ~(_olderStorePending_diff_T_19[5]), _olderStorePending_T_1467 & (|_olderStorePending_diff_T_18) & ~(_olderStorePending_diff_T_18[5]), _olderStorePending_T_1455 & (|_olderStorePending_diff_T_16) & ~(_olderStorePending_diff_T_16[5])})) & (~(slots_1_decoded_isSystem | slots_1_decoded_isFenceI | slots_1_decoded_isSfenceVma | slots_1_decoded_isWfi) | io_robHeadValid & slots_1_robIdx == io_robHeadIdx); wire _src1Wake_T_8 = io_wakeup_0_phys == slots_2_prs1; wire _src1Wake_T_10 = io_wakeup_1_phys == slots_2_prs1; wire _src2Wake_T_8 = io_wakeup_0_phys == slots_2_prs2; wire _src2Wake_T_10 = io_wakeup_1_phys == slots_2_prs2; wire [5:0] _olderStorePending_diff_T_32 = slots_2_robIdx - slots_0_robIdx; wire [5:0] _olderStorePending_diff_T_33 = slots_2_robIdx - slots_1_robIdx; wire [5:0] _olderStorePending_diff_T_35 = slots_2_robIdx - slots_3_robIdx; wire [5:0] _olderStorePending_diff_T_36 = slots_2_robIdx - slots_4_robIdx; wire [5:0] _olderStorePending_diff_T_37 = slots_2_robIdx - slots_5_robIdx; wire [5:0] _olderStorePending_diff_T_38 = slots_2_robIdx - slots_6_robIdx; wire [5:0] _olderStorePending_diff_T_39 = slots_2_robIdx - slots_7_robIdx; wire [5:0] _olderStorePending_diff_T_40 = slots_2_robIdx - slots_8_robIdx; wire [5:0] _olderStorePending_diff_T_41 = slots_2_robIdx - slots_9_robIdx; wire [5:0] _olderStorePending_diff_T_42 = slots_2_robIdx - slots_10_robIdx; wire [5:0] _olderStorePending_diff_T_43 = slots_2_robIdx - slots_11_robIdx; wire [5:0] _olderStorePending_diff_T_44 = slots_2_robIdx - slots_12_robIdx; wire [5:0] _olderStorePending_diff_T_45 = slots_2_robIdx - slots_13_robIdx; wire [5:0] _olderStorePending_diff_T_46 = slots_2_robIdx - slots_14_robIdx; wire [5:0] _olderStorePending_diff_T_47 = slots_2_robIdx - slots_15_robIdx; wire readyVec_2 = valid_2 & (slots_2_src1Ready | io_wakeup_0_valid & _src1Wake_T_8 | io_wakeup_1_valid & _src1Wake_T_10 | slots_2_decoded_rs1 == 5'h0) & (slots_2_src2Ready | io_wakeup_0_valid & _src2Wake_T_8 | io_wakeup_1_valid & _src2Wake_T_10 | slots_2_decoded_rs2 == 5'h0) & ~((slots_2_decoded_isLoad | slots_2_decoded_isAmo) & (|{_olderStorePending_T_1545 & (|_olderStorePending_diff_T_47) & ~(_olderStorePending_diff_T_47[5]), _olderStorePending_T_1539 & (|_olderStorePending_diff_T_46) & ~(_olderStorePending_diff_T_46[5]), _olderStorePending_T_1533 & (|_olderStorePending_diff_T_45) & ~(_olderStorePending_diff_T_45[5]), _olderStorePending_T_1527 & (|_olderStorePending_diff_T_44) & ~(_olderStorePending_diff_T_44[5]), _olderStorePending_T_1521 & (|_olderStorePending_diff_T_43) & ~(_olderStorePending_diff_T_43[5]), _olderStorePending_T_1515 & (|_olderStorePending_diff_T_42) & ~(_olderStorePending_diff_T_42[5]), _olderStorePending_T_1509 & (|_olderStorePending_diff_T_41) & ~(_olderStorePending_diff_T_41[5]), _olderStorePending_T_1503 & (|_olderStorePending_diff_T_40) & ~(_olderStorePending_diff_T_40[5]), _olderStorePending_T_1497 & (|_olderStorePending_diff_T_39) & ~(_olderStorePending_diff_T_39[5]), _olderStorePending_T_1491 & (|_olderStorePending_diff_T_38) & ~(_olderStorePending_diff_T_38[5]), _olderStorePending_T_1485 & (|_olderStorePending_diff_T_37) & ~(_olderStorePending_diff_T_37[5]), _olderStorePending_T_1479 & (|_olderStorePending_diff_T_36) & ~(_olderStorePending_diff_T_36[5]), _olderStorePending_T_1473 & (|_olderStorePending_diff_T_35) & ~(_olderStorePending_diff_T_35[5]), _olderStorePending_T_1461 & (|_olderStorePending_diff_T_33) & ~(_olderStorePending_diff_T_33[5]), _olderStorePending_T_1455 & (|_olderStorePending_diff_T_32) & ~(_olderStorePending_diff_T_32[5])})) & (~(slots_2_decoded_isSystem | slots_2_decoded_isFenceI | slots_2_decoded_isSfenceVma | slots_2_decoded_isWfi) | io_robHeadValid & slots_2_robIdx == io_robHeadIdx); wire _src1Wake_T_12 = io_wakeup_0_phys == slots_3_prs1; wire _src1Wake_T_14 = io_wakeup_1_phys == slots_3_prs1; wire _src2Wake_T_12 = io_wakeup_0_phys == slots_3_prs2; wire _src2Wake_T_14 = io_wakeup_1_phys == slots_3_prs2; wire [5:0] _olderStorePending_diff_T_48 = slots_3_robIdx - slots_0_robIdx; wire [5:0] _olderStorePending_diff_T_49 = slots_3_robIdx - slots_1_robIdx; wire [5:0] _olderStorePending_diff_T_50 = slots_3_robIdx - slots_2_robIdx; wire [5:0] _olderStorePending_diff_T_52 = slots_3_robIdx - slots_4_robIdx; wire [5:0] _olderStorePending_diff_T_53 = slots_3_robIdx - slots_5_robIdx; wire [5:0] _olderStorePending_diff_T_54 = slots_3_robIdx - slots_6_robIdx; wire [5:0] _olderStorePending_diff_T_55 = slots_3_robIdx - slots_7_robIdx; wire [5:0] _olderStorePending_diff_T_56 = slots_3_robIdx - slots_8_robIdx; wire [5:0] _olderStorePending_diff_T_57 = slots_3_robIdx - slots_9_robIdx; wire [5:0] _olderStorePending_diff_T_58 = slots_3_robIdx - slots_10_robIdx; wire [5:0] _olderStorePending_diff_T_59 = slots_3_robIdx - slots_11_robIdx; wire [5:0] _olderStorePending_diff_T_60 = slots_3_robIdx - slots_12_robIdx; wire [5:0] _olderStorePending_diff_T_61 = slots_3_robIdx - slots_13_robIdx; wire [5:0] _olderStorePending_diff_T_62 = slots_3_robIdx - slots_14_robIdx; wire [5:0] _olderStorePending_diff_T_63 = slots_3_robIdx - slots_15_robIdx; wire readyVec_3 = valid_3 & (slots_3_src1Ready | io_wakeup_0_valid & _src1Wake_T_12 | io_wakeup_1_valid & _src1Wake_T_14 | slots_3_decoded_rs1 == 5'h0) & (slots_3_src2Ready | io_wakeup_0_valid & _src2Wake_T_12 | io_wakeup_1_valid & _src2Wake_T_14 | slots_3_decoded_rs2 == 5'h0) & ~((slots_3_decoded_isLoad | slots_3_decoded_isAmo) & (|{_olderStorePending_T_1545 & (|_olderStorePending_diff_T_63) & ~(_olderStorePending_diff_T_63[5]), _olderStorePending_T_1539 & (|_olderStorePending_diff_T_62) & ~(_olderStorePending_diff_T_62[5]), _olderStorePending_T_1533 & (|_olderStorePending_diff_T_61) & ~(_olderStorePending_diff_T_61[5]), _olderStorePending_T_1527 & (|_olderStorePending_diff_T_60) & ~(_olderStorePending_diff_T_60[5]), _olderStorePending_T_1521 & (|_olderStorePending_diff_T_59) & ~(_olderStorePending_diff_T_59[5]), _olderStorePending_T_1515 & (|_olderStorePending_diff_T_58) & ~(_olderStorePending_diff_T_58[5]), _olderStorePending_T_1509 & (|_olderStorePending_diff_T_57) & ~(_olderStorePending_diff_T_57[5]), _olderStorePending_T_1503 & (|_olderStorePending_diff_T_56) & ~(_olderStorePending_diff_T_56[5]), _olderStorePending_T_1497 & (|_olderStorePending_diff_T_55) & ~(_olderStorePending_diff_T_55[5]), _olderStorePending_T_1491 & (|_olderStorePending_diff_T_54) & ~(_olderStorePending_diff_T_54[5]), _olderStorePending_T_1485 & (|_olderStorePending_diff_T_53) & ~(_olderStorePending_diff_T_53[5]), _olderStorePending_T_1479 & (|_olderStorePending_diff_T_52) & ~(_olderStorePending_diff_T_52[5]), _olderStorePending_T_1467 & (|_olderStorePending_diff_T_50) & ~(_olderStorePending_diff_T_50[5]), _olderStorePending_T_1461 & (|_olderStorePending_diff_T_49) & ~(_olderStorePending_diff_T_49[5]), _olderStorePending_T_1455 & (|_olderStorePending_diff_T_48) & ~(_olderStorePending_diff_T_48[5])})) & (~(slots_3_decoded_isSystem | slots_3_decoded_isFenceI | slots_3_decoded_isSfenceVma | slots_3_decoded_isWfi) | io_robHeadValid & slots_3_robIdx == io_robHeadIdx); wire _src1Wake_T_16 = io_wakeup_0_phys == slots_4_prs1; wire _src1Wake_T_18 = io_wakeup_1_phys == slots_4_prs1; wire _src2Wake_T_16 = io_wakeup_0_phys == slots_4_prs2; wire _src2Wake_T_18 = io_wakeup_1_phys == slots_4_prs2; wire [5:0] _olderStorePending_diff_T_64 = slots_4_robIdx - slots_0_robIdx; wire [5:0] _olderStorePending_diff_T_65 = slots_4_robIdx - slots_1_robIdx; wire [5:0] _olderStorePending_diff_T_66 = slots_4_robIdx - slots_2_robIdx; wire [5:0] _olderStorePending_diff_T_67 = slots_4_robIdx - slots_3_robIdx; wire [5:0] _olderStorePending_diff_T_69 = slots_4_robIdx - slots_5_robIdx; wire [5:0] _olderStorePending_diff_T_70 = slots_4_robIdx - slots_6_robIdx; wire [5:0] _olderStorePending_diff_T_71 = slots_4_robIdx - slots_7_robIdx; wire [5:0] _olderStorePending_diff_T_72 = slots_4_robIdx - slots_8_robIdx; wire [5:0] _olderStorePending_diff_T_73 = slots_4_robIdx - slots_9_robIdx; wire [5:0] _olderStorePending_diff_T_74 = slots_4_robIdx - slots_10_robIdx; wire [5:0] _olderStorePending_diff_T_75 = slots_4_robIdx - slots_11_robIdx; wire [5:0] _olderStorePending_diff_T_76 = slots_4_robIdx - slots_12_robIdx; wire [5:0] _olderStorePending_diff_T_77 = slots_4_robIdx - slots_13_robIdx; wire [5:0] _olderStorePending_diff_T_78 = slots_4_robIdx - slots_14_robIdx; wire [5:0] _olderStorePending_diff_T_79 = slots_4_robIdx - slots_15_robIdx; wire readyVec_4 = valid_4 & (slots_4_src1Ready | io_wakeup_0_valid & _src1Wake_T_16 | io_wakeup_1_valid & _src1Wake_T_18 | slots_4_decoded_rs1 == 5'h0) & (slots_4_src2Ready | io_wakeup_0_valid & _src2Wake_T_16 | io_wakeup_1_valid & _src2Wake_T_18 | slots_4_decoded_rs2 == 5'h0) & ~((slots_4_decoded_isLoad | slots_4_decoded_isAmo) & (|{_olderStorePending_T_1545 & (|_olderStorePending_diff_T_79) & ~(_olderStorePending_diff_T_79[5]), _olderStorePending_T_1539 & (|_olderStorePending_diff_T_78) & ~(_olderStorePending_diff_T_78[5]), _olderStorePending_T_1533 & (|_olderStorePending_diff_T_77) & ~(_olderStorePending_diff_T_77[5]), _olderStorePending_T_1527 & (|_olderStorePending_diff_T_76) & ~(_olderStorePending_diff_T_76[5]), _olderStorePending_T_1521 & (|_olderStorePending_diff_T_75) & ~(_olderStorePending_diff_T_75[5]), _olderStorePending_T_1515 & (|_olderStorePending_diff_T_74) & ~(_olderStorePending_diff_T_74[5]), _olderStorePending_T_1509 & (|_olderStorePending_diff_T_73) & ~(_olderStorePending_diff_T_73[5]), _olderStorePending_T_1503 & (|_olderStorePending_diff_T_72) & ~(_olderStorePending_diff_T_72[5]), _olderStorePending_T_1497 & (|_olderStorePending_diff_T_71) & ~(_olderStorePending_diff_T_71[5]), _olderStorePending_T_1491 & (|_olderStorePending_diff_T_70) & ~(_olderStorePending_diff_T_70[5]), _olderStorePending_T_1485 & (|_olderStorePending_diff_T_69) & ~(_olderStorePending_diff_T_69[5]), _olderStorePending_T_1473 & (|_olderStorePending_diff_T_67) & ~(_olderStorePending_diff_T_67[5]), _olderStorePending_T_1467 & (|_olderStorePending_diff_T_66) & ~(_olderStorePending_diff_T_66[5]), _olderStorePending_T_1461 & (|_olderStorePending_diff_T_65) & ~(_olderStorePending_diff_T_65[5]), _olderStorePending_T_1455 & (|_olderStorePending_diff_T_64) & ~(_olderStorePending_diff_T_64[5])})) & (~(slots_4_decoded_isSystem | slots_4_decoded_isFenceI | slots_4_decoded_isSfenceVma | slots_4_decoded_isWfi) | io_robHeadValid & slots_4_robIdx == io_robHeadIdx); wire _src1Wake_T_20 = io_wakeup_0_phys == slots_5_prs1; wire _src1Wake_T_22 = io_wakeup_1_phys == slots_5_prs1; wire _src2Wake_T_20 = io_wakeup_0_phys == slots_5_prs2; wire _src2Wake_T_22 = io_wakeup_1_phys == slots_5_prs2; wire [5:0] _olderStorePending_diff_T_80 = slots_5_robIdx - slots_0_robIdx; wire [5:0] _olderStorePending_diff_T_81 = slots_5_robIdx - slots_1_robIdx; wire [5:0] _olderStorePending_diff_T_82 = slots_5_robIdx - slots_2_robIdx; wire [5:0] _olderStorePending_diff_T_83 = slots_5_robIdx - slots_3_robIdx; wire [5:0] _olderStorePending_diff_T_84 = slots_5_robIdx - slots_4_robIdx; wire [5:0] _olderStorePending_diff_T_86 = slots_5_robIdx - slots_6_robIdx; wire [5:0] _olderStorePending_diff_T_87 = slots_5_robIdx - slots_7_robIdx; wire [5:0] _olderStorePending_diff_T_88 = slots_5_robIdx - slots_8_robIdx; wire [5:0] _olderStorePending_diff_T_89 = slots_5_robIdx - slots_9_robIdx; wire [5:0] _olderStorePending_diff_T_90 = slots_5_robIdx - slots_10_robIdx; wire [5:0] _olderStorePending_diff_T_91 = slots_5_robIdx - slots_11_robIdx; wire [5:0] _olderStorePending_diff_T_92 = slots_5_robIdx - slots_12_robIdx; wire [5:0] _olderStorePending_diff_T_93 = slots_5_robIdx - slots_13_robIdx; wire [5:0] _olderStorePending_diff_T_94 = slots_5_robIdx - slots_14_robIdx; wire [5:0] _olderStorePending_diff_T_95 = slots_5_robIdx - slots_15_robIdx; wire readyVec_5 = valid_5 & (slots_5_src1Ready | io_wakeup_0_valid & _src1Wake_T_20 | io_wakeup_1_valid & _src1Wake_T_22 | slots_5_decoded_rs1 == 5'h0) & (slots_5_src2Ready | io_wakeup_0_valid & _src2Wake_T_20 | io_wakeup_1_valid & _src2Wake_T_22 | slots_5_decoded_rs2 == 5'h0) & ~((slots_5_decoded_isLoad | slots_5_decoded_isAmo) & (|{_olderStorePending_T_1545 & (|_olderStorePending_diff_T_95) & ~(_olderStorePending_diff_T_95[5]), _olderStorePending_T_1539 & (|_olderStorePending_diff_T_94) & ~(_olderStorePending_diff_T_94[5]), _olderStorePending_T_1533 & (|_olderStorePending_diff_T_93) & ~(_olderStorePending_diff_T_93[5]), _olderStorePending_T_1527 & (|_olderStorePending_diff_T_92) & ~(_olderStorePending_diff_T_92[5]), _olderStorePending_T_1521 & (|_olderStorePending_diff_T_91) & ~(_olderStorePending_diff_T_91[5]), _olderStorePending_T_1515 & (|_olderStorePending_diff_T_90) & ~(_olderStorePending_diff_T_90[5]), _olderStorePending_T_1509 & (|_olderStorePending_diff_T_89) & ~(_olderStorePending_diff_T_89[5]), _olderStorePending_T_1503 & (|_olderStorePending_diff_T_88) & ~(_olderStorePending_diff_T_88[5]), _olderStorePending_T_1497 & (|_olderStorePending_diff_T_87) & ~(_olderStorePending_diff_T_87[5]), _olderStorePending_T_1491 & (|_olderStorePending_diff_T_86) & ~(_olderStorePending_diff_T_86[5]), _olderStorePending_T_1479 & (|_olderStorePending_diff_T_84) & ~(_olderStorePending_diff_T_84[5]), _olderStorePending_T_1473 & (|_olderStorePending_diff_T_83) & ~(_olderStorePending_diff_T_83[5]), _olderStorePending_T_1467 & (|_olderStorePending_diff_T_82) & ~(_olderStorePending_diff_T_82[5]), _olderStorePending_T_1461 & (|_olderStorePending_diff_T_81) & ~(_olderStorePending_diff_T_81[5]), _olderStorePending_T_1455 & (|_olderStorePending_diff_T_80) & ~(_olderStorePending_diff_T_80[5])})) & (~(slots_5_decoded_isSystem | slots_5_decoded_isFenceI | slots_5_decoded_isSfenceVma | slots_5_decoded_isWfi) | io_robHeadValid & slots_5_robIdx == io_robHeadIdx); wire _src1Wake_T_24 = io_wakeup_0_phys == slots_6_prs1; wire _src1Wake_T_26 = io_wakeup_1_phys == slots_6_prs1; wire _src2Wake_T_24 = io_wakeup_0_phys == slots_6_prs2; wire _src2Wake_T_26 = io_wakeup_1_phys == slots_6_prs2; wire [5:0] _olderStorePending_diff_T_96 = slots_6_robIdx - slots_0_robIdx; wire [5:0] _olderStorePending_diff_T_97 = slots_6_robIdx - slots_1_robIdx; wire [5:0] _olderStorePending_diff_T_98 = slots_6_robIdx - slots_2_robIdx; wire [5:0] _olderStorePending_diff_T_99 = slots_6_robIdx - slots_3_robIdx; wire [5:0] _olderStorePending_diff_T_100 = slots_6_robIdx - slots_4_robIdx; wire [5:0] _olderStorePending_diff_T_101 = slots_6_robIdx - slots_5_robIdx; wire [5:0] _olderStorePending_diff_T_103 = slots_6_robIdx - slots_7_robIdx; wire [5:0] _olderStorePending_diff_T_104 = slots_6_robIdx - slots_8_robIdx; wire [5:0] _olderStorePending_diff_T_105 = slots_6_robIdx - slots_9_robIdx; wire [5:0] _olderStorePending_diff_T_106 = slots_6_robIdx - slots_10_robIdx; wire [5:0] _olderStorePending_diff_T_107 = slots_6_robIdx - slots_11_robIdx; wire [5:0] _olderStorePending_diff_T_108 = slots_6_robIdx - slots_12_robIdx; wire [5:0] _olderStorePending_diff_T_109 = slots_6_robIdx - slots_13_robIdx; wire [5:0] _olderStorePending_diff_T_110 = slots_6_robIdx - slots_14_robIdx; wire [5:0] _olderStorePending_diff_T_111 = slots_6_robIdx - slots_15_robIdx; wire readyVec_6 = valid_6 & (slots_6_src1Ready | io_wakeup_0_valid & _src1Wake_T_24 | io_wakeup_1_valid & _src1Wake_T_26 | slots_6_decoded_rs1 == 5'h0) & (slots_6_src2Ready | io_wakeup_0_valid & _src2Wake_T_24 | io_wakeup_1_valid & _src2Wake_T_26 | slots_6_decoded_rs2 == 5'h0) & ~((slots_6_decoded_isLoad | slots_6_decoded_isAmo) & (|{_olderStorePending_T_1545 & (|_olderStorePending_diff_T_111) & ~(_olderStorePending_diff_T_111[5]), _olderStorePending_T_1539 & (|_olderStorePending_diff_T_110) & ~(_olderStorePending_diff_T_110[5]), _olderStorePending_T_1533 & (|_olderStorePending_diff_T_109) & ~(_olderStorePending_diff_T_109[5]), _olderStorePending_T_1527 & (|_olderStorePending_diff_T_108) & ~(_olderStorePending_diff_T_108[5]), _olderStorePending_T_1521 & (|_olderStorePending_diff_T_107) & ~(_olderStorePending_diff_T_107[5]), _olderStorePending_T_1515 & (|_olderStorePending_diff_T_106) & ~(_olderStorePending_diff_T_106[5]), _olderStorePending_T_1509 & (|_olderStorePending_diff_T_105) & ~(_olderStorePending_diff_T_105[5]), _olderStorePending_T_1503 & (|_olderStorePending_diff_T_104) & ~(_olderStorePending_diff_T_104[5]), _olderStorePending_T_1497 & (|_olderStorePending_diff_T_103) & ~(_olderStorePending_diff_T_103[5]), _olderStorePending_T_1485 & (|_olderStorePending_diff_T_101) & ~(_olderStorePending_diff_T_101[5]), _olderStorePending_T_1479 & (|_olderStorePending_diff_T_100) & ~(_olderStorePending_diff_T_100[5]), _olderStorePending_T_1473 & (|_olderStorePending_diff_T_99) & ~(_olderStorePending_diff_T_99[5]), _olderStorePending_T_1467 & (|_olderStorePending_diff_T_98) & ~(_olderStorePending_diff_T_98[5]), _olderStorePending_T_1461 & (|_olderStorePending_diff_T_97) & ~(_olderStorePending_diff_T_97[5]), _olderStorePending_T_1455 & (|_olderStorePending_diff_T_96) & ~(_olderStorePending_diff_T_96[5])})) & (~(slots_6_decoded_isSystem | slots_6_decoded_isFenceI | slots_6_decoded_isSfenceVma | slots_6_decoded_isWfi) | io_robHeadValid & slots_6_robIdx == io_robHeadIdx); wire _src1Wake_T_28 = io_wakeup_0_phys == slots_7_prs1; wire _src1Wake_T_30 = io_wakeup_1_phys == slots_7_prs1; wire _src2Wake_T_28 = io_wakeup_0_phys == slots_7_prs2; wire _src2Wake_T_30 = io_wakeup_1_phys == slots_7_prs2; wire [5:0] _olderStorePending_diff_T_112 = slots_7_robIdx - slots_0_robIdx; wire [5:0] _olderStorePending_diff_T_113 = slots_7_robIdx - slots_1_robIdx; wire [5:0] _olderStorePending_diff_T_114 = slots_7_robIdx - slots_2_robIdx; wire [5:0] _olderStorePending_diff_T_115 = slots_7_robIdx - slots_3_robIdx; wire [5:0] _olderStorePending_diff_T_116 = slots_7_robIdx - slots_4_robIdx; wire [5:0] _olderStorePending_diff_T_117 = slots_7_robIdx - slots_5_robIdx; wire [5:0] _olderStorePending_diff_T_118 = slots_7_robIdx - slots_6_robIdx; wire [5:0] _olderStorePending_diff_T_120 = slots_7_robIdx - slots_8_robIdx; wire [5:0] _olderStorePending_diff_T_121 = slots_7_robIdx - slots_9_robIdx; wire [5:0] _olderStorePending_diff_T_122 = slots_7_robIdx - slots_10_robIdx; wire [5:0] _olderStorePending_diff_T_123 = slots_7_robIdx - slots_11_robIdx; wire [5:0] _olderStorePending_diff_T_124 = slots_7_robIdx - slots_12_robIdx; wire [5:0] _olderStorePending_diff_T_125 = slots_7_robIdx - slots_13_robIdx; wire [5:0] _olderStorePending_diff_T_126 = slots_7_robIdx - slots_14_robIdx; wire [5:0] _olderStorePending_diff_T_127 = slots_7_robIdx - slots_15_robIdx; wire readyVec_7 = valid_7 & (slots_7_src1Ready | io_wakeup_0_valid & _src1Wake_T_28 | io_wakeup_1_valid & _src1Wake_T_30 | slots_7_decoded_rs1 == 5'h0) & (slots_7_src2Ready | io_wakeup_0_valid & _src2Wake_T_28 | io_wakeup_1_valid & _src2Wake_T_30 | slots_7_decoded_rs2 == 5'h0) & ~((slots_7_decoded_isLoad | slots_7_decoded_isAmo) & (|{_olderStorePending_T_1545 & (|_olderStorePending_diff_T_127) & ~(_olderStorePending_diff_T_127[5]), _olderStorePending_T_1539 & (|_olderStorePending_diff_T_126) & ~(_olderStorePending_diff_T_126[5]), _olderStorePending_T_1533 & (|_olderStorePending_diff_T_125) & ~(_olderStorePending_diff_T_125[5]), _olderStorePending_T_1527 & (|_olderStorePending_diff_T_124) & ~(_olderStorePending_diff_T_124[5]), _olderStorePending_T_1521 & (|_olderStorePending_diff_T_123) & ~(_olderStorePending_diff_T_123[5]), _olderStorePending_T_1515 & (|_olderStorePending_diff_T_122) & ~(_olderStorePending_diff_T_122[5]), _olderStorePending_T_1509 & (|_olderStorePending_diff_T_121) & ~(_olderStorePending_diff_T_121[5]), _olderStorePending_T_1503 & (|_olderStorePending_diff_T_120) & ~(_olderStorePending_diff_T_120[5]), _olderStorePending_T_1491 & (|_olderStorePending_diff_T_118) & ~(_olderStorePending_diff_T_118[5]), _olderStorePending_T_1485 & (|_olderStorePending_diff_T_117) & ~(_olderStorePending_diff_T_117[5]), _olderStorePending_T_1479 & (|_olderStorePending_diff_T_116) & ~(_olderStorePending_diff_T_116[5]), _olderStorePending_T_1473 & (|_olderStorePending_diff_T_115) & ~(_olderStorePending_diff_T_115[5]), _olderStorePending_T_1467 & (|_olderStorePending_diff_T_114) & ~(_olderStorePending_diff_T_114[5]), _olderStorePending_T_1461 & (|_olderStorePending_diff_T_113) & ~(_olderStorePending_diff_T_113[5]), _olderStorePending_T_1455 & (|_olderStorePending_diff_T_112) & ~(_olderStorePending_diff_T_112[5])})) & (~(slots_7_decoded_isSystem | slots_7_decoded_isFenceI | slots_7_decoded_isSfenceVma | slots_7_decoded_isWfi) | io_robHeadValid & slots_7_robIdx == io_robHeadIdx); wire _src1Wake_T_32 = io_wakeup_0_phys == slots_8_prs1; wire _src1Wake_T_34 = io_wakeup_1_phys == slots_8_prs1; wire _src2Wake_T_32 = io_wakeup_0_phys == slots_8_prs2; wire _src2Wake_T_34 = io_wakeup_1_phys == slots_8_prs2; wire [5:0] _olderStorePending_diff_T_128 = slots_8_robIdx - slots_0_robIdx; wire [5:0] _olderStorePending_diff_T_129 = slots_8_robIdx - slots_1_robIdx; wire [5:0] _olderStorePending_diff_T_130 = slots_8_robIdx - slots_2_robIdx; wire [5:0] _olderStorePending_diff_T_131 = slots_8_robIdx - slots_3_robIdx; wire [5:0] _olderStorePending_diff_T_132 = slots_8_robIdx - slots_4_robIdx; wire [5:0] _olderStorePending_diff_T_133 = slots_8_robIdx - slots_5_robIdx; wire [5:0] _olderStorePending_diff_T_134 = slots_8_robIdx - slots_6_robIdx; wire [5:0] _olderStorePending_diff_T_135 = slots_8_robIdx - slots_7_robIdx; wire [5:0] _olderStorePending_diff_T_137 = slots_8_robIdx - slots_9_robIdx; wire [5:0] _olderStorePending_diff_T_138 = slots_8_robIdx - slots_10_robIdx; wire [5:0] _olderStorePending_diff_T_139 = slots_8_robIdx - slots_11_robIdx; wire [5:0] _olderStorePending_diff_T_140 = slots_8_robIdx - slots_12_robIdx; wire [5:0] _olderStorePending_diff_T_141 = slots_8_robIdx - slots_13_robIdx; wire [5:0] _olderStorePending_diff_T_142 = slots_8_robIdx - slots_14_robIdx; wire [5:0] _olderStorePending_diff_T_143 = slots_8_robIdx - slots_15_robIdx; wire readyVec_8 = valid_8 & (slots_8_src1Ready | io_wakeup_0_valid & _src1Wake_T_32 | io_wakeup_1_valid & _src1Wake_T_34 | slots_8_decoded_rs1 == 5'h0) & (slots_8_src2Ready | io_wakeup_0_valid & _src2Wake_T_32 | io_wakeup_1_valid & _src2Wake_T_34 | slots_8_decoded_rs2 == 5'h0) & ~((slots_8_decoded_isLoad | slots_8_decoded_isAmo) & (|{_olderStorePending_T_1545 & (|_olderStorePending_diff_T_143) & ~(_olderStorePending_diff_T_143[5]), _olderStorePending_T_1539 & (|_olderStorePending_diff_T_142) & ~(_olderStorePending_diff_T_142[5]), _olderStorePending_T_1533 & (|_olderStorePending_diff_T_141) & ~(_olderStorePending_diff_T_141[5]), _olderStorePending_T_1527 & (|_olderStorePending_diff_T_140) & ~(_olderStorePending_diff_T_140[5]), _olderStorePending_T_1521 & (|_olderStorePending_diff_T_139) & ~(_olderStorePending_diff_T_139[5]), _olderStorePending_T_1515 & (|_olderStorePending_diff_T_138) & ~(_olderStorePending_diff_T_138[5]), _olderStorePending_T_1509 & (|_olderStorePending_diff_T_137) & ~(_olderStorePending_diff_T_137[5]), _olderStorePending_T_1497 & (|_olderStorePending_diff_T_135) & ~(_olderStorePending_diff_T_135[5]), _olderStorePending_T_1491 & (|_olderStorePending_diff_T_134) & ~(_olderStorePending_diff_T_134[5]), _olderStorePending_T_1485 & (|_olderStorePending_diff_T_133) & ~(_olderStorePending_diff_T_133[5]), _olderStorePending_T_1479 & (|_olderStorePending_diff_T_132) & ~(_olderStorePending_diff_T_132[5]), _olderStorePending_T_1473 & (|_olderStorePending_diff_T_131) & ~(_olderStorePending_diff_T_131[5]), _olderStorePending_T_1467 & (|_olderStorePending_diff_T_130) & ~(_olderStorePending_diff_T_130[5]), _olderStorePending_T_1461 & (|_olderStorePending_diff_T_129) & ~(_olderStorePending_diff_T_129[5]), _olderStorePending_T_1455 & (|_olderStorePending_diff_T_128) & ~(_olderStorePending_diff_T_128[5])})) & (~(slots_8_decoded_isSystem | slots_8_decoded_isFenceI | slots_8_decoded_isSfenceVma | slots_8_decoded_isWfi) | io_robHeadValid & slots_8_robIdx == io_robHeadIdx); wire _src1Wake_T_36 = io_wakeup_0_phys == slots_9_prs1; wire _src1Wake_T_38 = io_wakeup_1_phys == slots_9_prs1; wire _src2Wake_T_36 = io_wakeup_0_phys == slots_9_prs2; wire _src2Wake_T_38 = io_wakeup_1_phys == slots_9_prs2; wire [5:0] _olderStorePending_diff_T_144 = slots_9_robIdx - slots_0_robIdx; wire [5:0] _olderStorePending_diff_T_145 = slots_9_robIdx - slots_1_robIdx; wire [5:0] _olderStorePending_diff_T_146 = slots_9_robIdx - slots_2_robIdx; wire [5:0] _olderStorePending_diff_T_147 = slots_9_robIdx - slots_3_robIdx; wire [5:0] _olderStorePending_diff_T_148 = slots_9_robIdx - slots_4_robIdx; wire [5:0] _olderStorePending_diff_T_149 = slots_9_robIdx - slots_5_robIdx; wire [5:0] _olderStorePending_diff_T_150 = slots_9_robIdx - slots_6_robIdx; wire [5:0] _olderStorePending_diff_T_151 = slots_9_robIdx - slots_7_robIdx; wire [5:0] _olderStorePending_diff_T_152 = slots_9_robIdx - slots_8_robIdx; wire [5:0] _olderStorePending_diff_T_154 = slots_9_robIdx - slots_10_robIdx; wire [5:0] _olderStorePending_diff_T_155 = slots_9_robIdx - slots_11_robIdx; wire [5:0] _olderStorePending_diff_T_156 = slots_9_robIdx - slots_12_robIdx; wire [5:0] _olderStorePending_diff_T_157 = slots_9_robIdx - slots_13_robIdx; wire [5:0] _olderStorePending_diff_T_158 = slots_9_robIdx - slots_14_robIdx; wire [5:0] _olderStorePending_diff_T_159 = slots_9_robIdx - slots_15_robIdx; wire readyVec_9 = valid_9 & (slots_9_src1Ready | io_wakeup_0_valid & _src1Wake_T_36 | io_wakeup_1_valid & _src1Wake_T_38 | slots_9_decoded_rs1 == 5'h0) & (slots_9_src2Ready | io_wakeup_0_valid & _src2Wake_T_36 | io_wakeup_1_valid & _src2Wake_T_38 | slots_9_decoded_rs2 == 5'h0) & ~((slots_9_decoded_isLoad | slots_9_decoded_isAmo) & (|{_olderStorePending_T_1545 & (|_olderStorePending_diff_T_159) & ~(_olderStorePending_diff_T_159[5]), _olderStorePending_T_1539 & (|_olderStorePending_diff_T_158) & ~(_olderStorePending_diff_T_158[5]), _olderStorePending_T_1533 & (|_olderStorePending_diff_T_157) & ~(_olderStorePending_diff_T_157[5]), _olderStorePending_T_1527 & (|_olderStorePending_diff_T_156) & ~(_olderStorePending_diff_T_156[5]), _olderStorePending_T_1521 & (|_olderStorePending_diff_T_155) & ~(_olderStorePending_diff_T_155[5]), _olderStorePending_T_1515 & (|_olderStorePending_diff_T_154) & ~(_olderStorePending_diff_T_154[5]), _olderStorePending_T_1503 & (|_olderStorePending_diff_T_152) & ~(_olderStorePending_diff_T_152[5]), _olderStorePending_T_1497 & (|_olderStorePending_diff_T_151) & ~(_olderStorePending_diff_T_151[5]), _olderStorePending_T_1491 & (|_olderStorePending_diff_T_150) & ~(_olderStorePending_diff_T_150[5]), _olderStorePending_T_1485 & (|_olderStorePending_diff_T_149) & ~(_olderStorePending_diff_T_149[5]), _olderStorePending_T_1479 & (|_olderStorePending_diff_T_148) & ~(_olderStorePending_diff_T_148[5]), _olderStorePending_T_1473 & (|_olderStorePending_diff_T_147) & ~(_olderStorePending_diff_T_147[5]), _olderStorePending_T_1467 & (|_olderStorePending_diff_T_146) & ~(_olderStorePending_diff_T_146[5]), _olderStorePending_T_1461 & (|_olderStorePending_diff_T_145) & ~(_olderStorePending_diff_T_145[5]), _olderStorePending_T_1455 & (|_olderStorePending_diff_T_144) & ~(_olderStorePending_diff_T_144[5])})) & (~(slots_9_decoded_isSystem | slots_9_decoded_isFenceI | slots_9_decoded_isSfenceVma | slots_9_decoded_isWfi) | io_robHeadValid & slots_9_robIdx == io_robHeadIdx); wire _src1Wake_T_40 = io_wakeup_0_phys == slots_10_prs1; wire _src1Wake_T_42 = io_wakeup_1_phys == slots_10_prs1; wire _src2Wake_T_40 = io_wakeup_0_phys == slots_10_prs2; wire _src2Wake_T_42 = io_wakeup_1_phys == slots_10_prs2; wire [5:0] _olderStorePending_diff_T_160 = slots_10_robIdx - slots_0_robIdx; wire [5:0] _olderStorePending_diff_T_161 = slots_10_robIdx - slots_1_robIdx; wire [5:0] _olderStorePending_diff_T_162 = slots_10_robIdx - slots_2_robIdx; wire [5:0] _olderStorePending_diff_T_163 = slots_10_robIdx - slots_3_robIdx; wire [5:0] _olderStorePending_diff_T_164 = slots_10_robIdx - slots_4_robIdx; wire [5:0] _olderStorePending_diff_T_165 = slots_10_robIdx - slots_5_robIdx; wire [5:0] _olderStorePending_diff_T_166 = slots_10_robIdx - slots_6_robIdx; wire [5:0] _olderStorePending_diff_T_167 = slots_10_robIdx - slots_7_robIdx; wire [5:0] _olderStorePending_diff_T_168 = slots_10_robIdx - slots_8_robIdx; wire [5:0] _olderStorePending_diff_T_169 = slots_10_robIdx - slots_9_robIdx; wire [5:0] _olderStorePending_diff_T_171 = slots_10_robIdx - slots_11_robIdx; wire [5:0] _olderStorePending_diff_T_172 = slots_10_robIdx - slots_12_robIdx; wire [5:0] _olderStorePending_diff_T_173 = slots_10_robIdx - slots_13_robIdx; wire [5:0] _olderStorePending_diff_T_174 = slots_10_robIdx - slots_14_robIdx; wire [5:0] _olderStorePending_diff_T_175 = slots_10_robIdx - slots_15_robIdx; wire readyVec_10 = valid_10 & (slots_10_src1Ready | io_wakeup_0_valid & _src1Wake_T_40 | io_wakeup_1_valid & _src1Wake_T_42 | slots_10_decoded_rs1 == 5'h0) & (slots_10_src2Ready | io_wakeup_0_valid & _src2Wake_T_40 | io_wakeup_1_valid & _src2Wake_T_42 | slots_10_decoded_rs2 == 5'h0) & ~((slots_10_decoded_isLoad | slots_10_decoded_isAmo) & (|{_olderStorePending_T_1545 & (|_olderStorePending_diff_T_175) & ~(_olderStorePending_diff_T_175[5]), _olderStorePending_T_1539 & (|_olderStorePending_diff_T_174) & ~(_olderStorePending_diff_T_174[5]), _olderStorePending_T_1533 & (|_olderStorePending_diff_T_173) & ~(_olderStorePending_diff_T_173[5]), _olderStorePending_T_1527 & (|_olderStorePending_diff_T_172) & ~(_olderStorePending_diff_T_172[5]), _olderStorePending_T_1521 & (|_olderStorePending_diff_T_171) & ~(_olderStorePending_diff_T_171[5]), _olderStorePending_T_1509 & (|_olderStorePending_diff_T_169) & ~(_olderStorePending_diff_T_169[5]), _olderStorePending_T_1503 & (|_olderStorePending_diff_T_168) & ~(_olderStorePending_diff_T_168[5]), _olderStorePending_T_1497 & (|_olderStorePending_diff_T_167) & ~(_olderStorePending_diff_T_167[5]), _olderStorePending_T_1491 & (|_olderStorePending_diff_T_166) & ~(_olderStorePending_diff_T_166[5]), _olderStorePending_T_1485 & (|_olderStorePending_diff_T_165) & ~(_olderStorePending_diff_T_165[5]), _olderStorePending_T_1479 & (|_olderStorePending_diff_T_164) & ~(_olderStorePending_diff_T_164[5]), _olderStorePending_T_1473 & (|_olderStorePending_diff_T_163) & ~(_olderStorePending_diff_T_163[5]), _olderStorePending_T_1467 & (|_olderStorePending_diff_T_162) & ~(_olderStorePending_diff_T_162[5]), _olderStorePending_T_1461 & (|_olderStorePending_diff_T_161) & ~(_olderStorePending_diff_T_161[5]), _olderStorePending_T_1455 & (|_olderStorePending_diff_T_160) & ~(_olderStorePending_diff_T_160[5])})) & (~(slots_10_decoded_isSystem | slots_10_decoded_isFenceI | slots_10_decoded_isSfenceVma | slots_10_decoded_isWfi) | io_robHeadValid & slots_10_robIdx == io_robHeadIdx); wire _src1Wake_T_44 = io_wakeup_0_phys == slots_11_prs1; wire _src1Wake_T_46 = io_wakeup_1_phys == slots_11_prs1; wire _src2Wake_T_44 = io_wakeup_0_phys == slots_11_prs2; wire _src2Wake_T_46 = io_wakeup_1_phys == slots_11_prs2; wire [5:0] _olderStorePending_diff_T_176 = slots_11_robIdx - slots_0_robIdx; wire [5:0] _olderStorePending_diff_T_177 = slots_11_robIdx - slots_1_robIdx; wire [5:0] _olderStorePending_diff_T_178 = slots_11_robIdx - slots_2_robIdx; wire [5:0] _olderStorePending_diff_T_179 = slots_11_robIdx - slots_3_robIdx; wire [5:0] _olderStorePending_diff_T_180 = slots_11_robIdx - slots_4_robIdx; wire [5:0] _olderStorePending_diff_T_181 = slots_11_robIdx - slots_5_robIdx; wire [5:0] _olderStorePending_diff_T_182 = slots_11_robIdx - slots_6_robIdx; wire [5:0] _olderStorePending_diff_T_183 = slots_11_robIdx - slots_7_robIdx; wire [5:0] _olderStorePending_diff_T_184 = slots_11_robIdx - slots_8_robIdx; wire [5:0] _olderStorePending_diff_T_185 = slots_11_robIdx - slots_9_robIdx; wire [5:0] _olderStorePending_diff_T_186 = slots_11_robIdx - slots_10_robIdx; wire [5:0] _olderStorePending_diff_T_188 = slots_11_robIdx - slots_12_robIdx; wire [5:0] _olderStorePending_diff_T_189 = slots_11_robIdx - slots_13_robIdx; wire [5:0] _olderStorePending_diff_T_190 = slots_11_robIdx - slots_14_robIdx; wire [5:0] _olderStorePending_diff_T_191 = slots_11_robIdx - slots_15_robIdx; wire readyVec_11 = valid_11 & (slots_11_src1Ready | io_wakeup_0_valid & _src1Wake_T_44 | io_wakeup_1_valid & _src1Wake_T_46 | slots_11_decoded_rs1 == 5'h0) & (slots_11_src2Ready | io_wakeup_0_valid & _src2Wake_T_44 | io_wakeup_1_valid & _src2Wake_T_46 | slots_11_decoded_rs2 == 5'h0) & ~((slots_11_decoded_isLoad | slots_11_decoded_isAmo) & (|{_olderStorePending_T_1545 & (|_olderStorePending_diff_T_191) & ~(_olderStorePending_diff_T_191[5]), _olderStorePending_T_1539 & (|_olderStorePending_diff_T_190) & ~(_olderStorePending_diff_T_190[5]), _olderStorePending_T_1533 & (|_olderStorePending_diff_T_189) & ~(_olderStorePending_diff_T_189[5]), _olderStorePending_T_1527 & (|_olderStorePending_diff_T_188) & ~(_olderStorePending_diff_T_188[5]), _olderStorePending_T_1515 & (|_olderStorePending_diff_T_186) & ~(_olderStorePending_diff_T_186[5]), _olderStorePending_T_1509 & (|_olderStorePending_diff_T_185) & ~(_olderStorePending_diff_T_185[5]), _olderStorePending_T_1503 & (|_olderStorePending_diff_T_184) & ~(_olderStorePending_diff_T_184[5]), _olderStorePending_T_1497 & (|_olderStorePending_diff_T_183) & ~(_olderStorePending_diff_T_183[5]), _olderStorePending_T_1491 & (|_olderStorePending_diff_T_182) & ~(_olderStorePending_diff_T_182[5]), _olderStorePending_T_1485 & (|_olderStorePending_diff_T_181) & ~(_olderStorePending_diff_T_181[5]), _olderStorePending_T_1479 & (|_olderStorePending_diff_T_180) & ~(_olderStorePending_diff_T_180[5]), _olderStorePending_T_1473 & (|_olderStorePending_diff_T_179) & ~(_olderStorePending_diff_T_179[5]), _olderStorePending_T_1467 & (|_olderStorePending_diff_T_178) & ~(_olderStorePending_diff_T_178[5]), _olderStorePending_T_1461 & (|_olderStorePending_diff_T_177) & ~(_olderStorePending_diff_T_177[5]), _olderStorePending_T_1455 & (|_olderStorePending_diff_T_176) & ~(_olderStorePending_diff_T_176[5])})) & (~(slots_11_decoded_isSystem | slots_11_decoded_isFenceI | slots_11_decoded_isSfenceVma | slots_11_decoded_isWfi) | io_robHeadValid & slots_11_robIdx == io_robHeadIdx); wire _src1Wake_T_48 = io_wakeup_0_phys == slots_12_prs1; wire _src1Wake_T_50 = io_wakeup_1_phys == slots_12_prs1; wire _src2Wake_T_48 = io_wakeup_0_phys == slots_12_prs2; wire _src2Wake_T_50 = io_wakeup_1_phys == slots_12_prs2; wire [5:0] _olderStorePending_diff_T_192 = slots_12_robIdx - slots_0_robIdx; wire [5:0] _olderStorePending_diff_T_193 = slots_12_robIdx - slots_1_robIdx; wire [5:0] _olderStorePending_diff_T_194 = slots_12_robIdx - slots_2_robIdx; wire [5:0] _olderStorePending_diff_T_195 = slots_12_robIdx - slots_3_robIdx; wire [5:0] _olderStorePending_diff_T_196 = slots_12_robIdx - slots_4_robIdx; wire [5:0] _olderStorePending_diff_T_197 = slots_12_robIdx - slots_5_robIdx; wire [5:0] _olderStorePending_diff_T_198 = slots_12_robIdx - slots_6_robIdx; wire [5:0] _olderStorePending_diff_T_199 = slots_12_robIdx - slots_7_robIdx; wire [5:0] _olderStorePending_diff_T_200 = slots_12_robIdx - slots_8_robIdx; wire [5:0] _olderStorePending_diff_T_201 = slots_12_robIdx - slots_9_robIdx; wire [5:0] _olderStorePending_diff_T_202 = slots_12_robIdx - slots_10_robIdx; wire [5:0] _olderStorePending_diff_T_203 = slots_12_robIdx - slots_11_robIdx; wire [5:0] _olderStorePending_diff_T_205 = slots_12_robIdx - slots_13_robIdx; wire [5:0] _olderStorePending_diff_T_206 = slots_12_robIdx - slots_14_robIdx; wire [5:0] _olderStorePending_diff_T_207 = slots_12_robIdx - slots_15_robIdx; wire readyVec_12 = valid_12 & (slots_12_src1Ready | io_wakeup_0_valid & _src1Wake_T_48 | io_wakeup_1_valid & _src1Wake_T_50 | slots_12_decoded_rs1 == 5'h0) & (slots_12_src2Ready | io_wakeup_0_valid & _src2Wake_T_48 | io_wakeup_1_valid & _src2Wake_T_50 | slots_12_decoded_rs2 == 5'h0) & ~((slots_12_decoded_isLoad | slots_12_decoded_isAmo) & (|{_olderStorePending_T_1545 & (|_olderStorePending_diff_T_207) & ~(_olderStorePending_diff_T_207[5]), _olderStorePending_T_1539 & (|_olderStorePending_diff_T_206) & ~(_olderStorePending_diff_T_206[5]), _olderStorePending_T_1533 & (|_olderStorePending_diff_T_205) & ~(_olderStorePending_diff_T_205[5]), _olderStorePending_T_1521 & (|_olderStorePending_diff_T_203) & ~(_olderStorePending_diff_T_203[5]), _olderStorePending_T_1515 & (|_olderStorePending_diff_T_202) & ~(_olderStorePending_diff_T_202[5]), _olderStorePending_T_1509 & (|_olderStorePending_diff_T_201) & ~(_olderStorePending_diff_T_201[5]), _olderStorePending_T_1503 & (|_olderStorePending_diff_T_200) & ~(_olderStorePending_diff_T_200[5]), _olderStorePending_T_1497 & (|_olderStorePending_diff_T_199) & ~(_olderStorePending_diff_T_199[5]), _olderStorePending_T_1491 & (|_olderStorePending_diff_T_198) & ~(_olderStorePending_diff_T_198[5]), _olderStorePending_T_1485 & (|_olderStorePending_diff_T_197) & ~(_olderStorePending_diff_T_197[5]), _olderStorePending_T_1479 & (|_olderStorePending_diff_T_196) & ~(_olderStorePending_diff_T_196[5]), _olderStorePending_T_1473 & (|_olderStorePending_diff_T_195) & ~(_olderStorePending_diff_T_195[5]), _olderStorePending_T_1467 & (|_olderStorePending_diff_T_194) & ~(_olderStorePending_diff_T_194[5]), _olderStorePending_T_1461 & (|_olderStorePending_diff_T_193) & ~(_olderStorePending_diff_T_193[5]), _olderStorePending_T_1455 & (|_olderStorePending_diff_T_192) & ~(_olderStorePending_diff_T_192[5])})) & (~(slots_12_decoded_isSystem | slots_12_decoded_isFenceI | slots_12_decoded_isSfenceVma | slots_12_decoded_isWfi) | io_robHeadValid & slots_12_robIdx == io_robHeadIdx); wire _src1Wake_T_52 = io_wakeup_0_phys == slots_13_prs1; wire _src1Wake_T_54 = io_wakeup_1_phys == slots_13_prs1; wire _src2Wake_T_52 = io_wakeup_0_phys == slots_13_prs2; wire _src2Wake_T_54 = io_wakeup_1_phys == slots_13_prs2; wire [5:0] _olderStorePending_diff_T_208 = slots_13_robIdx - slots_0_robIdx; wire [5:0] _olderStorePending_diff_T_209 = slots_13_robIdx - slots_1_robIdx; wire [5:0] _olderStorePending_diff_T_210 = slots_13_robIdx - slots_2_robIdx; wire [5:0] _olderStorePending_diff_T_211 = slots_13_robIdx - slots_3_robIdx; wire [5:0] _olderStorePending_diff_T_212 = slots_13_robIdx - slots_4_robIdx; wire [5:0] _olderStorePending_diff_T_213 = slots_13_robIdx - slots_5_robIdx; wire [5:0] _olderStorePending_diff_T_214 = slots_13_robIdx - slots_6_robIdx; wire [5:0] _olderStorePending_diff_T_215 = slots_13_robIdx - slots_7_robIdx; wire [5:0] _olderStorePending_diff_T_216 = slots_13_robIdx - slots_8_robIdx; wire [5:0] _olderStorePending_diff_T_217 = slots_13_robIdx - slots_9_robIdx; wire [5:0] _olderStorePending_diff_T_218 = slots_13_robIdx - slots_10_robIdx; wire [5:0] _olderStorePending_diff_T_219 = slots_13_robIdx - slots_11_robIdx; wire [5:0] _olderStorePending_diff_T_220 = slots_13_robIdx - slots_12_robIdx; wire [5:0] _olderStorePending_diff_T_222 = slots_13_robIdx - slots_14_robIdx; wire [5:0] _olderStorePending_diff_T_223 = slots_13_robIdx - slots_15_robIdx; wire readyVec_13 = valid_13 & (slots_13_src1Ready | io_wakeup_0_valid & _src1Wake_T_52 | io_wakeup_1_valid & _src1Wake_T_54 | slots_13_decoded_rs1 == 5'h0) & (slots_13_src2Ready | io_wakeup_0_valid & _src2Wake_T_52 | io_wakeup_1_valid & _src2Wake_T_54 | slots_13_decoded_rs2 == 5'h0) & ~((slots_13_decoded_isLoad | slots_13_decoded_isAmo) & (|{_olderStorePending_T_1545 & (|_olderStorePending_diff_T_223) & ~(_olderStorePending_diff_T_223[5]), _olderStorePending_T_1539 & (|_olderStorePending_diff_T_222) & ~(_olderStorePending_diff_T_222[5]), _olderStorePending_T_1527 & (|_olderStorePending_diff_T_220) & ~(_olderStorePending_diff_T_220[5]), _olderStorePending_T_1521 & (|_olderStorePending_diff_T_219) & ~(_olderStorePending_diff_T_219[5]), _olderStorePending_T_1515 & (|_olderStorePending_diff_T_218) & ~(_olderStorePending_diff_T_218[5]), _olderStorePending_T_1509 & (|_olderStorePending_diff_T_217) & ~(_olderStorePending_diff_T_217[5]), _olderStorePending_T_1503 & (|_olderStorePending_diff_T_216) & ~(_olderStorePending_diff_T_216[5]), _olderStorePending_T_1497 & (|_olderStorePending_diff_T_215) & ~(_olderStorePending_diff_T_215[5]), _olderStorePending_T_1491 & (|_olderStorePending_diff_T_214) & ~(_olderStorePending_diff_T_214[5]), _olderStorePending_T_1485 & (|_olderStorePending_diff_T_213) & ~(_olderStorePending_diff_T_213[5]), _olderStorePending_T_1479 & (|_olderStorePending_diff_T_212) & ~(_olderStorePending_diff_T_212[5]), _olderStorePending_T_1473 & (|_olderStorePending_diff_T_211) & ~(_olderStorePending_diff_T_211[5]), _olderStorePending_T_1467 & (|_olderStorePending_diff_T_210) & ~(_olderStorePending_diff_T_210[5]), _olderStorePending_T_1461 & (|_olderStorePending_diff_T_209) & ~(_olderStorePending_diff_T_209[5]), _olderStorePending_T_1455 & (|_olderStorePending_diff_T_208) & ~(_olderStorePending_diff_T_208[5])})) & (~(slots_13_decoded_isSystem | slots_13_decoded_isFenceI | slots_13_decoded_isSfenceVma | slots_13_decoded_isWfi) | io_robHeadValid & slots_13_robIdx == io_robHeadIdx); wire _src1Wake_T_56 = io_wakeup_0_phys == slots_14_prs1; wire _src1Wake_T_58 = io_wakeup_1_phys == slots_14_prs1; wire _src2Wake_T_56 = io_wakeup_0_phys == slots_14_prs2; wire _src2Wake_T_58 = io_wakeup_1_phys == slots_14_prs2; wire [5:0] _olderStorePending_diff_T_224 = slots_14_robIdx - slots_0_robIdx; wire [5:0] _olderStorePending_diff_T_225 = slots_14_robIdx - slots_1_robIdx; wire [5:0] _olderStorePending_diff_T_226 = slots_14_robIdx - slots_2_robIdx; wire [5:0] _olderStorePending_diff_T_227 = slots_14_robIdx - slots_3_robIdx; wire [5:0] _olderStorePending_diff_T_228 = slots_14_robIdx - slots_4_robIdx; wire [5:0] _olderStorePending_diff_T_229 = slots_14_robIdx - slots_5_robIdx; wire [5:0] _olderStorePending_diff_T_230 = slots_14_robIdx - slots_6_robIdx; wire [5:0] _olderStorePending_diff_T_231 = slots_14_robIdx - slots_7_robIdx; wire [5:0] _olderStorePending_diff_T_232 = slots_14_robIdx - slots_8_robIdx; wire [5:0] _olderStorePending_diff_T_233 = slots_14_robIdx - slots_9_robIdx; wire [5:0] _olderStorePending_diff_T_234 = slots_14_robIdx - slots_10_robIdx; wire [5:0] _olderStorePending_diff_T_235 = slots_14_robIdx - slots_11_robIdx; wire [5:0] _olderStorePending_diff_T_236 = slots_14_robIdx - slots_12_robIdx; wire [5:0] _olderStorePending_diff_T_237 = slots_14_robIdx - slots_13_robIdx; wire [5:0] _olderStorePending_diff_T_239 = slots_14_robIdx - slots_15_robIdx; wire readyVec_14 = valid_14 & (slots_14_src1Ready | io_wakeup_0_valid & _src1Wake_T_56 | io_wakeup_1_valid & _src1Wake_T_58 | slots_14_decoded_rs1 == 5'h0) & (slots_14_src2Ready | io_wakeup_0_valid & _src2Wake_T_56 | io_wakeup_1_valid & _src2Wake_T_58 | slots_14_decoded_rs2 == 5'h0) & ~((slots_14_decoded_isLoad | slots_14_decoded_isAmo) & (|{_olderStorePending_T_1545 & (|_olderStorePending_diff_T_239) & ~(_olderStorePending_diff_T_239[5]), _olderStorePending_T_1533 & (|_olderStorePending_diff_T_237) & ~(_olderStorePending_diff_T_237[5]), _olderStorePending_T_1527 & (|_olderStorePending_diff_T_236) & ~(_olderStorePending_diff_T_236[5]), _olderStorePending_T_1521 & (|_olderStorePending_diff_T_235) & ~(_olderStorePending_diff_T_235[5]), _olderStorePending_T_1515 & (|_olderStorePending_diff_T_234) & ~(_olderStorePending_diff_T_234[5]), _olderStorePending_T_1509 & (|_olderStorePending_diff_T_233) & ~(_olderStorePending_diff_T_233[5]), _olderStorePending_T_1503 & (|_olderStorePending_diff_T_232) & ~(_olderStorePending_diff_T_232[5]), _olderStorePending_T_1497 & (|_olderStorePending_diff_T_231) & ~(_olderStorePending_diff_T_231[5]), _olderStorePending_T_1491 & (|_olderStorePending_diff_T_230) & ~(_olderStorePending_diff_T_230[5]), _olderStorePending_T_1485 & (|_olderStorePending_diff_T_229) & ~(_olderStorePending_diff_T_229[5]), _olderStorePending_T_1479 & (|_olderStorePending_diff_T_228) & ~(_olderStorePending_diff_T_228[5]), _olderStorePending_T_1473 & (|_olderStorePending_diff_T_227) & ~(_olderStorePending_diff_T_227[5]), _olderStorePending_T_1467 & (|_olderStorePending_diff_T_226) & ~(_olderStorePending_diff_T_226[5]), _olderStorePending_T_1461 & (|_olderStorePending_diff_T_225) & ~(_olderStorePending_diff_T_225[5]), _olderStorePending_T_1455 & (|_olderStorePending_diff_T_224) & ~(_olderStorePending_diff_T_224[5])})) & (~(slots_14_decoded_isSystem | slots_14_decoded_isFenceI | slots_14_decoded_isSfenceVma | slots_14_decoded_isWfi) | io_robHeadValid & slots_14_robIdx == io_robHeadIdx); wire _src1Wake_T_60 = io_wakeup_0_phys == slots_15_prs1; wire _src1Wake_T_62 = io_wakeup_1_phys == slots_15_prs1; wire _src2Wake_T_60 = io_wakeup_0_phys == slots_15_prs2; wire _src2Wake_T_62 = io_wakeup_1_phys == slots_15_prs2; wire [5:0] _olderStorePending_diff_T_240 = slots_15_robIdx - slots_0_robIdx; wire [5:0] _olderStorePending_diff_T_241 = slots_15_robIdx - slots_1_robIdx; wire [5:0] _olderStorePending_diff_T_242 = slots_15_robIdx - slots_2_robIdx; wire [5:0] _olderStorePending_diff_T_243 = slots_15_robIdx - slots_3_robIdx; wire [5:0] _olderStorePending_diff_T_244 = slots_15_robIdx - slots_4_robIdx; wire [5:0] _olderStorePending_diff_T_245 = slots_15_robIdx - slots_5_robIdx; wire [5:0] _olderStorePending_diff_T_246 = slots_15_robIdx - slots_6_robIdx; wire [5:0] _olderStorePending_diff_T_247 = slots_15_robIdx - slots_7_robIdx; wire [5:0] _olderStorePending_diff_T_248 = slots_15_robIdx - slots_8_robIdx; wire [5:0] _olderStorePending_diff_T_249 = slots_15_robIdx - slots_9_robIdx; wire [5:0] _olderStorePending_diff_T_250 = slots_15_robIdx - slots_10_robIdx; wire [5:0] _olderStorePending_diff_T_251 = slots_15_robIdx - slots_11_robIdx; wire [5:0] _olderStorePending_diff_T_252 = slots_15_robIdx - slots_12_robIdx; wire [5:0] _olderStorePending_diff_T_253 = slots_15_robIdx - slots_13_robIdx; wire [5:0] _olderStorePending_diff_T_254 = slots_15_robIdx - slots_14_robIdx; wire readyVec_15 = valid_15 & (slots_15_src1Ready | io_wakeup_0_valid & _src1Wake_T_60 | io_wakeup_1_valid & _src1Wake_T_62 | slots_15_decoded_rs1 == 5'h0) & (slots_15_src2Ready | io_wakeup_0_valid & _src2Wake_T_60 | io_wakeup_1_valid & _src2Wake_T_62 | slots_15_decoded_rs2 == 5'h0) & ~((slots_15_decoded_isLoad | slots_15_decoded_isAmo) & (|{_olderStorePending_T_1539 & (|_olderStorePending_diff_T_254) & ~(_olderStorePending_diff_T_254[5]), _olderStorePending_T_1533 & (|_olderStorePending_diff_T_253) & ~(_olderStorePending_diff_T_253[5]), _olderStorePending_T_1527 & (|_olderStorePending_diff_T_252) & ~(_olderStorePending_diff_T_252[5]), _olderStorePending_T_1521 & (|_olderStorePending_diff_T_251) & ~(_olderStorePending_diff_T_251[5]), _olderStorePending_T_1515 & (|_olderStorePending_diff_T_250) & ~(_olderStorePending_diff_T_250[5]), _olderStorePending_T_1509 & (|_olderStorePending_diff_T_249) & ~(_olderStorePending_diff_T_249[5]), _olderStorePending_T_1503 & (|_olderStorePending_diff_T_248) & ~(_olderStorePending_diff_T_248[5]), _olderStorePending_T_1497 & (|_olderStorePending_diff_T_247) & ~(_olderStorePending_diff_T_247[5]), _olderStorePending_T_1491 & (|_olderStorePending_diff_T_246) & ~(_olderStorePending_diff_T_246[5]), _olderStorePending_T_1485 & (|_olderStorePending_diff_T_245) & ~(_olderStorePending_diff_T_245[5]), _olderStorePending_T_1479 & (|_olderStorePending_diff_T_244) & ~(_olderStorePending_diff_T_244[5]), _olderStorePending_T_1473 & (|_olderStorePending_diff_T_243) & ~(_olderStorePending_diff_T_243[5]), _olderStorePending_T_1467 & (|_olderStorePending_diff_T_242) & ~(_olderStorePending_diff_T_242[5]), _olderStorePending_T_1461 & (|_olderStorePending_diff_T_241) & ~(_olderStorePending_diff_T_241[5]), _olderStorePending_T_1455 & (|_olderStorePending_diff_T_240) & ~(_olderStorePending_diff_T_240[5])})) & (~(slots_15_decoded_isSystem | slots_15_decoded_isFenceI | slots_15_decoded_isSfenceVma | slots_15_decoded_isWfi) | io_robHeadValid & slots_15_robIdx == io_robHeadIdx); wire [15:0] _io_issueValid_1_T = {readyVec_15, readyVec_14, readyVec_13, readyVec_12, readyVec_11, readyVec_10, readyVec_9, readyVec_8, readyVec_7, readyVec_6, readyVec_5, readyVec_4, readyVec_3, readyVec_2, readyVec_1, readyVec_0}; wire [15:0] issue0OH = readyVec_0 ? 16'h1 : readyVec_1 ? 16'h2 : readyVec_2 ? 16'h4 : readyVec_3 ? 16'h8 : readyVec_4 ? 16'h10 : readyVec_5 ? 16'h20 : readyVec_6 ? 16'h40 : readyVec_7 ? 16'h80 : readyVec_8 ? 16'h100 : readyVec_9 ? 16'h200 : readyVec_10 ? 16'h400 : readyVec_11 ? 16'h800 : readyVec_12 ? 16'h1000 : readyVec_13 ? 16'h2000 : readyVec_14 ? 16'h4000 : {readyVec_15, 15'h0}; wire [15:0] _io_issueValid_1_T_1 = ~issue0OH; wire [15:0] issue1OH = readyVec_0 & _io_issueValid_1_T_1[0] ? 16'h1 : readyVec_1 & _io_issueValid_1_T_1[1] ? 16'h2 : readyVec_2 & _io_issueValid_1_T_1[2] ? 16'h4 : readyVec_3 & _io_issueValid_1_T_1[3] ? 16'h8 : readyVec_4 & _io_issueValid_1_T_1[4] ? 16'h10 : readyVec_5 & _io_issueValid_1_T_1[5] ? 16'h20 : readyVec_6 & _io_issueValid_1_T_1[6] ? 16'h40 : readyVec_7 & _io_issueValid_1_T_1[7] ? 16'h80 : readyVec_8 & _io_issueValid_1_T_1[8] ? 16'h100 : readyVec_9 & _io_issueValid_1_T_1[9] ? 16'h200 : readyVec_10 & _io_issueValid_1_T_1[10] ? 16'h400 : readyVec_11 & _io_issueValid_1_T_1[11] ? 16'h800 : readyVec_12 & _io_issueValid_1_T_1[12] ? 16'h1000 : readyVec_13 & _io_issueValid_1_T_1[13] ? 16'h2000 : readyVec_14 & _io_issueValid_1_T_1[14] ? 16'h4000 : {readyVec_15 & _io_issueValid_1_T_1[15], 15'h0}; always @(posedge clock) begin automatic logic [15:0] enq1OH = ~valid_0 & _io_enqReady_1_T[0] ? 16'h1 : ~valid_1 & _io_enqReady_1_T[1] ? 16'h2 : ~valid_2 & _io_enqReady_1_T[2] ? 16'h4 : ~valid_3 & _io_enqReady_1_T[3] ? 16'h8 : ~valid_4 & _io_enqReady_1_T[4] ? 16'h10 : ~valid_5 & _io_enqReady_1_T[5] ? 16'h20 : ~valid_6 & _io_enqReady_1_T[6] ? 16'h40 : ~valid_7 & _io_enqReady_1_T[7] ? 16'h80 : ~valid_8 & _io_enqReady_1_T[8] ? 16'h100 : ~valid_9 & _io_enqReady_1_T[9] ? 16'h200 : ~valid_10 & _io_enqReady_1_T[10] ? 16'h400 : ~valid_11 & _io_enqReady_1_T[11] ? 16'h800 : ~valid_12 & _io_enqReady_1_T[12] ? 16'h1000 : ~valid_13 & _io_enqReady_1_T[13] ? 16'h2000 : ~valid_14 & _io_enqReady_1_T[14] ? 16'h4000 : {~valid_15 & _io_enqReady_1_T[15], 15'h0}; automatic logic _GEN; automatic logic _GEN_0; automatic logic _GEN_1; automatic logic _GEN_2; automatic logic _GEN_3; automatic logic _GEN_4; automatic logic _GEN_5; automatic logic _GEN_6; automatic logic _GEN_7; automatic logic _GEN_8; automatic logic _GEN_9; automatic logic _GEN_10; automatic logic _GEN_11; automatic logic _GEN_12; automatic logic _GEN_13; automatic logic _GEN_14; automatic logic _GEN_15; automatic logic _GEN_16; automatic logic _GEN_17; automatic logic _GEN_18; automatic logic _GEN_19; automatic logic _GEN_20; automatic logic _GEN_21; automatic logic _GEN_22; automatic logic _GEN_23; automatic logic _GEN_24; automatic logic _GEN_25; automatic logic _GEN_26; automatic logic _GEN_27; automatic logic _GEN_28; automatic logic _GEN_29; automatic logic _GEN_30; _GEN = enq0OH[0] & io_enqValid_0 & (|freeMask); _GEN_0 = enq1OH[0] & io_enqValid_1 & (|_io_enqReady_1_T_1); _GEN_1 = enq0OH[1] & io_enqValid_0 & (|freeMask); _GEN_2 = enq1OH[1] & io_enqValid_1 & (|_io_enqReady_1_T_1); _GEN_3 = enq0OH[2] & io_enqValid_0 & (|freeMask); _GEN_4 = enq1OH[2] & io_enqValid_1 & (|_io_enqReady_1_T_1); _GEN_5 = enq0OH[3] & io_enqValid_0 & (|freeMask); _GEN_6 = enq1OH[3] & io_enqValid_1 & (|_io_enqReady_1_T_1); _GEN_7 = enq0OH[4] & io_enqValid_0 & (|freeMask); _GEN_8 = enq1OH[4] & io_enqValid_1 & (|_io_enqReady_1_T_1); _GEN_9 = enq0OH[5] & io_enqValid_0 & (|freeMask); _GEN_10 = enq1OH[5] & io_enqValid_1 & (|_io_enqReady_1_T_1); _GEN_11 = enq0OH[6] & io_enqValid_0 & (|freeMask); _GEN_12 = enq1OH[6] & io_enqValid_1 & (|_io_enqReady_1_T_1); _GEN_13 = enq0OH[7] & io_enqValid_0 & (|freeMask); _GEN_14 = enq1OH[7] & io_enqValid_1 & (|_io_enqReady_1_T_1); _GEN_15 = enq0OH[8] & io_enqValid_0 & (|freeMask); _GEN_16 = enq1OH[8] & io_enqValid_1 & (|_io_enqReady_1_T_1); _GEN_17 = enq0OH[9] & io_enqValid_0 & (|freeMask); _GEN_18 = enq1OH[9] & io_enqValid_1 & (|_io_enqReady_1_T_1); _GEN_19 = enq0OH[10] & io_enqValid_0 & (|freeMask); _GEN_20 = enq1OH[10] & io_enqValid_1 & (|_io_enqReady_1_T_1); _GEN_21 = enq0OH[11] & io_enqValid_0 & (|freeMask); _GEN_22 = enq1OH[11] & io_enqValid_1 & (|_io_enqReady_1_T_1); _GEN_23 = enq0OH[12] & io_enqValid_0 & (|freeMask); _GEN_24 = enq1OH[12] & io_enqValid_1 & (|_io_enqReady_1_T_1); _GEN_25 = enq0OH[13] & io_enqValid_0 & (|freeMask); _GEN_26 = enq1OH[13] & io_enqValid_1 & (|_io_enqReady_1_T_1); _GEN_27 = enq0OH[14] & io_enqValid_0 & (|freeMask); _GEN_28 = enq1OH[14] & io_enqValid_1 & (|_io_enqReady_1_T_1); _GEN_29 = enq0OH[15] & io_enqValid_0 & (|freeMask); _GEN_30 = enq1OH[15] & io_enqValid_1 & (|_io_enqReady_1_T_1); if (reset) begin valid_0 <= 1'h0; valid_1 <= 1'h0; valid_2 <= 1'h0; valid_3 <= 1'h0; valid_4 <= 1'h0; valid_5 <= 1'h0; valid_6 <= 1'h0; valid_7 <= 1'h0; valid_8 <= 1'h0; valid_9 <= 1'h0; valid_10 <= 1'h0; valid_11 <= 1'h0; valid_12 <= 1'h0; valid_13 <= 1'h0; valid_14 <= 1'h0; valid_15 <= 1'h0; end else begin valid_0 <= ~io_flush & (_GEN_0 | _GEN | ~(issue1OH[0] & io_issueReady_1 | issue0OH[0] & io_issueReady_0) & valid_0); valid_1 <= ~io_flush & (_GEN_2 | _GEN_1 | ~(issue1OH[1] & io_issueReady_1 | issue0OH[1] & io_issueReady_0) & valid_1); valid_2 <= ~io_flush & (_GEN_4 | _GEN_3 | ~(issue1OH[2] & io_issueReady_1 | issue0OH[2] & io_issueReady_0) & valid_2); valid_3 <= ~io_flush & (_GEN_6 | _GEN_5 | ~(issue1OH[3] & io_issueReady_1 | issue0OH[3] & io_issueReady_0) & valid_3); valid_4 <= ~io_flush & (_GEN_8 | _GEN_7 | ~(issue1OH[4] & io_issueReady_1 | issue0OH[4] & io_issueReady_0) & valid_4); valid_5 <= ~io_flush & (_GEN_10 | _GEN_9 | ~(issue1OH[5] & io_issueReady_1 | issue0OH[5] & io_issueReady_0) & valid_5); valid_6 <= ~io_flush & (_GEN_12 | _GEN_11 | ~(issue1OH[6] & io_issueReady_1 | issue0OH[6] & io_issueReady_0) & valid_6); valid_7 <= ~io_flush & (_GEN_14 | _GEN_13 | ~(issue1OH[7] & io_issueReady_1 | issue0OH[7] & io_issueReady_0) & valid_7); valid_8 <= ~io_flush & (_GEN_16 | _GEN_15 | ~(issue1OH[8] & io_issueReady_1 | issue0OH[8] & io_issueReady_0) & valid_8); valid_9 <= ~io_flush & (_GEN_18 | _GEN_17 | ~(issue1OH[9] & io_issueReady_1 | issue0OH[9] & io_issueReady_0) & valid_9); valid_10 <= ~io_flush & (_GEN_20 | _GEN_19 | ~(issue1OH[10] & io_issueReady_1 | issue0OH[10] & io_issueReady_0) & valid_10); valid_11 <= ~io_flush & (_GEN_22 | _GEN_21 | ~(issue1OH[11] & io_issueReady_1 | issue0OH[11] & io_issueReady_0) & valid_11); valid_12 <= ~io_flush & (_GEN_24 | _GEN_23 | ~(issue1OH[12] & io_issueReady_1 | issue0OH[12] & io_issueReady_0) & valid_12); valid_13 <= ~io_flush & (_GEN_26 | _GEN_25 | ~(issue1OH[13] & io_issueReady_1 | issue0OH[13] & io_issueReady_0) & valid_13); valid_14 <= ~io_flush & (_GEN_28 | _GEN_27 | ~(issue1OH[14] & io_issueReady_1 | issue0OH[14] & io_issueReady_0) & valid_14); valid_15 <= ~io_flush & (_GEN_30 | _GEN_29 | ~(issue1OH[15] & io_issueReady_1 | issue0OH[15] & io_issueReady_0) & valid_15); end if (io_flush) begin end else begin if (_GEN_0) begin slots_0_decoded_pc <= io_enq_1_decoded_pc; slots_0_decoded_inst <= io_enq_1_decoded_inst; slots_0_decoded_rs1 <= io_enq_1_decoded_rs1; slots_0_decoded_rs2 <= io_enq_1_decoded_rs2; slots_0_decoded_funct3 <= io_enq_1_decoded_funct3; slots_0_decoded_immI <= io_enq_1_decoded_immI; slots_0_decoded_immS <= io_enq_1_decoded_immS; slots_0_decoded_immB <= io_enq_1_decoded_immB; slots_0_decoded_immU <= io_enq_1_decoded_immU; slots_0_decoded_immJ <= io_enq_1_decoded_immJ; slots_0_decoded_aluFn <= io_enq_1_decoded_aluFn; slots_0_decoded_memWidth <= io_enq_1_decoded_memWidth; slots_0_decoded_memSigned <= io_enq_1_decoded_memSigned; slots_0_decoded_isLoad <= io_enq_1_decoded_isLoad; slots_0_decoded_isStore <= io_enq_1_decoded_isStore; slots_0_decoded_isBranch <= io_enq_1_decoded_isBranch; slots_0_decoded_isJal <= io_enq_1_decoded_isJal; slots_0_decoded_isJalr <= io_enq_1_decoded_isJalr; slots_0_decoded_isLui <= io_enq_1_decoded_isLui; slots_0_decoded_isAuipc <= io_enq_1_decoded_isAuipc; slots_0_decoded_isOpImm <= io_enq_1_decoded_isOpImm; slots_0_decoded_isWord <= io_enq_1_decoded_isWord; slots_0_decoded_isSystem <= io_enq_1_decoded_isSystem; slots_0_decoded_isFenceI <= io_enq_1_decoded_isFenceI; slots_0_decoded_isEcall <= io_enq_1_decoded_isEcall; slots_0_decoded_isEbreak <= io_enq_1_decoded_isEbreak; slots_0_decoded_isMret <= io_enq_1_decoded_isMret; slots_0_decoded_isSret <= io_enq_1_decoded_isSret; slots_0_decoded_isSfenceVma <= io_enq_1_decoded_isSfenceVma; slots_0_decoded_isXret <= io_enq_1_decoded_isXret; slots_0_decoded_isWfi <= io_enq_1_decoded_isWfi; slots_0_decoded_isAmo <= io_enq_1_decoded_isAmo; slots_0_decoded_amoOp <= io_enq_1_decoded_amoOp; slots_0_decoded_writesRd <= io_enq_1_decoded_writesRd; slots_0_decoded_illegal <= io_enq_1_decoded_illegal; slots_0_decoded_fetchException <= io_enq_1_decoded_fetchException; slots_0_decoded_fetchExceptionCause <= io_enq_1_decoded_fetchExceptionCause; slots_0_decoded_fetchExceptionTval <= io_enq_1_decoded_fetchExceptionTval; slots_0_prs1 <= io_enq_1_prs1; slots_0_prs2 <= io_enq_1_prs2; slots_0_prd <= io_enq_1_prd; slots_0_robIdx <= io_enq_1_robIdx; end else if (_GEN) begin slots_0_decoded_pc <= io_enq_0_decoded_pc; slots_0_decoded_inst <= io_enq_0_decoded_inst; slots_0_decoded_rs1 <= io_enq_0_decoded_rs1; slots_0_decoded_rs2 <= io_enq_0_decoded_rs2; slots_0_decoded_funct3 <= io_enq_0_decoded_funct3; slots_0_decoded_immI <= io_enq_0_decoded_immI; slots_0_decoded_immS <= io_enq_0_decoded_immS; slots_0_decoded_immB <= io_enq_0_decoded_immB; slots_0_decoded_immU <= io_enq_0_decoded_immU; slots_0_decoded_immJ <= io_enq_0_decoded_immJ; slots_0_decoded_aluFn <= io_enq_0_decoded_aluFn; slots_0_decoded_memWidth <= io_enq_0_decoded_memWidth; slots_0_decoded_memSigned <= io_enq_0_decoded_memSigned; slots_0_decoded_isLoad <= io_enq_0_decoded_isLoad; slots_0_decoded_isStore <= io_enq_0_decoded_isStore; slots_0_decoded_isBranch <= io_enq_0_decoded_isBranch; slots_0_decoded_isJal <= io_enq_0_decoded_isJal; slots_0_decoded_isJalr <= io_enq_0_decoded_isJalr; slots_0_decoded_isLui <= io_enq_0_decoded_isLui; slots_0_decoded_isAuipc <= io_enq_0_decoded_isAuipc; slots_0_decoded_isOpImm <= io_enq_0_decoded_isOpImm; slots_0_decoded_isWord <= io_enq_0_decoded_isWord; slots_0_decoded_isSystem <= io_enq_0_decoded_isSystem; slots_0_decoded_isFenceI <= io_enq_0_decoded_isFenceI; slots_0_decoded_isEcall <= io_enq_0_decoded_isEcall; slots_0_decoded_isEbreak <= io_enq_0_decoded_isEbreak; slots_0_decoded_isMret <= io_enq_0_decoded_isMret; slots_0_decoded_isSret <= io_enq_0_decoded_isSret; slots_0_decoded_isSfenceVma <= io_enq_0_decoded_isSfenceVma; slots_0_decoded_isXret <= io_enq_0_decoded_isXret; slots_0_decoded_isWfi <= io_enq_0_decoded_isWfi; slots_0_decoded_isAmo <= io_enq_0_decoded_isAmo; slots_0_decoded_amoOp <= io_enq_0_decoded_amoOp; slots_0_decoded_writesRd <= io_enq_0_decoded_writesRd; slots_0_decoded_illegal <= io_enq_0_decoded_illegal; slots_0_decoded_fetchException <= io_enq_0_decoded_fetchException; slots_0_decoded_fetchExceptionCause <= io_enq_0_decoded_fetchExceptionCause; slots_0_decoded_fetchExceptionTval <= io_enq_0_decoded_fetchExceptionTval; slots_0_prs1 <= io_enq_0_prs1; slots_0_prs2 <= io_enq_0_prs2; slots_0_prd <= io_enq_0_prd; slots_0_robIdx <= io_enq_0_robIdx; end slots_0_src1Ready <= _GEN_0 ? io_enq_1_src1Ready : _GEN ? io_enq_0_src1Ready : valid_0 & (io_wakeup_1_valid & _src1Wake_T_2 | io_wakeup_0_valid & _src1Wake_T) | slots_0_src1Ready; slots_0_src2Ready <= _GEN_0 ? io_enq_1_src2Ready : _GEN ? io_enq_0_src2Ready : valid_0 & (io_wakeup_1_valid & _src2Wake_T_2 | io_wakeup_0_valid & _src2Wake_T) | slots_0_src2Ready; if (_GEN_2) begin slots_1_decoded_pc <= io_enq_1_decoded_pc; slots_1_decoded_inst <= io_enq_1_decoded_inst; slots_1_decoded_rs1 <= io_enq_1_decoded_rs1; slots_1_decoded_rs2 <= io_enq_1_decoded_rs2; slots_1_decoded_funct3 <= io_enq_1_decoded_funct3; slots_1_decoded_immI <= io_enq_1_decoded_immI; slots_1_decoded_immS <= io_enq_1_decoded_immS; slots_1_decoded_immB <= io_enq_1_decoded_immB; slots_1_decoded_immU <= io_enq_1_decoded_immU; slots_1_decoded_immJ <= io_enq_1_decoded_immJ; slots_1_decoded_aluFn <= io_enq_1_decoded_aluFn; slots_1_decoded_memWidth <= io_enq_1_decoded_memWidth; slots_1_decoded_memSigned <= io_enq_1_decoded_memSigned; slots_1_decoded_isLoad <= io_enq_1_decoded_isLoad; slots_1_decoded_isStore <= io_enq_1_decoded_isStore; slots_1_decoded_isBranch <= io_enq_1_decoded_isBranch; slots_1_decoded_isJal <= io_enq_1_decoded_isJal; slots_1_decoded_isJalr <= io_enq_1_decoded_isJalr; slots_1_decoded_isLui <= io_enq_1_decoded_isLui; slots_1_decoded_isAuipc <= io_enq_1_decoded_isAuipc; slots_1_decoded_isOpImm <= io_enq_1_decoded_isOpImm; slots_1_decoded_isWord <= io_enq_1_decoded_isWord; slots_1_decoded_isSystem <= io_enq_1_decoded_isSystem; slots_1_decoded_isFenceI <= io_enq_1_decoded_isFenceI; slots_1_decoded_isEcall <= io_enq_1_decoded_isEcall; slots_1_decoded_isEbreak <= io_enq_1_decoded_isEbreak; slots_1_decoded_isMret <= io_enq_1_decoded_isMret; slots_1_decoded_isSret <= io_enq_1_decoded_isSret; slots_1_decoded_isSfenceVma <= io_enq_1_decoded_isSfenceVma; slots_1_decoded_isXret <= io_enq_1_decoded_isXret; slots_1_decoded_isWfi <= io_enq_1_decoded_isWfi; slots_1_decoded_isAmo <= io_enq_1_decoded_isAmo; slots_1_decoded_amoOp <= io_enq_1_decoded_amoOp; slots_1_decoded_writesRd <= io_enq_1_decoded_writesRd; slots_1_decoded_illegal <= io_enq_1_decoded_illegal; slots_1_decoded_fetchException <= io_enq_1_decoded_fetchException; slots_1_decoded_fetchExceptionCause <= io_enq_1_decoded_fetchExceptionCause; slots_1_decoded_fetchExceptionTval <= io_enq_1_decoded_fetchExceptionTval; slots_1_prs1 <= io_enq_1_prs1; slots_1_prs2 <= io_enq_1_prs2; slots_1_prd <= io_enq_1_prd; slots_1_robIdx <= io_enq_1_robIdx; end else if (_GEN_1) begin slots_1_decoded_pc <= io_enq_0_decoded_pc; slots_1_decoded_inst <= io_enq_0_decoded_inst; slots_1_decoded_rs1 <= io_enq_0_decoded_rs1; slots_1_decoded_rs2 <= io_enq_0_decoded_rs2; slots_1_decoded_funct3 <= io_enq_0_decoded_funct3; slots_1_decoded_immI <= io_enq_0_decoded_immI; slots_1_decoded_immS <= io_enq_0_decoded_immS; slots_1_decoded_immB <= io_enq_0_decoded_immB; slots_1_decoded_immU <= io_enq_0_decoded_immU; slots_1_decoded_immJ <= io_enq_0_decoded_immJ; slots_1_decoded_aluFn <= io_enq_0_decoded_aluFn; slots_1_decoded_memWidth <= io_enq_0_decoded_memWidth; slots_1_decoded_memSigned <= io_enq_0_decoded_memSigned; slots_1_decoded_isLoad <= io_enq_0_decoded_isLoad; slots_1_decoded_isStore <= io_enq_0_decoded_isStore; slots_1_decoded_isBranch <= io_enq_0_decoded_isBranch; slots_1_decoded_isJal <= io_enq_0_decoded_isJal; slots_1_decoded_isJalr <= io_enq_0_decoded_isJalr; slots_1_decoded_isLui <= io_enq_0_decoded_isLui; slots_1_decoded_isAuipc <= io_enq_0_decoded_isAuipc; slots_1_decoded_isOpImm <= io_enq_0_decoded_isOpImm; slots_1_decoded_isWord <= io_enq_0_decoded_isWord; slots_1_decoded_isSystem <= io_enq_0_decoded_isSystem; slots_1_decoded_isFenceI <= io_enq_0_decoded_isFenceI; slots_1_decoded_isEcall <= io_enq_0_decoded_isEcall; slots_1_decoded_isEbreak <= io_enq_0_decoded_isEbreak; slots_1_decoded_isMret <= io_enq_0_decoded_isMret; slots_1_decoded_isSret <= io_enq_0_decoded_isSret; slots_1_decoded_isSfenceVma <= io_enq_0_decoded_isSfenceVma; slots_1_decoded_isXret <= io_enq_0_decoded_isXret; slots_1_decoded_isWfi <= io_enq_0_decoded_isWfi; slots_1_decoded_isAmo <= io_enq_0_decoded_isAmo; slots_1_decoded_amoOp <= io_enq_0_decoded_amoOp; slots_1_decoded_writesRd <= io_enq_0_decoded_writesRd; slots_1_decoded_illegal <= io_enq_0_decoded_illegal; slots_1_decoded_fetchException <= io_enq_0_decoded_fetchException; slots_1_decoded_fetchExceptionCause <= io_enq_0_decoded_fetchExceptionCause; slots_1_decoded_fetchExceptionTval <= io_enq_0_decoded_fetchExceptionTval; slots_1_prs1 <= io_enq_0_prs1; slots_1_prs2 <= io_enq_0_prs2; slots_1_prd <= io_enq_0_prd; slots_1_robIdx <= io_enq_0_robIdx; end slots_1_src1Ready <= _GEN_2 ? io_enq_1_src1Ready : _GEN_1 ? io_enq_0_src1Ready : valid_1 & (io_wakeup_1_valid & _src1Wake_T_6 | io_wakeup_0_valid & _src1Wake_T_4) | slots_1_src1Ready; slots_1_src2Ready <= _GEN_2 ? io_enq_1_src2Ready : _GEN_1 ? io_enq_0_src2Ready : valid_1 & (io_wakeup_1_valid & _src2Wake_T_6 | io_wakeup_0_valid & _src2Wake_T_4) | slots_1_src2Ready; if (_GEN_4) begin slots_2_decoded_pc <= io_enq_1_decoded_pc; slots_2_decoded_inst <= io_enq_1_decoded_inst; slots_2_decoded_rs1 <= io_enq_1_decoded_rs1; slots_2_decoded_rs2 <= io_enq_1_decoded_rs2; slots_2_decoded_funct3 <= io_enq_1_decoded_funct3; slots_2_decoded_immI <= io_enq_1_decoded_immI; slots_2_decoded_immS <= io_enq_1_decoded_immS; slots_2_decoded_immB <= io_enq_1_decoded_immB; slots_2_decoded_immU <= io_enq_1_decoded_immU; slots_2_decoded_immJ <= io_enq_1_decoded_immJ; slots_2_decoded_aluFn <= io_enq_1_decoded_aluFn; slots_2_decoded_memWidth <= io_enq_1_decoded_memWidth; slots_2_decoded_memSigned <= io_enq_1_decoded_memSigned; slots_2_decoded_isLoad <= io_enq_1_decoded_isLoad; slots_2_decoded_isStore <= io_enq_1_decoded_isStore; slots_2_decoded_isBranch <= io_enq_1_decoded_isBranch; slots_2_decoded_isJal <= io_enq_1_decoded_isJal; slots_2_decoded_isJalr <= io_enq_1_decoded_isJalr; slots_2_decoded_isLui <= io_enq_1_decoded_isLui; slots_2_decoded_isAuipc <= io_enq_1_decoded_isAuipc; slots_2_decoded_isOpImm <= io_enq_1_decoded_isOpImm; slots_2_decoded_isWord <= io_enq_1_decoded_isWord; slots_2_decoded_isSystem <= io_enq_1_decoded_isSystem; slots_2_decoded_isFenceI <= io_enq_1_decoded_isFenceI; slots_2_decoded_isEcall <= io_enq_1_decoded_isEcall; slots_2_decoded_isEbreak <= io_enq_1_decoded_isEbreak; slots_2_decoded_isMret <= io_enq_1_decoded_isMret; slots_2_decoded_isSret <= io_enq_1_decoded_isSret; slots_2_decoded_isSfenceVma <= io_enq_1_decoded_isSfenceVma; slots_2_decoded_isXret <= io_enq_1_decoded_isXret; slots_2_decoded_isWfi <= io_enq_1_decoded_isWfi; slots_2_decoded_isAmo <= io_enq_1_decoded_isAmo; slots_2_decoded_amoOp <= io_enq_1_decoded_amoOp; slots_2_decoded_writesRd <= io_enq_1_decoded_writesRd; slots_2_decoded_illegal <= io_enq_1_decoded_illegal; slots_2_decoded_fetchException <= io_enq_1_decoded_fetchException; slots_2_decoded_fetchExceptionCause <= io_enq_1_decoded_fetchExceptionCause; slots_2_decoded_fetchExceptionTval <= io_enq_1_decoded_fetchExceptionTval; slots_2_prs1 <= io_enq_1_prs1; slots_2_prs2 <= io_enq_1_prs2; slots_2_prd <= io_enq_1_prd; slots_2_robIdx <= io_enq_1_robIdx; end else if (_GEN_3) begin slots_2_decoded_pc <= io_enq_0_decoded_pc; slots_2_decoded_inst <= io_enq_0_decoded_inst; slots_2_decoded_rs1 <= io_enq_0_decoded_rs1; slots_2_decoded_rs2 <= io_enq_0_decoded_rs2; slots_2_decoded_funct3 <= io_enq_0_decoded_funct3; slots_2_decoded_immI <= io_enq_0_decoded_immI; slots_2_decoded_immS <= io_enq_0_decoded_immS; slots_2_decoded_immB <= io_enq_0_decoded_immB; slots_2_decoded_immU <= io_enq_0_decoded_immU; slots_2_decoded_immJ <= io_enq_0_decoded_immJ; slots_2_decoded_aluFn <= io_enq_0_decoded_aluFn; slots_2_decoded_memWidth <= io_enq_0_decoded_memWidth; slots_2_decoded_memSigned <= io_enq_0_decoded_memSigned; slots_2_decoded_isLoad <= io_enq_0_decoded_isLoad; slots_2_decoded_isStore <= io_enq_0_decoded_isStore; slots_2_decoded_isBranch <= io_enq_0_decoded_isBranch; slots_2_decoded_isJal <= io_enq_0_decoded_isJal; slots_2_decoded_isJalr <= io_enq_0_decoded_isJalr; slots_2_decoded_isLui <= io_enq_0_decoded_isLui; slots_2_decoded_isAuipc <= io_enq_0_decoded_isAuipc; slots_2_decoded_isOpImm <= io_enq_0_decoded_isOpImm; slots_2_decoded_isWord <= io_enq_0_decoded_isWord; slots_2_decoded_isSystem <= io_enq_0_decoded_isSystem; slots_2_decoded_isFenceI <= io_enq_0_decoded_isFenceI; slots_2_decoded_isEcall <= io_enq_0_decoded_isEcall; slots_2_decoded_isEbreak <= io_enq_0_decoded_isEbreak; slots_2_decoded_isMret <= io_enq_0_decoded_isMret; slots_2_decoded_isSret <= io_enq_0_decoded_isSret; slots_2_decoded_isSfenceVma <= io_enq_0_decoded_isSfenceVma; slots_2_decoded_isXret <= io_enq_0_decoded_isXret; slots_2_decoded_isWfi <= io_enq_0_decoded_isWfi; slots_2_decoded_isAmo <= io_enq_0_decoded_isAmo; slots_2_decoded_amoOp <= io_enq_0_decoded_amoOp; slots_2_decoded_writesRd <= io_enq_0_decoded_writesRd; slots_2_decoded_illegal <= io_enq_0_decoded_illegal; slots_2_decoded_fetchException <= io_enq_0_decoded_fetchException; slots_2_decoded_fetchExceptionCause <= io_enq_0_decoded_fetchExceptionCause; slots_2_decoded_fetchExceptionTval <= io_enq_0_decoded_fetchExceptionTval; slots_2_prs1 <= io_enq_0_prs1; slots_2_prs2 <= io_enq_0_prs2; slots_2_prd <= io_enq_0_prd; slots_2_robIdx <= io_enq_0_robIdx; end slots_2_src1Ready <= _GEN_4 ? io_enq_1_src1Ready : _GEN_3 ? io_enq_0_src1Ready : valid_2 & (io_wakeup_1_valid & _src1Wake_T_10 | io_wakeup_0_valid & _src1Wake_T_8) | slots_2_src1Ready; slots_2_src2Ready <= _GEN_4 ? io_enq_1_src2Ready : _GEN_3 ? io_enq_0_src2Ready : valid_2 & (io_wakeup_1_valid & _src2Wake_T_10 | io_wakeup_0_valid & _src2Wake_T_8) | slots_2_src2Ready; if (_GEN_6) begin slots_3_decoded_pc <= io_enq_1_decoded_pc; slots_3_decoded_inst <= io_enq_1_decoded_inst; slots_3_decoded_rs1 <= io_enq_1_decoded_rs1; slots_3_decoded_rs2 <= io_enq_1_decoded_rs2; slots_3_decoded_funct3 <= io_enq_1_decoded_funct3; slots_3_decoded_immI <= io_enq_1_decoded_immI; slots_3_decoded_immS <= io_enq_1_decoded_immS; slots_3_decoded_immB <= io_enq_1_decoded_immB; slots_3_decoded_immU <= io_enq_1_decoded_immU; slots_3_decoded_immJ <= io_enq_1_decoded_immJ; slots_3_decoded_aluFn <= io_enq_1_decoded_aluFn; slots_3_decoded_memWidth <= io_enq_1_decoded_memWidth; slots_3_decoded_memSigned <= io_enq_1_decoded_memSigned; slots_3_decoded_isLoad <= io_enq_1_decoded_isLoad; slots_3_decoded_isStore <= io_enq_1_decoded_isStore; slots_3_decoded_isBranch <= io_enq_1_decoded_isBranch; slots_3_decoded_isJal <= io_enq_1_decoded_isJal; slots_3_decoded_isJalr <= io_enq_1_decoded_isJalr; slots_3_decoded_isLui <= io_enq_1_decoded_isLui; slots_3_decoded_isAuipc <= io_enq_1_decoded_isAuipc; slots_3_decoded_isOpImm <= io_enq_1_decoded_isOpImm; slots_3_decoded_isWord <= io_enq_1_decoded_isWord; slots_3_decoded_isSystem <= io_enq_1_decoded_isSystem; slots_3_decoded_isFenceI <= io_enq_1_decoded_isFenceI; slots_3_decoded_isEcall <= io_enq_1_decoded_isEcall; slots_3_decoded_isEbreak <= io_enq_1_decoded_isEbreak; slots_3_decoded_isMret <= io_enq_1_decoded_isMret; slots_3_decoded_isSret <= io_enq_1_decoded_isSret; slots_3_decoded_isSfenceVma <= io_enq_1_decoded_isSfenceVma; slots_3_decoded_isXret <= io_enq_1_decoded_isXret; slots_3_decoded_isWfi <= io_enq_1_decoded_isWfi; slots_3_decoded_isAmo <= io_enq_1_decoded_isAmo; slots_3_decoded_amoOp <= io_enq_1_decoded_amoOp; slots_3_decoded_writesRd <= io_enq_1_decoded_writesRd; slots_3_decoded_illegal <= io_enq_1_decoded_illegal; slots_3_decoded_fetchException <= io_enq_1_decoded_fetchException; slots_3_decoded_fetchExceptionCause <= io_enq_1_decoded_fetchExceptionCause; slots_3_decoded_fetchExceptionTval <= io_enq_1_decoded_fetchExceptionTval; slots_3_prs1 <= io_enq_1_prs1; slots_3_prs2 <= io_enq_1_prs2; slots_3_prd <= io_enq_1_prd; slots_3_robIdx <= io_enq_1_robIdx; end else if (_GEN_5) begin slots_3_decoded_pc <= io_enq_0_decoded_pc; slots_3_decoded_inst <= io_enq_0_decoded_inst; slots_3_decoded_rs1 <= io_enq_0_decoded_rs1; slots_3_decoded_rs2 <= io_enq_0_decoded_rs2; slots_3_decoded_funct3 <= io_enq_0_decoded_funct3; slots_3_decoded_immI <= io_enq_0_decoded_immI; slots_3_decoded_immS <= io_enq_0_decoded_immS; slots_3_decoded_immB <= io_enq_0_decoded_immB; slots_3_decoded_immU <= io_enq_0_decoded_immU; slots_3_decoded_immJ <= io_enq_0_decoded_immJ; slots_3_decoded_aluFn <= io_enq_0_decoded_aluFn; slots_3_decoded_memWidth <= io_enq_0_decoded_memWidth; slots_3_decoded_memSigned <= io_enq_0_decoded_memSigned; slots_3_decoded_isLoad <= io_enq_0_decoded_isLoad; slots_3_decoded_isStore <= io_enq_0_decoded_isStore; slots_3_decoded_isBranch <= io_enq_0_decoded_isBranch; slots_3_decoded_isJal <= io_enq_0_decoded_isJal; slots_3_decoded_isJalr <= io_enq_0_decoded_isJalr; slots_3_decoded_isLui <= io_enq_0_decoded_isLui; slots_3_decoded_isAuipc <= io_enq_0_decoded_isAuipc; slots_3_decoded_isOpImm <= io_enq_0_decoded_isOpImm; slots_3_decoded_isWord <= io_enq_0_decoded_isWord; slots_3_decoded_isSystem <= io_enq_0_decoded_isSystem; slots_3_decoded_isFenceI <= io_enq_0_decoded_isFenceI; slots_3_decoded_isEcall <= io_enq_0_decoded_isEcall; slots_3_decoded_isEbreak <= io_enq_0_decoded_isEbreak; slots_3_decoded_isMret <= io_enq_0_decoded_isMret; slots_3_decoded_isSret <= io_enq_0_decoded_isSret; slots_3_decoded_isSfenceVma <= io_enq_0_decoded_isSfenceVma; slots_3_decoded_isXret <= io_enq_0_decoded_isXret; slots_3_decoded_isWfi <= io_enq_0_decoded_isWfi; slots_3_decoded_isAmo <= io_enq_0_decoded_isAmo; slots_3_decoded_amoOp <= io_enq_0_decoded_amoOp; slots_3_decoded_writesRd <= io_enq_0_decoded_writesRd; slots_3_decoded_illegal <= io_enq_0_decoded_illegal; slots_3_decoded_fetchException <= io_enq_0_decoded_fetchException; slots_3_decoded_fetchExceptionCause <= io_enq_0_decoded_fetchExceptionCause; slots_3_decoded_fetchExceptionTval <= io_enq_0_decoded_fetchExceptionTval; slots_3_prs1 <= io_enq_0_prs1; slots_3_prs2 <= io_enq_0_prs2; slots_3_prd <= io_enq_0_prd; slots_3_robIdx <= io_enq_0_robIdx; end slots_3_src1Ready <= _GEN_6 ? io_enq_1_src1Ready : _GEN_5 ? io_enq_0_src1Ready : valid_3 & (io_wakeup_1_valid & _src1Wake_T_14 | io_wakeup_0_valid & _src1Wake_T_12) | slots_3_src1Ready; slots_3_src2Ready <= _GEN_6 ? io_enq_1_src2Ready : _GEN_5 ? io_enq_0_src2Ready : valid_3 & (io_wakeup_1_valid & _src2Wake_T_14 | io_wakeup_0_valid & _src2Wake_T_12) | slots_3_src2Ready; if (_GEN_8) begin slots_4_decoded_pc <= io_enq_1_decoded_pc; slots_4_decoded_inst <= io_enq_1_decoded_inst; slots_4_decoded_rs1 <= io_enq_1_decoded_rs1; slots_4_decoded_rs2 <= io_enq_1_decoded_rs2; slots_4_decoded_funct3 <= io_enq_1_decoded_funct3; slots_4_decoded_immI <= io_enq_1_decoded_immI; slots_4_decoded_immS <= io_enq_1_decoded_immS; slots_4_decoded_immB <= io_enq_1_decoded_immB; slots_4_decoded_immU <= io_enq_1_decoded_immU; slots_4_decoded_immJ <= io_enq_1_decoded_immJ; slots_4_decoded_aluFn <= io_enq_1_decoded_aluFn; slots_4_decoded_memWidth <= io_enq_1_decoded_memWidth; slots_4_decoded_memSigned <= io_enq_1_decoded_memSigned; slots_4_decoded_isLoad <= io_enq_1_decoded_isLoad; slots_4_decoded_isStore <= io_enq_1_decoded_isStore; slots_4_decoded_isBranch <= io_enq_1_decoded_isBranch; slots_4_decoded_isJal <= io_enq_1_decoded_isJal; slots_4_decoded_isJalr <= io_enq_1_decoded_isJalr; slots_4_decoded_isLui <= io_enq_1_decoded_isLui; slots_4_decoded_isAuipc <= io_enq_1_decoded_isAuipc; slots_4_decoded_isOpImm <= io_enq_1_decoded_isOpImm; slots_4_decoded_isWord <= io_enq_1_decoded_isWord; slots_4_decoded_isSystem <= io_enq_1_decoded_isSystem; slots_4_decoded_isFenceI <= io_enq_1_decoded_isFenceI; slots_4_decoded_isEcall <= io_enq_1_decoded_isEcall; slots_4_decoded_isEbreak <= io_enq_1_decoded_isEbreak; slots_4_decoded_isMret <= io_enq_1_decoded_isMret; slots_4_decoded_isSret <= io_enq_1_decoded_isSret; slots_4_decoded_isSfenceVma <= io_enq_1_decoded_isSfenceVma; slots_4_decoded_isXret <= io_enq_1_decoded_isXret; slots_4_decoded_isWfi <= io_enq_1_decoded_isWfi; slots_4_decoded_isAmo <= io_enq_1_decoded_isAmo; slots_4_decoded_amoOp <= io_enq_1_decoded_amoOp; slots_4_decoded_writesRd <= io_enq_1_decoded_writesRd; slots_4_decoded_illegal <= io_enq_1_decoded_illegal; slots_4_decoded_fetchException <= io_enq_1_decoded_fetchException; slots_4_decoded_fetchExceptionCause <= io_enq_1_decoded_fetchExceptionCause; slots_4_decoded_fetchExceptionTval <= io_enq_1_decoded_fetchExceptionTval; slots_4_prs1 <= io_enq_1_prs1; slots_4_prs2 <= io_enq_1_prs2; slots_4_prd <= io_enq_1_prd; slots_4_robIdx <= io_enq_1_robIdx; end else if (_GEN_7) begin slots_4_decoded_pc <= io_enq_0_decoded_pc; slots_4_decoded_inst <= io_enq_0_decoded_inst; slots_4_decoded_rs1 <= io_enq_0_decoded_rs1; slots_4_decoded_rs2 <= io_enq_0_decoded_rs2; slots_4_decoded_funct3 <= io_enq_0_decoded_funct3; slots_4_decoded_immI <= io_enq_0_decoded_immI; slots_4_decoded_immS <= io_enq_0_decoded_immS; slots_4_decoded_immB <= io_enq_0_decoded_immB; slots_4_decoded_immU <= io_enq_0_decoded_immU; slots_4_decoded_immJ <= io_enq_0_decoded_immJ; slots_4_decoded_aluFn <= io_enq_0_decoded_aluFn; slots_4_decoded_memWidth <= io_enq_0_decoded_memWidth; slots_4_decoded_memSigned <= io_enq_0_decoded_memSigned; slots_4_decoded_isLoad <= io_enq_0_decoded_isLoad; slots_4_decoded_isStore <= io_enq_0_decoded_isStore; slots_4_decoded_isBranch <= io_enq_0_decoded_isBranch; slots_4_decoded_isJal <= io_enq_0_decoded_isJal; slots_4_decoded_isJalr <= io_enq_0_decoded_isJalr; slots_4_decoded_isLui <= io_enq_0_decoded_isLui; slots_4_decoded_isAuipc <= io_enq_0_decoded_isAuipc; slots_4_decoded_isOpImm <= io_enq_0_decoded_isOpImm; slots_4_decoded_isWord <= io_enq_0_decoded_isWord; slots_4_decoded_isSystem <= io_enq_0_decoded_isSystem; slots_4_decoded_isFenceI <= io_enq_0_decoded_isFenceI; slots_4_decoded_isEcall <= io_enq_0_decoded_isEcall; slots_4_decoded_isEbreak <= io_enq_0_decoded_isEbreak; slots_4_decoded_isMret <= io_enq_0_decoded_isMret; slots_4_decoded_isSret <= io_enq_0_decoded_isSret; slots_4_decoded_isSfenceVma <= io_enq_0_decoded_isSfenceVma; slots_4_decoded_isXret <= io_enq_0_decoded_isXret; slots_4_decoded_isWfi <= io_enq_0_decoded_isWfi; slots_4_decoded_isAmo <= io_enq_0_decoded_isAmo; slots_4_decoded_amoOp <= io_enq_0_decoded_amoOp; slots_4_decoded_writesRd <= io_enq_0_decoded_writesRd; slots_4_decoded_illegal <= io_enq_0_decoded_illegal; slots_4_decoded_fetchException <= io_enq_0_decoded_fetchException; slots_4_decoded_fetchExceptionCause <= io_enq_0_decoded_fetchExceptionCause; slots_4_decoded_fetchExceptionTval <= io_enq_0_decoded_fetchExceptionTval; slots_4_prs1 <= io_enq_0_prs1; slots_4_prs2 <= io_enq_0_prs2; slots_4_prd <= io_enq_0_prd; slots_4_robIdx <= io_enq_0_robIdx; end slots_4_src1Ready <= _GEN_8 ? io_enq_1_src1Ready : _GEN_7 ? io_enq_0_src1Ready : valid_4 & (io_wakeup_1_valid & _src1Wake_T_18 | io_wakeup_0_valid & _src1Wake_T_16) | slots_4_src1Ready; slots_4_src2Ready <= _GEN_8 ? io_enq_1_src2Ready : _GEN_7 ? io_enq_0_src2Ready : valid_4 & (io_wakeup_1_valid & _src2Wake_T_18 | io_wakeup_0_valid & _src2Wake_T_16) | slots_4_src2Ready; if (_GEN_10) begin slots_5_decoded_pc <= io_enq_1_decoded_pc; slots_5_decoded_inst <= io_enq_1_decoded_inst; slots_5_decoded_rs1 <= io_enq_1_decoded_rs1; slots_5_decoded_rs2 <= io_enq_1_decoded_rs2; slots_5_decoded_funct3 <= io_enq_1_decoded_funct3; slots_5_decoded_immI <= io_enq_1_decoded_immI; slots_5_decoded_immS <= io_enq_1_decoded_immS; slots_5_decoded_immB <= io_enq_1_decoded_immB; slots_5_decoded_immU <= io_enq_1_decoded_immU; slots_5_decoded_immJ <= io_enq_1_decoded_immJ; slots_5_decoded_aluFn <= io_enq_1_decoded_aluFn; slots_5_decoded_memWidth <= io_enq_1_decoded_memWidth; slots_5_decoded_memSigned <= io_enq_1_decoded_memSigned; slots_5_decoded_isLoad <= io_enq_1_decoded_isLoad; slots_5_decoded_isStore <= io_enq_1_decoded_isStore; slots_5_decoded_isBranch <= io_enq_1_decoded_isBranch; slots_5_decoded_isJal <= io_enq_1_decoded_isJal; slots_5_decoded_isJalr <= io_enq_1_decoded_isJalr; slots_5_decoded_isLui <= io_enq_1_decoded_isLui; slots_5_decoded_isAuipc <= io_enq_1_decoded_isAuipc; slots_5_decoded_isOpImm <= io_enq_1_decoded_isOpImm; slots_5_decoded_isWord <= io_enq_1_decoded_isWord; slots_5_decoded_isSystem <= io_enq_1_decoded_isSystem; slots_5_decoded_isFenceI <= io_enq_1_decoded_isFenceI; slots_5_decoded_isEcall <= io_enq_1_decoded_isEcall; slots_5_decoded_isEbreak <= io_enq_1_decoded_isEbreak; slots_5_decoded_isMret <= io_enq_1_decoded_isMret; slots_5_decoded_isSret <= io_enq_1_decoded_isSret; slots_5_decoded_isSfenceVma <= io_enq_1_decoded_isSfenceVma; slots_5_decoded_isXret <= io_enq_1_decoded_isXret; slots_5_decoded_isWfi <= io_enq_1_decoded_isWfi; slots_5_decoded_isAmo <= io_enq_1_decoded_isAmo; slots_5_decoded_amoOp <= io_enq_1_decoded_amoOp; slots_5_decoded_writesRd <= io_enq_1_decoded_writesRd; slots_5_decoded_illegal <= io_enq_1_decoded_illegal; slots_5_decoded_fetchException <= io_enq_1_decoded_fetchException; slots_5_decoded_fetchExceptionCause <= io_enq_1_decoded_fetchExceptionCause; slots_5_decoded_fetchExceptionTval <= io_enq_1_decoded_fetchExceptionTval; slots_5_prs1 <= io_enq_1_prs1; slots_5_prs2 <= io_enq_1_prs2; slots_5_prd <= io_enq_1_prd; slots_5_robIdx <= io_enq_1_robIdx; end else if (_GEN_9) begin slots_5_decoded_pc <= io_enq_0_decoded_pc; slots_5_decoded_inst <= io_enq_0_decoded_inst; slots_5_decoded_rs1 <= io_enq_0_decoded_rs1; slots_5_decoded_rs2 <= io_enq_0_decoded_rs2; slots_5_decoded_funct3 <= io_enq_0_decoded_funct3; slots_5_decoded_immI <= io_enq_0_decoded_immI; slots_5_decoded_immS <= io_enq_0_decoded_immS; slots_5_decoded_immB <= io_enq_0_decoded_immB; slots_5_decoded_immU <= io_enq_0_decoded_immU; slots_5_decoded_immJ <= io_enq_0_decoded_immJ; slots_5_decoded_aluFn <= io_enq_0_decoded_aluFn; slots_5_decoded_memWidth <= io_enq_0_decoded_memWidth; slots_5_decoded_memSigned <= io_enq_0_decoded_memSigned; slots_5_decoded_isLoad <= io_enq_0_decoded_isLoad; slots_5_decoded_isStore <= io_enq_0_decoded_isStore; slots_5_decoded_isBranch <= io_enq_0_decoded_isBranch; slots_5_decoded_isJal <= io_enq_0_decoded_isJal; slots_5_decoded_isJalr <= io_enq_0_decoded_isJalr; slots_5_decoded_isLui <= io_enq_0_decoded_isLui; slots_5_decoded_isAuipc <= io_enq_0_decoded_isAuipc; slots_5_decoded_isOpImm <= io_enq_0_decoded_isOpImm; slots_5_decoded_isWord <= io_enq_0_decoded_isWord; slots_5_decoded_isSystem <= io_enq_0_decoded_isSystem; slots_5_decoded_isFenceI <= io_enq_0_decoded_isFenceI; slots_5_decoded_isEcall <= io_enq_0_decoded_isEcall; slots_5_decoded_isEbreak <= io_enq_0_decoded_isEbreak; slots_5_decoded_isMret <= io_enq_0_decoded_isMret; slots_5_decoded_isSret <= io_enq_0_decoded_isSret; slots_5_decoded_isSfenceVma <= io_enq_0_decoded_isSfenceVma; slots_5_decoded_isXret <= io_enq_0_decoded_isXret; slots_5_decoded_isWfi <= io_enq_0_decoded_isWfi; slots_5_decoded_isAmo <= io_enq_0_decoded_isAmo; slots_5_decoded_amoOp <= io_enq_0_decoded_amoOp; slots_5_decoded_writesRd <= io_enq_0_decoded_writesRd; slots_5_decoded_illegal <= io_enq_0_decoded_illegal; slots_5_decoded_fetchException <= io_enq_0_decoded_fetchException; slots_5_decoded_fetchExceptionCause <= io_enq_0_decoded_fetchExceptionCause; slots_5_decoded_fetchExceptionTval <= io_enq_0_decoded_fetchExceptionTval; slots_5_prs1 <= io_enq_0_prs1; slots_5_prs2 <= io_enq_0_prs2; slots_5_prd <= io_enq_0_prd; slots_5_robIdx <= io_enq_0_robIdx; end slots_5_src1Ready <= _GEN_10 ? io_enq_1_src1Ready : _GEN_9 ? io_enq_0_src1Ready : valid_5 & (io_wakeup_1_valid & _src1Wake_T_22 | io_wakeup_0_valid & _src1Wake_T_20) | slots_5_src1Ready; slots_5_src2Ready <= _GEN_10 ? io_enq_1_src2Ready : _GEN_9 ? io_enq_0_src2Ready : valid_5 & (io_wakeup_1_valid & _src2Wake_T_22 | io_wakeup_0_valid & _src2Wake_T_20) | slots_5_src2Ready; if (_GEN_12) begin slots_6_decoded_pc <= io_enq_1_decoded_pc; slots_6_decoded_inst <= io_enq_1_decoded_inst; slots_6_decoded_rs1 <= io_enq_1_decoded_rs1; slots_6_decoded_rs2 <= io_enq_1_decoded_rs2; slots_6_decoded_funct3 <= io_enq_1_decoded_funct3; slots_6_decoded_immI <= io_enq_1_decoded_immI; slots_6_decoded_immS <= io_enq_1_decoded_immS; slots_6_decoded_immB <= io_enq_1_decoded_immB; slots_6_decoded_immU <= io_enq_1_decoded_immU; slots_6_decoded_immJ <= io_enq_1_decoded_immJ; slots_6_decoded_aluFn <= io_enq_1_decoded_aluFn; slots_6_decoded_memWidth <= io_enq_1_decoded_memWidth; slots_6_decoded_memSigned <= io_enq_1_decoded_memSigned; slots_6_decoded_isLoad <= io_enq_1_decoded_isLoad; slots_6_decoded_isStore <= io_enq_1_decoded_isStore; slots_6_decoded_isBranch <= io_enq_1_decoded_isBranch; slots_6_decoded_isJal <= io_enq_1_decoded_isJal; slots_6_decoded_isJalr <= io_enq_1_decoded_isJalr; slots_6_decoded_isLui <= io_enq_1_decoded_isLui; slots_6_decoded_isAuipc <= io_enq_1_decoded_isAuipc; slots_6_decoded_isOpImm <= io_enq_1_decoded_isOpImm; slots_6_decoded_isWord <= io_enq_1_decoded_isWord; slots_6_decoded_isSystem <= io_enq_1_decoded_isSystem; slots_6_decoded_isFenceI <= io_enq_1_decoded_isFenceI; slots_6_decoded_isEcall <= io_enq_1_decoded_isEcall; slots_6_decoded_isEbreak <= io_enq_1_decoded_isEbreak; slots_6_decoded_isMret <= io_enq_1_decoded_isMret; slots_6_decoded_isSret <= io_enq_1_decoded_isSret; slots_6_decoded_isSfenceVma <= io_enq_1_decoded_isSfenceVma; slots_6_decoded_isXret <= io_enq_1_decoded_isXret; slots_6_decoded_isWfi <= io_enq_1_decoded_isWfi; slots_6_decoded_isAmo <= io_enq_1_decoded_isAmo; slots_6_decoded_amoOp <= io_enq_1_decoded_amoOp; slots_6_decoded_writesRd <= io_enq_1_decoded_writesRd; slots_6_decoded_illegal <= io_enq_1_decoded_illegal; slots_6_decoded_fetchException <= io_enq_1_decoded_fetchException; slots_6_decoded_fetchExceptionCause <= io_enq_1_decoded_fetchExceptionCause; slots_6_decoded_fetchExceptionTval <= io_enq_1_decoded_fetchExceptionTval; slots_6_prs1 <= io_enq_1_prs1; slots_6_prs2 <= io_enq_1_prs2; slots_6_prd <= io_enq_1_prd; slots_6_robIdx <= io_enq_1_robIdx; end else if (_GEN_11) begin slots_6_decoded_pc <= io_enq_0_decoded_pc; slots_6_decoded_inst <= io_enq_0_decoded_inst; slots_6_decoded_rs1 <= io_enq_0_decoded_rs1; slots_6_decoded_rs2 <= io_enq_0_decoded_rs2; slots_6_decoded_funct3 <= io_enq_0_decoded_funct3; slots_6_decoded_immI <= io_enq_0_decoded_immI; slots_6_decoded_immS <= io_enq_0_decoded_immS; slots_6_decoded_immB <= io_enq_0_decoded_immB; slots_6_decoded_immU <= io_enq_0_decoded_immU; slots_6_decoded_immJ <= io_enq_0_decoded_immJ; slots_6_decoded_aluFn <= io_enq_0_decoded_aluFn; slots_6_decoded_memWidth <= io_enq_0_decoded_memWidth; slots_6_decoded_memSigned <= io_enq_0_decoded_memSigned; slots_6_decoded_isLoad <= io_enq_0_decoded_isLoad; slots_6_decoded_isStore <= io_enq_0_decoded_isStore; slots_6_decoded_isBranch <= io_enq_0_decoded_isBranch; slots_6_decoded_isJal <= io_enq_0_decoded_isJal; slots_6_decoded_isJalr <= io_enq_0_decoded_isJalr; slots_6_decoded_isLui <= io_enq_0_decoded_isLui; slots_6_decoded_isAuipc <= io_enq_0_decoded_isAuipc; slots_6_decoded_isOpImm <= io_enq_0_decoded_isOpImm; slots_6_decoded_isWord <= io_enq_0_decoded_isWord; slots_6_decoded_isSystem <= io_enq_0_decoded_isSystem; slots_6_decoded_isFenceI <= io_enq_0_decoded_isFenceI; slots_6_decoded_isEcall <= io_enq_0_decoded_isEcall; slots_6_decoded_isEbreak <= io_enq_0_decoded_isEbreak; slots_6_decoded_isMret <= io_enq_0_decoded_isMret; slots_6_decoded_isSret <= io_enq_0_decoded_isSret; slots_6_decoded_isSfenceVma <= io_enq_0_decoded_isSfenceVma; slots_6_decoded_isXret <= io_enq_0_decoded_isXret; slots_6_decoded_isWfi <= io_enq_0_decoded_isWfi; slots_6_decoded_isAmo <= io_enq_0_decoded_isAmo; slots_6_decoded_amoOp <= io_enq_0_decoded_amoOp; slots_6_decoded_writesRd <= io_enq_0_decoded_writesRd; slots_6_decoded_illegal <= io_enq_0_decoded_illegal; slots_6_decoded_fetchException <= io_enq_0_decoded_fetchException; slots_6_decoded_fetchExceptionCause <= io_enq_0_decoded_fetchExceptionCause; slots_6_decoded_fetchExceptionTval <= io_enq_0_decoded_fetchExceptionTval; slots_6_prs1 <= io_enq_0_prs1; slots_6_prs2 <= io_enq_0_prs2; slots_6_prd <= io_enq_0_prd; slots_6_robIdx <= io_enq_0_robIdx; end slots_6_src1Ready <= _GEN_12 ? io_enq_1_src1Ready : _GEN_11 ? io_enq_0_src1Ready : valid_6 & (io_wakeup_1_valid & _src1Wake_T_26 | io_wakeup_0_valid & _src1Wake_T_24) | slots_6_src1Ready; slots_6_src2Ready <= _GEN_12 ? io_enq_1_src2Ready : _GEN_11 ? io_enq_0_src2Ready : valid_6 & (io_wakeup_1_valid & _src2Wake_T_26 | io_wakeup_0_valid & _src2Wake_T_24) | slots_6_src2Ready; if (_GEN_14) begin slots_7_decoded_pc <= io_enq_1_decoded_pc; slots_7_decoded_inst <= io_enq_1_decoded_inst; slots_7_decoded_rs1 <= io_enq_1_decoded_rs1; slots_7_decoded_rs2 <= io_enq_1_decoded_rs2; slots_7_decoded_funct3 <= io_enq_1_decoded_funct3; slots_7_decoded_immI <= io_enq_1_decoded_immI; slots_7_decoded_immS <= io_enq_1_decoded_immS; slots_7_decoded_immB <= io_enq_1_decoded_immB; slots_7_decoded_immU <= io_enq_1_decoded_immU; slots_7_decoded_immJ <= io_enq_1_decoded_immJ; slots_7_decoded_aluFn <= io_enq_1_decoded_aluFn; slots_7_decoded_memWidth <= io_enq_1_decoded_memWidth; slots_7_decoded_memSigned <= io_enq_1_decoded_memSigned; slots_7_decoded_isLoad <= io_enq_1_decoded_isLoad; slots_7_decoded_isStore <= io_enq_1_decoded_isStore; slots_7_decoded_isBranch <= io_enq_1_decoded_isBranch; slots_7_decoded_isJal <= io_enq_1_decoded_isJal; slots_7_decoded_isJalr <= io_enq_1_decoded_isJalr; slots_7_decoded_isLui <= io_enq_1_decoded_isLui; slots_7_decoded_isAuipc <= io_enq_1_decoded_isAuipc; slots_7_decoded_isOpImm <= io_enq_1_decoded_isOpImm; slots_7_decoded_isWord <= io_enq_1_decoded_isWord; slots_7_decoded_isSystem <= io_enq_1_decoded_isSystem; slots_7_decoded_isFenceI <= io_enq_1_decoded_isFenceI; slots_7_decoded_isEcall <= io_enq_1_decoded_isEcall; slots_7_decoded_isEbreak <= io_enq_1_decoded_isEbreak; slots_7_decoded_isMret <= io_enq_1_decoded_isMret; slots_7_decoded_isSret <= io_enq_1_decoded_isSret; slots_7_decoded_isSfenceVma <= io_enq_1_decoded_isSfenceVma; slots_7_decoded_isXret <= io_enq_1_decoded_isXret; slots_7_decoded_isWfi <= io_enq_1_decoded_isWfi; slots_7_decoded_isAmo <= io_enq_1_decoded_isAmo; slots_7_decoded_amoOp <= io_enq_1_decoded_amoOp; slots_7_decoded_writesRd <= io_enq_1_decoded_writesRd; slots_7_decoded_illegal <= io_enq_1_decoded_illegal; slots_7_decoded_fetchException <= io_enq_1_decoded_fetchException; slots_7_decoded_fetchExceptionCause <= io_enq_1_decoded_fetchExceptionCause; slots_7_decoded_fetchExceptionTval <= io_enq_1_decoded_fetchExceptionTval; slots_7_prs1 <= io_enq_1_prs1; slots_7_prs2 <= io_enq_1_prs2; slots_7_prd <= io_enq_1_prd; slots_7_robIdx <= io_enq_1_robIdx; end else if (_GEN_13) begin slots_7_decoded_pc <= io_enq_0_decoded_pc; slots_7_decoded_inst <= io_enq_0_decoded_inst; slots_7_decoded_rs1 <= io_enq_0_decoded_rs1; slots_7_decoded_rs2 <= io_enq_0_decoded_rs2; slots_7_decoded_funct3 <= io_enq_0_decoded_funct3; slots_7_decoded_immI <= io_enq_0_decoded_immI; slots_7_decoded_immS <= io_enq_0_decoded_immS; slots_7_decoded_immB <= io_enq_0_decoded_immB; slots_7_decoded_immU <= io_enq_0_decoded_immU; slots_7_decoded_immJ <= io_enq_0_decoded_immJ; slots_7_decoded_aluFn <= io_enq_0_decoded_aluFn; slots_7_decoded_memWidth <= io_enq_0_decoded_memWidth; slots_7_decoded_memSigned <= io_enq_0_decoded_memSigned; slots_7_decoded_isLoad <= io_enq_0_decoded_isLoad; slots_7_decoded_isStore <= io_enq_0_decoded_isStore; slots_7_decoded_isBranch <= io_enq_0_decoded_isBranch; slots_7_decoded_isJal <= io_enq_0_decoded_isJal; slots_7_decoded_isJalr <= io_enq_0_decoded_isJalr; slots_7_decoded_isLui <= io_enq_0_decoded_isLui; slots_7_decoded_isAuipc <= io_enq_0_decoded_isAuipc; slots_7_decoded_isOpImm <= io_enq_0_decoded_isOpImm; slots_7_decoded_isWord <= io_enq_0_decoded_isWord; slots_7_decoded_isSystem <= io_enq_0_decoded_isSystem; slots_7_decoded_isFenceI <= io_enq_0_decoded_isFenceI; slots_7_decoded_isEcall <= io_enq_0_decoded_isEcall; slots_7_decoded_isEbreak <= io_enq_0_decoded_isEbreak; slots_7_decoded_isMret <= io_enq_0_decoded_isMret; slots_7_decoded_isSret <= io_enq_0_decoded_isSret; slots_7_decoded_isSfenceVma <= io_enq_0_decoded_isSfenceVma; slots_7_decoded_isXret <= io_enq_0_decoded_isXret; slots_7_decoded_isWfi <= io_enq_0_decoded_isWfi; slots_7_decoded_isAmo <= io_enq_0_decoded_isAmo; slots_7_decoded_amoOp <= io_enq_0_decoded_amoOp; slots_7_decoded_writesRd <= io_enq_0_decoded_writesRd; slots_7_decoded_illegal <= io_enq_0_decoded_illegal; slots_7_decoded_fetchException <= io_enq_0_decoded_fetchException; slots_7_decoded_fetchExceptionCause <= io_enq_0_decoded_fetchExceptionCause; slots_7_decoded_fetchExceptionTval <= io_enq_0_decoded_fetchExceptionTval; slots_7_prs1 <= io_enq_0_prs1; slots_7_prs2 <= io_enq_0_prs2; slots_7_prd <= io_enq_0_prd; slots_7_robIdx <= io_enq_0_robIdx; end slots_7_src1Ready <= _GEN_14 ? io_enq_1_src1Ready : _GEN_13 ? io_enq_0_src1Ready : valid_7 & (io_wakeup_1_valid & _src1Wake_T_30 | io_wakeup_0_valid & _src1Wake_T_28) | slots_7_src1Ready; slots_7_src2Ready <= _GEN_14 ? io_enq_1_src2Ready : _GEN_13 ? io_enq_0_src2Ready : valid_7 & (io_wakeup_1_valid & _src2Wake_T_30 | io_wakeup_0_valid & _src2Wake_T_28) | slots_7_src2Ready; if (_GEN_16) begin slots_8_decoded_pc <= io_enq_1_decoded_pc; slots_8_decoded_inst <= io_enq_1_decoded_inst; slots_8_decoded_rs1 <= io_enq_1_decoded_rs1; slots_8_decoded_rs2 <= io_enq_1_decoded_rs2; slots_8_decoded_funct3 <= io_enq_1_decoded_funct3; slots_8_decoded_immI <= io_enq_1_decoded_immI; slots_8_decoded_immS <= io_enq_1_decoded_immS; slots_8_decoded_immB <= io_enq_1_decoded_immB; slots_8_decoded_immU <= io_enq_1_decoded_immU; slots_8_decoded_immJ <= io_enq_1_decoded_immJ; slots_8_decoded_aluFn <= io_enq_1_decoded_aluFn; slots_8_decoded_memWidth <= io_enq_1_decoded_memWidth; slots_8_decoded_memSigned <= io_enq_1_decoded_memSigned; slots_8_decoded_isLoad <= io_enq_1_decoded_isLoad; slots_8_decoded_isStore <= io_enq_1_decoded_isStore; slots_8_decoded_isBranch <= io_enq_1_decoded_isBranch; slots_8_decoded_isJal <= io_enq_1_decoded_isJal; slots_8_decoded_isJalr <= io_enq_1_decoded_isJalr; slots_8_decoded_isLui <= io_enq_1_decoded_isLui; slots_8_decoded_isAuipc <= io_enq_1_decoded_isAuipc; slots_8_decoded_isOpImm <= io_enq_1_decoded_isOpImm; slots_8_decoded_isWord <= io_enq_1_decoded_isWord; slots_8_decoded_isSystem <= io_enq_1_decoded_isSystem; slots_8_decoded_isFenceI <= io_enq_1_decoded_isFenceI; slots_8_decoded_isEcall <= io_enq_1_decoded_isEcall; slots_8_decoded_isEbreak <= io_enq_1_decoded_isEbreak; slots_8_decoded_isMret <= io_enq_1_decoded_isMret; slots_8_decoded_isSret <= io_enq_1_decoded_isSret; slots_8_decoded_isSfenceVma <= io_enq_1_decoded_isSfenceVma; slots_8_decoded_isXret <= io_enq_1_decoded_isXret; slots_8_decoded_isWfi <= io_enq_1_decoded_isWfi; slots_8_decoded_isAmo <= io_enq_1_decoded_isAmo; slots_8_decoded_amoOp <= io_enq_1_decoded_amoOp; slots_8_decoded_writesRd <= io_enq_1_decoded_writesRd; slots_8_decoded_illegal <= io_enq_1_decoded_illegal; slots_8_decoded_fetchException <= io_enq_1_decoded_fetchException; slots_8_decoded_fetchExceptionCause <= io_enq_1_decoded_fetchExceptionCause; slots_8_decoded_fetchExceptionTval <= io_enq_1_decoded_fetchExceptionTval; slots_8_prs1 <= io_enq_1_prs1; slots_8_prs2 <= io_enq_1_prs2; slots_8_prd <= io_enq_1_prd; slots_8_robIdx <= io_enq_1_robIdx; end else if (_GEN_15) begin slots_8_decoded_pc <= io_enq_0_decoded_pc; slots_8_decoded_inst <= io_enq_0_decoded_inst; slots_8_decoded_rs1 <= io_enq_0_decoded_rs1; slots_8_decoded_rs2 <= io_enq_0_decoded_rs2; slots_8_decoded_funct3 <= io_enq_0_decoded_funct3; slots_8_decoded_immI <= io_enq_0_decoded_immI; slots_8_decoded_immS <= io_enq_0_decoded_immS; slots_8_decoded_immB <= io_enq_0_decoded_immB; slots_8_decoded_immU <= io_enq_0_decoded_immU; slots_8_decoded_immJ <= io_enq_0_decoded_immJ; slots_8_decoded_aluFn <= io_enq_0_decoded_aluFn; slots_8_decoded_memWidth <= io_enq_0_decoded_memWidth; slots_8_decoded_memSigned <= io_enq_0_decoded_memSigned; slots_8_decoded_isLoad <= io_enq_0_decoded_isLoad; slots_8_decoded_isStore <= io_enq_0_decoded_isStore; slots_8_decoded_isBranch <= io_enq_0_decoded_isBranch; slots_8_decoded_isJal <= io_enq_0_decoded_isJal; slots_8_decoded_isJalr <= io_enq_0_decoded_isJalr; slots_8_decoded_isLui <= io_enq_0_decoded_isLui; slots_8_decoded_isAuipc <= io_enq_0_decoded_isAuipc; slots_8_decoded_isOpImm <= io_enq_0_decoded_isOpImm; slots_8_decoded_isWord <= io_enq_0_decoded_isWord; slots_8_decoded_isSystem <= io_enq_0_decoded_isSystem; slots_8_decoded_isFenceI <= io_enq_0_decoded_isFenceI; slots_8_decoded_isEcall <= io_enq_0_decoded_isEcall; slots_8_decoded_isEbreak <= io_enq_0_decoded_isEbreak; slots_8_decoded_isMret <= io_enq_0_decoded_isMret; slots_8_decoded_isSret <= io_enq_0_decoded_isSret; slots_8_decoded_isSfenceVma <= io_enq_0_decoded_isSfenceVma; slots_8_decoded_isXret <= io_enq_0_decoded_isXret; slots_8_decoded_isWfi <= io_enq_0_decoded_isWfi; slots_8_decoded_isAmo <= io_enq_0_decoded_isAmo; slots_8_decoded_amoOp <= io_enq_0_decoded_amoOp; slots_8_decoded_writesRd <= io_enq_0_decoded_writesRd; slots_8_decoded_illegal <= io_enq_0_decoded_illegal; slots_8_decoded_fetchException <= io_enq_0_decoded_fetchException; slots_8_decoded_fetchExceptionCause <= io_enq_0_decoded_fetchExceptionCause; slots_8_decoded_fetchExceptionTval <= io_enq_0_decoded_fetchExceptionTval; slots_8_prs1 <= io_enq_0_prs1; slots_8_prs2 <= io_enq_0_prs2; slots_8_prd <= io_enq_0_prd; slots_8_robIdx <= io_enq_0_robIdx; end slots_8_src1Ready <= _GEN_16 ? io_enq_1_src1Ready : _GEN_15 ? io_enq_0_src1Ready : valid_8 & (io_wakeup_1_valid & _src1Wake_T_34 | io_wakeup_0_valid & _src1Wake_T_32) | slots_8_src1Ready; slots_8_src2Ready <= _GEN_16 ? io_enq_1_src2Ready : _GEN_15 ? io_enq_0_src2Ready : valid_8 & (io_wakeup_1_valid & _src2Wake_T_34 | io_wakeup_0_valid & _src2Wake_T_32) | slots_8_src2Ready; if (_GEN_18) begin slots_9_decoded_pc <= io_enq_1_decoded_pc; slots_9_decoded_inst <= io_enq_1_decoded_inst; slots_9_decoded_rs1 <= io_enq_1_decoded_rs1; slots_9_decoded_rs2 <= io_enq_1_decoded_rs2; slots_9_decoded_funct3 <= io_enq_1_decoded_funct3; slots_9_decoded_immI <= io_enq_1_decoded_immI; slots_9_decoded_immS <= io_enq_1_decoded_immS; slots_9_decoded_immB <= io_enq_1_decoded_immB; slots_9_decoded_immU <= io_enq_1_decoded_immU; slots_9_decoded_immJ <= io_enq_1_decoded_immJ; slots_9_decoded_aluFn <= io_enq_1_decoded_aluFn; slots_9_decoded_memWidth <= io_enq_1_decoded_memWidth; slots_9_decoded_memSigned <= io_enq_1_decoded_memSigned; slots_9_decoded_isLoad <= io_enq_1_decoded_isLoad; slots_9_decoded_isStore <= io_enq_1_decoded_isStore; slots_9_decoded_isBranch <= io_enq_1_decoded_isBranch; slots_9_decoded_isJal <= io_enq_1_decoded_isJal; slots_9_decoded_isJalr <= io_enq_1_decoded_isJalr; slots_9_decoded_isLui <= io_enq_1_decoded_isLui; slots_9_decoded_isAuipc <= io_enq_1_decoded_isAuipc; slots_9_decoded_isOpImm <= io_enq_1_decoded_isOpImm; slots_9_decoded_isWord <= io_enq_1_decoded_isWord; slots_9_decoded_isSystem <= io_enq_1_decoded_isSystem; slots_9_decoded_isFenceI <= io_enq_1_decoded_isFenceI; slots_9_decoded_isEcall <= io_enq_1_decoded_isEcall; slots_9_decoded_isEbreak <= io_enq_1_decoded_isEbreak; slots_9_decoded_isMret <= io_enq_1_decoded_isMret; slots_9_decoded_isSret <= io_enq_1_decoded_isSret; slots_9_decoded_isSfenceVma <= io_enq_1_decoded_isSfenceVma; slots_9_decoded_isXret <= io_enq_1_decoded_isXret; slots_9_decoded_isWfi <= io_enq_1_decoded_isWfi; slots_9_decoded_isAmo <= io_enq_1_decoded_isAmo; slots_9_decoded_amoOp <= io_enq_1_decoded_amoOp; slots_9_decoded_writesRd <= io_enq_1_decoded_writesRd; slots_9_decoded_illegal <= io_enq_1_decoded_illegal; slots_9_decoded_fetchException <= io_enq_1_decoded_fetchException; slots_9_decoded_fetchExceptionCause <= io_enq_1_decoded_fetchExceptionCause; slots_9_decoded_fetchExceptionTval <= io_enq_1_decoded_fetchExceptionTval; slots_9_prs1 <= io_enq_1_prs1; slots_9_prs2 <= io_enq_1_prs2; slots_9_prd <= io_enq_1_prd; slots_9_robIdx <= io_enq_1_robIdx; end else if (_GEN_17) begin slots_9_decoded_pc <= io_enq_0_decoded_pc; slots_9_decoded_inst <= io_enq_0_decoded_inst; slots_9_decoded_rs1 <= io_enq_0_decoded_rs1; slots_9_decoded_rs2 <= io_enq_0_decoded_rs2; slots_9_decoded_funct3 <= io_enq_0_decoded_funct3; slots_9_decoded_immI <= io_enq_0_decoded_immI; slots_9_decoded_immS <= io_enq_0_decoded_immS; slots_9_decoded_immB <= io_enq_0_decoded_immB; slots_9_decoded_immU <= io_enq_0_decoded_immU; slots_9_decoded_immJ <= io_enq_0_decoded_immJ; slots_9_decoded_aluFn <= io_enq_0_decoded_aluFn; slots_9_decoded_memWidth <= io_enq_0_decoded_memWidth; slots_9_decoded_memSigned <= io_enq_0_decoded_memSigned; slots_9_decoded_isLoad <= io_enq_0_decoded_isLoad; slots_9_decoded_isStore <= io_enq_0_decoded_isStore; slots_9_decoded_isBranch <= io_enq_0_decoded_isBranch; slots_9_decoded_isJal <= io_enq_0_decoded_isJal; slots_9_decoded_isJalr <= io_enq_0_decoded_isJalr; slots_9_decoded_isLui <= io_enq_0_decoded_isLui; slots_9_decoded_isAuipc <= io_enq_0_decoded_isAuipc; slots_9_decoded_isOpImm <= io_enq_0_decoded_isOpImm; slots_9_decoded_isWord <= io_enq_0_decoded_isWord; slots_9_decoded_isSystem <= io_enq_0_decoded_isSystem; slots_9_decoded_isFenceI <= io_enq_0_decoded_isFenceI; slots_9_decoded_isEcall <= io_enq_0_decoded_isEcall; slots_9_decoded_isEbreak <= io_enq_0_decoded_isEbreak; slots_9_decoded_isMret <= io_enq_0_decoded_isMret; slots_9_decoded_isSret <= io_enq_0_decoded_isSret; slots_9_decoded_isSfenceVma <= io_enq_0_decoded_isSfenceVma; slots_9_decoded_isXret <= io_enq_0_decoded_isXret; slots_9_decoded_isWfi <= io_enq_0_decoded_isWfi; slots_9_decoded_isAmo <= io_enq_0_decoded_isAmo; slots_9_decoded_amoOp <= io_enq_0_decoded_amoOp; slots_9_decoded_writesRd <= io_enq_0_decoded_writesRd; slots_9_decoded_illegal <= io_enq_0_decoded_illegal; slots_9_decoded_fetchException <= io_enq_0_decoded_fetchException; slots_9_decoded_fetchExceptionCause <= io_enq_0_decoded_fetchExceptionCause; slots_9_decoded_fetchExceptionTval <= io_enq_0_decoded_fetchExceptionTval; slots_9_prs1 <= io_enq_0_prs1; slots_9_prs2 <= io_enq_0_prs2; slots_9_prd <= io_enq_0_prd; slots_9_robIdx <= io_enq_0_robIdx; end slots_9_src1Ready <= _GEN_18 ? io_enq_1_src1Ready : _GEN_17 ? io_enq_0_src1Ready : valid_9 & (io_wakeup_1_valid & _src1Wake_T_38 | io_wakeup_0_valid & _src1Wake_T_36) | slots_9_src1Ready; slots_9_src2Ready <= _GEN_18 ? io_enq_1_src2Ready : _GEN_17 ? io_enq_0_src2Ready : valid_9 & (io_wakeup_1_valid & _src2Wake_T_38 | io_wakeup_0_valid & _src2Wake_T_36) | slots_9_src2Ready; if (_GEN_20) begin slots_10_decoded_pc <= io_enq_1_decoded_pc; slots_10_decoded_inst <= io_enq_1_decoded_inst; slots_10_decoded_rs1 <= io_enq_1_decoded_rs1; slots_10_decoded_rs2 <= io_enq_1_decoded_rs2; slots_10_decoded_funct3 <= io_enq_1_decoded_funct3; slots_10_decoded_immI <= io_enq_1_decoded_immI; slots_10_decoded_immS <= io_enq_1_decoded_immS; slots_10_decoded_immB <= io_enq_1_decoded_immB; slots_10_decoded_immU <= io_enq_1_decoded_immU; slots_10_decoded_immJ <= io_enq_1_decoded_immJ; slots_10_decoded_aluFn <= io_enq_1_decoded_aluFn; slots_10_decoded_memWidth <= io_enq_1_decoded_memWidth; slots_10_decoded_memSigned <= io_enq_1_decoded_memSigned; slots_10_decoded_isLoad <= io_enq_1_decoded_isLoad; slots_10_decoded_isStore <= io_enq_1_decoded_isStore; slots_10_decoded_isBranch <= io_enq_1_decoded_isBranch; slots_10_decoded_isJal <= io_enq_1_decoded_isJal; slots_10_decoded_isJalr <= io_enq_1_decoded_isJalr; slots_10_decoded_isLui <= io_enq_1_decoded_isLui; slots_10_decoded_isAuipc <= io_enq_1_decoded_isAuipc; slots_10_decoded_isOpImm <= io_enq_1_decoded_isOpImm; slots_10_decoded_isWord <= io_enq_1_decoded_isWord; slots_10_decoded_isSystem <= io_enq_1_decoded_isSystem; slots_10_decoded_isFenceI <= io_enq_1_decoded_isFenceI; slots_10_decoded_isEcall <= io_enq_1_decoded_isEcall; slots_10_decoded_isEbreak <= io_enq_1_decoded_isEbreak; slots_10_decoded_isMret <= io_enq_1_decoded_isMret; slots_10_decoded_isSret <= io_enq_1_decoded_isSret; slots_10_decoded_isSfenceVma <= io_enq_1_decoded_isSfenceVma; slots_10_decoded_isXret <= io_enq_1_decoded_isXret; slots_10_decoded_isWfi <= io_enq_1_decoded_isWfi; slots_10_decoded_isAmo <= io_enq_1_decoded_isAmo; slots_10_decoded_amoOp <= io_enq_1_decoded_amoOp; slots_10_decoded_writesRd <= io_enq_1_decoded_writesRd; slots_10_decoded_illegal <= io_enq_1_decoded_illegal; slots_10_decoded_fetchException <= io_enq_1_decoded_fetchException; slots_10_decoded_fetchExceptionCause <= io_enq_1_decoded_fetchExceptionCause; slots_10_decoded_fetchExceptionTval <= io_enq_1_decoded_fetchExceptionTval; slots_10_prs1 <= io_enq_1_prs1; slots_10_prs2 <= io_enq_1_prs2; slots_10_prd <= io_enq_1_prd; slots_10_robIdx <= io_enq_1_robIdx; end else if (_GEN_19) begin slots_10_decoded_pc <= io_enq_0_decoded_pc; slots_10_decoded_inst <= io_enq_0_decoded_inst; slots_10_decoded_rs1 <= io_enq_0_decoded_rs1; slots_10_decoded_rs2 <= io_enq_0_decoded_rs2; slots_10_decoded_funct3 <= io_enq_0_decoded_funct3; slots_10_decoded_immI <= io_enq_0_decoded_immI; slots_10_decoded_immS <= io_enq_0_decoded_immS; slots_10_decoded_immB <= io_enq_0_decoded_immB; slots_10_decoded_immU <= io_enq_0_decoded_immU; slots_10_decoded_immJ <= io_enq_0_decoded_immJ; slots_10_decoded_aluFn <= io_enq_0_decoded_aluFn; slots_10_decoded_memWidth <= io_enq_0_decoded_memWidth; slots_10_decoded_memSigned <= io_enq_0_decoded_memSigned; slots_10_decoded_isLoad <= io_enq_0_decoded_isLoad; slots_10_decoded_isStore <= io_enq_0_decoded_isStore; slots_10_decoded_isBranch <= io_enq_0_decoded_isBranch; slots_10_decoded_isJal <= io_enq_0_decoded_isJal; slots_10_decoded_isJalr <= io_enq_0_decoded_isJalr; slots_10_decoded_isLui <= io_enq_0_decoded_isLui; slots_10_decoded_isAuipc <= io_enq_0_decoded_isAuipc; slots_10_decoded_isOpImm <= io_enq_0_decoded_isOpImm; slots_10_decoded_isWord <= io_enq_0_decoded_isWord; slots_10_decoded_isSystem <= io_enq_0_decoded_isSystem; slots_10_decoded_isFenceI <= io_enq_0_decoded_isFenceI; slots_10_decoded_isEcall <= io_enq_0_decoded_isEcall; slots_10_decoded_isEbreak <= io_enq_0_decoded_isEbreak; slots_10_decoded_isMret <= io_enq_0_decoded_isMret; slots_10_decoded_isSret <= io_enq_0_decoded_isSret; slots_10_decoded_isSfenceVma <= io_enq_0_decoded_isSfenceVma; slots_10_decoded_isXret <= io_enq_0_decoded_isXret; slots_10_decoded_isWfi <= io_enq_0_decoded_isWfi; slots_10_decoded_isAmo <= io_enq_0_decoded_isAmo; slots_10_decoded_amoOp <= io_enq_0_decoded_amoOp; slots_10_decoded_writesRd <= io_enq_0_decoded_writesRd; slots_10_decoded_illegal <= io_enq_0_decoded_illegal; slots_10_decoded_fetchException <= io_enq_0_decoded_fetchException; slots_10_decoded_fetchExceptionCause <= io_enq_0_decoded_fetchExceptionCause; slots_10_decoded_fetchExceptionTval <= io_enq_0_decoded_fetchExceptionTval; slots_10_prs1 <= io_enq_0_prs1; slots_10_prs2 <= io_enq_0_prs2; slots_10_prd <= io_enq_0_prd; slots_10_robIdx <= io_enq_0_robIdx; end slots_10_src1Ready <= _GEN_20 ? io_enq_1_src1Ready : _GEN_19 ? io_enq_0_src1Ready : valid_10 & (io_wakeup_1_valid & _src1Wake_T_42 | io_wakeup_0_valid & _src1Wake_T_40) | slots_10_src1Ready; slots_10_src2Ready <= _GEN_20 ? io_enq_1_src2Ready : _GEN_19 ? io_enq_0_src2Ready : valid_10 & (io_wakeup_1_valid & _src2Wake_T_42 | io_wakeup_0_valid & _src2Wake_T_40) | slots_10_src2Ready; if (_GEN_22) begin slots_11_decoded_pc <= io_enq_1_decoded_pc; slots_11_decoded_inst <= io_enq_1_decoded_inst; slots_11_decoded_rs1 <= io_enq_1_decoded_rs1; slots_11_decoded_rs2 <= io_enq_1_decoded_rs2; slots_11_decoded_funct3 <= io_enq_1_decoded_funct3; slots_11_decoded_immI <= io_enq_1_decoded_immI; slots_11_decoded_immS <= io_enq_1_decoded_immS; slots_11_decoded_immB <= io_enq_1_decoded_immB; slots_11_decoded_immU <= io_enq_1_decoded_immU; slots_11_decoded_immJ <= io_enq_1_decoded_immJ; slots_11_decoded_aluFn <= io_enq_1_decoded_aluFn; slots_11_decoded_memWidth <= io_enq_1_decoded_memWidth; slots_11_decoded_memSigned <= io_enq_1_decoded_memSigned; slots_11_decoded_isLoad <= io_enq_1_decoded_isLoad; slots_11_decoded_isStore <= io_enq_1_decoded_isStore; slots_11_decoded_isBranch <= io_enq_1_decoded_isBranch; slots_11_decoded_isJal <= io_enq_1_decoded_isJal; slots_11_decoded_isJalr <= io_enq_1_decoded_isJalr; slots_11_decoded_isLui <= io_enq_1_decoded_isLui; slots_11_decoded_isAuipc <= io_enq_1_decoded_isAuipc; slots_11_decoded_isOpImm <= io_enq_1_decoded_isOpImm; slots_11_decoded_isWord <= io_enq_1_decoded_isWord; slots_11_decoded_isSystem <= io_enq_1_decoded_isSystem; slots_11_decoded_isFenceI <= io_enq_1_decoded_isFenceI; slots_11_decoded_isEcall <= io_enq_1_decoded_isEcall; slots_11_decoded_isEbreak <= io_enq_1_decoded_isEbreak; slots_11_decoded_isMret <= io_enq_1_decoded_isMret; slots_11_decoded_isSret <= io_enq_1_decoded_isSret; slots_11_decoded_isSfenceVma <= io_enq_1_decoded_isSfenceVma; slots_11_decoded_isXret <= io_enq_1_decoded_isXret; slots_11_decoded_isWfi <= io_enq_1_decoded_isWfi; slots_11_decoded_isAmo <= io_enq_1_decoded_isAmo; slots_11_decoded_amoOp <= io_enq_1_decoded_amoOp; slots_11_decoded_writesRd <= io_enq_1_decoded_writesRd; slots_11_decoded_illegal <= io_enq_1_decoded_illegal; slots_11_decoded_fetchException <= io_enq_1_decoded_fetchException; slots_11_decoded_fetchExceptionCause <= io_enq_1_decoded_fetchExceptionCause; slots_11_decoded_fetchExceptionTval <= io_enq_1_decoded_fetchExceptionTval; slots_11_prs1 <= io_enq_1_prs1; slots_11_prs2 <= io_enq_1_prs2; slots_11_prd <= io_enq_1_prd; slots_11_robIdx <= io_enq_1_robIdx; end else if (_GEN_21) begin slots_11_decoded_pc <= io_enq_0_decoded_pc; slots_11_decoded_inst <= io_enq_0_decoded_inst; slots_11_decoded_rs1 <= io_enq_0_decoded_rs1; slots_11_decoded_rs2 <= io_enq_0_decoded_rs2; slots_11_decoded_funct3 <= io_enq_0_decoded_funct3; slots_11_decoded_immI <= io_enq_0_decoded_immI; slots_11_decoded_immS <= io_enq_0_decoded_immS; slots_11_decoded_immB <= io_enq_0_decoded_immB; slots_11_decoded_immU <= io_enq_0_decoded_immU; slots_11_decoded_immJ <= io_enq_0_decoded_immJ; slots_11_decoded_aluFn <= io_enq_0_decoded_aluFn; slots_11_decoded_memWidth <= io_enq_0_decoded_memWidth; slots_11_decoded_memSigned <= io_enq_0_decoded_memSigned; slots_11_decoded_isLoad <= io_enq_0_decoded_isLoad; slots_11_decoded_isStore <= io_enq_0_decoded_isStore; slots_11_decoded_isBranch <= io_enq_0_decoded_isBranch; slots_11_decoded_isJal <= io_enq_0_decoded_isJal; slots_11_decoded_isJalr <= io_enq_0_decoded_isJalr; slots_11_decoded_isLui <= io_enq_0_decoded_isLui; slots_11_decoded_isAuipc <= io_enq_0_decoded_isAuipc; slots_11_decoded_isOpImm <= io_enq_0_decoded_isOpImm; slots_11_decoded_isWord <= io_enq_0_decoded_isWord; slots_11_decoded_isSystem <= io_enq_0_decoded_isSystem; slots_11_decoded_isFenceI <= io_enq_0_decoded_isFenceI; slots_11_decoded_isEcall <= io_enq_0_decoded_isEcall; slots_11_decoded_isEbreak <= io_enq_0_decoded_isEbreak; slots_11_decoded_isMret <= io_enq_0_decoded_isMret; slots_11_decoded_isSret <= io_enq_0_decoded_isSret; slots_11_decoded_isSfenceVma <= io_enq_0_decoded_isSfenceVma; slots_11_decoded_isXret <= io_enq_0_decoded_isXret; slots_11_decoded_isWfi <= io_enq_0_decoded_isWfi; slots_11_decoded_isAmo <= io_enq_0_decoded_isAmo; slots_11_decoded_amoOp <= io_enq_0_decoded_amoOp; slots_11_decoded_writesRd <= io_enq_0_decoded_writesRd; slots_11_decoded_illegal <= io_enq_0_decoded_illegal; slots_11_decoded_fetchException <= io_enq_0_decoded_fetchException; slots_11_decoded_fetchExceptionCause <= io_enq_0_decoded_fetchExceptionCause; slots_11_decoded_fetchExceptionTval <= io_enq_0_decoded_fetchExceptionTval; slots_11_prs1 <= io_enq_0_prs1; slots_11_prs2 <= io_enq_0_prs2; slots_11_prd <= io_enq_0_prd; slots_11_robIdx <= io_enq_0_robIdx; end slots_11_src1Ready <= _GEN_22 ? io_enq_1_src1Ready : _GEN_21 ? io_enq_0_src1Ready : valid_11 & (io_wakeup_1_valid & _src1Wake_T_46 | io_wakeup_0_valid & _src1Wake_T_44) | slots_11_src1Ready; slots_11_src2Ready <= _GEN_22 ? io_enq_1_src2Ready : _GEN_21 ? io_enq_0_src2Ready : valid_11 & (io_wakeup_1_valid & _src2Wake_T_46 | io_wakeup_0_valid & _src2Wake_T_44) | slots_11_src2Ready; if (_GEN_24) begin slots_12_decoded_pc <= io_enq_1_decoded_pc; slots_12_decoded_inst <= io_enq_1_decoded_inst; slots_12_decoded_rs1 <= io_enq_1_decoded_rs1; slots_12_decoded_rs2 <= io_enq_1_decoded_rs2; slots_12_decoded_funct3 <= io_enq_1_decoded_funct3; slots_12_decoded_immI <= io_enq_1_decoded_immI; slots_12_decoded_immS <= io_enq_1_decoded_immS; slots_12_decoded_immB <= io_enq_1_decoded_immB; slots_12_decoded_immU <= io_enq_1_decoded_immU; slots_12_decoded_immJ <= io_enq_1_decoded_immJ; slots_12_decoded_aluFn <= io_enq_1_decoded_aluFn; slots_12_decoded_memWidth <= io_enq_1_decoded_memWidth; slots_12_decoded_memSigned <= io_enq_1_decoded_memSigned; slots_12_decoded_isLoad <= io_enq_1_decoded_isLoad; slots_12_decoded_isStore <= io_enq_1_decoded_isStore; slots_12_decoded_isBranch <= io_enq_1_decoded_isBranch; slots_12_decoded_isJal <= io_enq_1_decoded_isJal; slots_12_decoded_isJalr <= io_enq_1_decoded_isJalr; slots_12_decoded_isLui <= io_enq_1_decoded_isLui; slots_12_decoded_isAuipc <= io_enq_1_decoded_isAuipc; slots_12_decoded_isOpImm <= io_enq_1_decoded_isOpImm; slots_12_decoded_isWord <= io_enq_1_decoded_isWord; slots_12_decoded_isSystem <= io_enq_1_decoded_isSystem; slots_12_decoded_isFenceI <= io_enq_1_decoded_isFenceI; slots_12_decoded_isEcall <= io_enq_1_decoded_isEcall; slots_12_decoded_isEbreak <= io_enq_1_decoded_isEbreak; slots_12_decoded_isMret <= io_enq_1_decoded_isMret; slots_12_decoded_isSret <= io_enq_1_decoded_isSret; slots_12_decoded_isSfenceVma <= io_enq_1_decoded_isSfenceVma; slots_12_decoded_isXret <= io_enq_1_decoded_isXret; slots_12_decoded_isWfi <= io_enq_1_decoded_isWfi; slots_12_decoded_isAmo <= io_enq_1_decoded_isAmo; slots_12_decoded_amoOp <= io_enq_1_decoded_amoOp; slots_12_decoded_writesRd <= io_enq_1_decoded_writesRd; slots_12_decoded_illegal <= io_enq_1_decoded_illegal; slots_12_decoded_fetchException <= io_enq_1_decoded_fetchException; slots_12_decoded_fetchExceptionCause <= io_enq_1_decoded_fetchExceptionCause; slots_12_decoded_fetchExceptionTval <= io_enq_1_decoded_fetchExceptionTval; slots_12_prs1 <= io_enq_1_prs1; slots_12_prs2 <= io_enq_1_prs2; slots_12_prd <= io_enq_1_prd; slots_12_robIdx <= io_enq_1_robIdx; end else if (_GEN_23) begin slots_12_decoded_pc <= io_enq_0_decoded_pc; slots_12_decoded_inst <= io_enq_0_decoded_inst; slots_12_decoded_rs1 <= io_enq_0_decoded_rs1; slots_12_decoded_rs2 <= io_enq_0_decoded_rs2; slots_12_decoded_funct3 <= io_enq_0_decoded_funct3; slots_12_decoded_immI <= io_enq_0_decoded_immI; slots_12_decoded_immS <= io_enq_0_decoded_immS; slots_12_decoded_immB <= io_enq_0_decoded_immB; slots_12_decoded_immU <= io_enq_0_decoded_immU; slots_12_decoded_immJ <= io_enq_0_decoded_immJ; slots_12_decoded_aluFn <= io_enq_0_decoded_aluFn; slots_12_decoded_memWidth <= io_enq_0_decoded_memWidth; slots_12_decoded_memSigned <= io_enq_0_decoded_memSigned; slots_12_decoded_isLoad <= io_enq_0_decoded_isLoad; slots_12_decoded_isStore <= io_enq_0_decoded_isStore; slots_12_decoded_isBranch <= io_enq_0_decoded_isBranch; slots_12_decoded_isJal <= io_enq_0_decoded_isJal; slots_12_decoded_isJalr <= io_enq_0_decoded_isJalr; slots_12_decoded_isLui <= io_enq_0_decoded_isLui; slots_12_decoded_isAuipc <= io_enq_0_decoded_isAuipc; slots_12_decoded_isOpImm <= io_enq_0_decoded_isOpImm; slots_12_decoded_isWord <= io_enq_0_decoded_isWord; slots_12_decoded_isSystem <= io_enq_0_decoded_isSystem; slots_12_decoded_isFenceI <= io_enq_0_decoded_isFenceI; slots_12_decoded_isEcall <= io_enq_0_decoded_isEcall; slots_12_decoded_isEbreak <= io_enq_0_decoded_isEbreak; slots_12_decoded_isMret <= io_enq_0_decoded_isMret; slots_12_decoded_isSret <= io_enq_0_decoded_isSret; slots_12_decoded_isSfenceVma <= io_enq_0_decoded_isSfenceVma; slots_12_decoded_isXret <= io_enq_0_decoded_isXret; slots_12_decoded_isWfi <= io_enq_0_decoded_isWfi; slots_12_decoded_isAmo <= io_enq_0_decoded_isAmo; slots_12_decoded_amoOp <= io_enq_0_decoded_amoOp; slots_12_decoded_writesRd <= io_enq_0_decoded_writesRd; slots_12_decoded_illegal <= io_enq_0_decoded_illegal; slots_12_decoded_fetchException <= io_enq_0_decoded_fetchException; slots_12_decoded_fetchExceptionCause <= io_enq_0_decoded_fetchExceptionCause; slots_12_decoded_fetchExceptionTval <= io_enq_0_decoded_fetchExceptionTval; slots_12_prs1 <= io_enq_0_prs1; slots_12_prs2 <= io_enq_0_prs2; slots_12_prd <= io_enq_0_prd; slots_12_robIdx <= io_enq_0_robIdx; end slots_12_src1Ready <= _GEN_24 ? io_enq_1_src1Ready : _GEN_23 ? io_enq_0_src1Ready : valid_12 & (io_wakeup_1_valid & _src1Wake_T_50 | io_wakeup_0_valid & _src1Wake_T_48) | slots_12_src1Ready; slots_12_src2Ready <= _GEN_24 ? io_enq_1_src2Ready : _GEN_23 ? io_enq_0_src2Ready : valid_12 & (io_wakeup_1_valid & _src2Wake_T_50 | io_wakeup_0_valid & _src2Wake_T_48) | slots_12_src2Ready; if (_GEN_26) begin slots_13_decoded_pc <= io_enq_1_decoded_pc; slots_13_decoded_inst <= io_enq_1_decoded_inst; slots_13_decoded_rs1 <= io_enq_1_decoded_rs1; slots_13_decoded_rs2 <= io_enq_1_decoded_rs2; slots_13_decoded_funct3 <= io_enq_1_decoded_funct3; slots_13_decoded_immI <= io_enq_1_decoded_immI; slots_13_decoded_immS <= io_enq_1_decoded_immS; slots_13_decoded_immB <= io_enq_1_decoded_immB; slots_13_decoded_immU <= io_enq_1_decoded_immU; slots_13_decoded_immJ <= io_enq_1_decoded_immJ; slots_13_decoded_aluFn <= io_enq_1_decoded_aluFn; slots_13_decoded_memWidth <= io_enq_1_decoded_memWidth; slots_13_decoded_memSigned <= io_enq_1_decoded_memSigned; slots_13_decoded_isLoad <= io_enq_1_decoded_isLoad; slots_13_decoded_isStore <= io_enq_1_decoded_isStore; slots_13_decoded_isBranch <= io_enq_1_decoded_isBranch; slots_13_decoded_isJal <= io_enq_1_decoded_isJal; slots_13_decoded_isJalr <= io_enq_1_decoded_isJalr; slots_13_decoded_isLui <= io_enq_1_decoded_isLui; slots_13_decoded_isAuipc <= io_enq_1_decoded_isAuipc; slots_13_decoded_isOpImm <= io_enq_1_decoded_isOpImm; slots_13_decoded_isWord <= io_enq_1_decoded_isWord; slots_13_decoded_isSystem <= io_enq_1_decoded_isSystem; slots_13_decoded_isFenceI <= io_enq_1_decoded_isFenceI; slots_13_decoded_isEcall <= io_enq_1_decoded_isEcall; slots_13_decoded_isEbreak <= io_enq_1_decoded_isEbreak; slots_13_decoded_isMret <= io_enq_1_decoded_isMret; slots_13_decoded_isSret <= io_enq_1_decoded_isSret; slots_13_decoded_isSfenceVma <= io_enq_1_decoded_isSfenceVma; slots_13_decoded_isXret <= io_enq_1_decoded_isXret; slots_13_decoded_isWfi <= io_enq_1_decoded_isWfi; slots_13_decoded_isAmo <= io_enq_1_decoded_isAmo; slots_13_decoded_amoOp <= io_enq_1_decoded_amoOp; slots_13_decoded_writesRd <= io_enq_1_decoded_writesRd; slots_13_decoded_illegal <= io_enq_1_decoded_illegal; slots_13_decoded_fetchException <= io_enq_1_decoded_fetchException; slots_13_decoded_fetchExceptionCause <= io_enq_1_decoded_fetchExceptionCause; slots_13_decoded_fetchExceptionTval <= io_enq_1_decoded_fetchExceptionTval; slots_13_prs1 <= io_enq_1_prs1; slots_13_prs2 <= io_enq_1_prs2; slots_13_prd <= io_enq_1_prd; slots_13_robIdx <= io_enq_1_robIdx; end else if (_GEN_25) begin slots_13_decoded_pc <= io_enq_0_decoded_pc; slots_13_decoded_inst <= io_enq_0_decoded_inst; slots_13_decoded_rs1 <= io_enq_0_decoded_rs1; slots_13_decoded_rs2 <= io_enq_0_decoded_rs2; slots_13_decoded_funct3 <= io_enq_0_decoded_funct3; slots_13_decoded_immI <= io_enq_0_decoded_immI; slots_13_decoded_immS <= io_enq_0_decoded_immS; slots_13_decoded_immB <= io_enq_0_decoded_immB; slots_13_decoded_immU <= io_enq_0_decoded_immU; slots_13_decoded_immJ <= io_enq_0_decoded_immJ; slots_13_decoded_aluFn <= io_enq_0_decoded_aluFn; slots_13_decoded_memWidth <= io_enq_0_decoded_memWidth; slots_13_decoded_memSigned <= io_enq_0_decoded_memSigned; slots_13_decoded_isLoad <= io_enq_0_decoded_isLoad; slots_13_decoded_isStore <= io_enq_0_decoded_isStore; slots_13_decoded_isBranch <= io_enq_0_decoded_isBranch; slots_13_decoded_isJal <= io_enq_0_decoded_isJal; slots_13_decoded_isJalr <= io_enq_0_decoded_isJalr; slots_13_decoded_isLui <= io_enq_0_decoded_isLui; slots_13_decoded_isAuipc <= io_enq_0_decoded_isAuipc; slots_13_decoded_isOpImm <= io_enq_0_decoded_isOpImm; slots_13_decoded_isWord <= io_enq_0_decoded_isWord; slots_13_decoded_isSystem <= io_enq_0_decoded_isSystem; slots_13_decoded_isFenceI <= io_enq_0_decoded_isFenceI; slots_13_decoded_isEcall <= io_enq_0_decoded_isEcall; slots_13_decoded_isEbreak <= io_enq_0_decoded_isEbreak; slots_13_decoded_isMret <= io_enq_0_decoded_isMret; slots_13_decoded_isSret <= io_enq_0_decoded_isSret; slots_13_decoded_isSfenceVma <= io_enq_0_decoded_isSfenceVma; slots_13_decoded_isXret <= io_enq_0_decoded_isXret; slots_13_decoded_isWfi <= io_enq_0_decoded_isWfi; slots_13_decoded_isAmo <= io_enq_0_decoded_isAmo; slots_13_decoded_amoOp <= io_enq_0_decoded_amoOp; slots_13_decoded_writesRd <= io_enq_0_decoded_writesRd; slots_13_decoded_illegal <= io_enq_0_decoded_illegal; slots_13_decoded_fetchException <= io_enq_0_decoded_fetchException; slots_13_decoded_fetchExceptionCause <= io_enq_0_decoded_fetchExceptionCause; slots_13_decoded_fetchExceptionTval <= io_enq_0_decoded_fetchExceptionTval; slots_13_prs1 <= io_enq_0_prs1; slots_13_prs2 <= io_enq_0_prs2; slots_13_prd <= io_enq_0_prd; slots_13_robIdx <= io_enq_0_robIdx; end slots_13_src1Ready <= _GEN_26 ? io_enq_1_src1Ready : _GEN_25 ? io_enq_0_src1Ready : valid_13 & (io_wakeup_1_valid & _src1Wake_T_54 | io_wakeup_0_valid & _src1Wake_T_52) | slots_13_src1Ready; slots_13_src2Ready <= _GEN_26 ? io_enq_1_src2Ready : _GEN_25 ? io_enq_0_src2Ready : valid_13 & (io_wakeup_1_valid & _src2Wake_T_54 | io_wakeup_0_valid & _src2Wake_T_52) | slots_13_src2Ready; if (_GEN_28) begin slots_14_decoded_pc <= io_enq_1_decoded_pc; slots_14_decoded_inst <= io_enq_1_decoded_inst; slots_14_decoded_rs1 <= io_enq_1_decoded_rs1; slots_14_decoded_rs2 <= io_enq_1_decoded_rs2; slots_14_decoded_funct3 <= io_enq_1_decoded_funct3; slots_14_decoded_immI <= io_enq_1_decoded_immI; slots_14_decoded_immS <= io_enq_1_decoded_immS; slots_14_decoded_immB <= io_enq_1_decoded_immB; slots_14_decoded_immU <= io_enq_1_decoded_immU; slots_14_decoded_immJ <= io_enq_1_decoded_immJ; slots_14_decoded_aluFn <= io_enq_1_decoded_aluFn; slots_14_decoded_memWidth <= io_enq_1_decoded_memWidth; slots_14_decoded_memSigned <= io_enq_1_decoded_memSigned; slots_14_decoded_isLoad <= io_enq_1_decoded_isLoad; slots_14_decoded_isStore <= io_enq_1_decoded_isStore; slots_14_decoded_isBranch <= io_enq_1_decoded_isBranch; slots_14_decoded_isJal <= io_enq_1_decoded_isJal; slots_14_decoded_isJalr <= io_enq_1_decoded_isJalr; slots_14_decoded_isLui <= io_enq_1_decoded_isLui; slots_14_decoded_isAuipc <= io_enq_1_decoded_isAuipc; slots_14_decoded_isOpImm <= io_enq_1_decoded_isOpImm; slots_14_decoded_isWord <= io_enq_1_decoded_isWord; slots_14_decoded_isSystem <= io_enq_1_decoded_isSystem; slots_14_decoded_isFenceI <= io_enq_1_decoded_isFenceI; slots_14_decoded_isEcall <= io_enq_1_decoded_isEcall; slots_14_decoded_isEbreak <= io_enq_1_decoded_isEbreak; slots_14_decoded_isMret <= io_enq_1_decoded_isMret; slots_14_decoded_isSret <= io_enq_1_decoded_isSret; slots_14_decoded_isSfenceVma <= io_enq_1_decoded_isSfenceVma; slots_14_decoded_isXret <= io_enq_1_decoded_isXret; slots_14_decoded_isWfi <= io_enq_1_decoded_isWfi; slots_14_decoded_isAmo <= io_enq_1_decoded_isAmo; slots_14_decoded_amoOp <= io_enq_1_decoded_amoOp; slots_14_decoded_writesRd <= io_enq_1_decoded_writesRd; slots_14_decoded_illegal <= io_enq_1_decoded_illegal; slots_14_decoded_fetchException <= io_enq_1_decoded_fetchException; slots_14_decoded_fetchExceptionCause <= io_enq_1_decoded_fetchExceptionCause; slots_14_decoded_fetchExceptionTval <= io_enq_1_decoded_fetchExceptionTval; slots_14_prs1 <= io_enq_1_prs1; slots_14_prs2 <= io_enq_1_prs2; slots_14_prd <= io_enq_1_prd; slots_14_robIdx <= io_enq_1_robIdx; end else if (_GEN_27) begin slots_14_decoded_pc <= io_enq_0_decoded_pc; slots_14_decoded_inst <= io_enq_0_decoded_inst; slots_14_decoded_rs1 <= io_enq_0_decoded_rs1; slots_14_decoded_rs2 <= io_enq_0_decoded_rs2; slots_14_decoded_funct3 <= io_enq_0_decoded_funct3; slots_14_decoded_immI <= io_enq_0_decoded_immI; slots_14_decoded_immS <= io_enq_0_decoded_immS; slots_14_decoded_immB <= io_enq_0_decoded_immB; slots_14_decoded_immU <= io_enq_0_decoded_immU; slots_14_decoded_immJ <= io_enq_0_decoded_immJ; slots_14_decoded_aluFn <= io_enq_0_decoded_aluFn; slots_14_decoded_memWidth <= io_enq_0_decoded_memWidth; slots_14_decoded_memSigned <= io_enq_0_decoded_memSigned; slots_14_decoded_isLoad <= io_enq_0_decoded_isLoad; slots_14_decoded_isStore <= io_enq_0_decoded_isStore; slots_14_decoded_isBranch <= io_enq_0_decoded_isBranch; slots_14_decoded_isJal <= io_enq_0_decoded_isJal; slots_14_decoded_isJalr <= io_enq_0_decoded_isJalr; slots_14_decoded_isLui <= io_enq_0_decoded_isLui; slots_14_decoded_isAuipc <= io_enq_0_decoded_isAuipc; slots_14_decoded_isOpImm <= io_enq_0_decoded_isOpImm; slots_14_decoded_isWord <= io_enq_0_decoded_isWord; slots_14_decoded_isSystem <= io_enq_0_decoded_isSystem; slots_14_decoded_isFenceI <= io_enq_0_decoded_isFenceI; slots_14_decoded_isEcall <= io_enq_0_decoded_isEcall; slots_14_decoded_isEbreak <= io_enq_0_decoded_isEbreak; slots_14_decoded_isMret <= io_enq_0_decoded_isMret; slots_14_decoded_isSret <= io_enq_0_decoded_isSret; slots_14_decoded_isSfenceVma <= io_enq_0_decoded_isSfenceVma; slots_14_decoded_isXret <= io_enq_0_decoded_isXret; slots_14_decoded_isWfi <= io_enq_0_decoded_isWfi; slots_14_decoded_isAmo <= io_enq_0_decoded_isAmo; slots_14_decoded_amoOp <= io_enq_0_decoded_amoOp; slots_14_decoded_writesRd <= io_enq_0_decoded_writesRd; slots_14_decoded_illegal <= io_enq_0_decoded_illegal; slots_14_decoded_fetchException <= io_enq_0_decoded_fetchException; slots_14_decoded_fetchExceptionCause <= io_enq_0_decoded_fetchExceptionCause; slots_14_decoded_fetchExceptionTval <= io_enq_0_decoded_fetchExceptionTval; slots_14_prs1 <= io_enq_0_prs1; slots_14_prs2 <= io_enq_0_prs2; slots_14_prd <= io_enq_0_prd; slots_14_robIdx <= io_enq_0_robIdx; end slots_14_src1Ready <= _GEN_28 ? io_enq_1_src1Ready : _GEN_27 ? io_enq_0_src1Ready : valid_14 & (io_wakeup_1_valid & _src1Wake_T_58 | io_wakeup_0_valid & _src1Wake_T_56) | slots_14_src1Ready; slots_14_src2Ready <= _GEN_28 ? io_enq_1_src2Ready : _GEN_27 ? io_enq_0_src2Ready : valid_14 & (io_wakeup_1_valid & _src2Wake_T_58 | io_wakeup_0_valid & _src2Wake_T_56) | slots_14_src2Ready; if (_GEN_30) begin slots_15_decoded_pc <= io_enq_1_decoded_pc; slots_15_decoded_inst <= io_enq_1_decoded_inst; slots_15_decoded_rs1 <= io_enq_1_decoded_rs1; slots_15_decoded_rs2 <= io_enq_1_decoded_rs2; slots_15_decoded_funct3 <= io_enq_1_decoded_funct3; slots_15_decoded_immI <= io_enq_1_decoded_immI; slots_15_decoded_immS <= io_enq_1_decoded_immS; slots_15_decoded_immB <= io_enq_1_decoded_immB; slots_15_decoded_immU <= io_enq_1_decoded_immU; slots_15_decoded_immJ <= io_enq_1_decoded_immJ; slots_15_decoded_aluFn <= io_enq_1_decoded_aluFn; slots_15_decoded_memWidth <= io_enq_1_decoded_memWidth; slots_15_decoded_memSigned <= io_enq_1_decoded_memSigned; slots_15_decoded_isLoad <= io_enq_1_decoded_isLoad; slots_15_decoded_isStore <= io_enq_1_decoded_isStore; slots_15_decoded_isBranch <= io_enq_1_decoded_isBranch; slots_15_decoded_isJal <= io_enq_1_decoded_isJal; slots_15_decoded_isJalr <= io_enq_1_decoded_isJalr; slots_15_decoded_isLui <= io_enq_1_decoded_isLui; slots_15_decoded_isAuipc <= io_enq_1_decoded_isAuipc; slots_15_decoded_isOpImm <= io_enq_1_decoded_isOpImm; slots_15_decoded_isWord <= io_enq_1_decoded_isWord; slots_15_decoded_isSystem <= io_enq_1_decoded_isSystem; slots_15_decoded_isFenceI <= io_enq_1_decoded_isFenceI; slots_15_decoded_isEcall <= io_enq_1_decoded_isEcall; slots_15_decoded_isEbreak <= io_enq_1_decoded_isEbreak; slots_15_decoded_isMret <= io_enq_1_decoded_isMret; slots_15_decoded_isSret <= io_enq_1_decoded_isSret; slots_15_decoded_isSfenceVma <= io_enq_1_decoded_isSfenceVma; slots_15_decoded_isXret <= io_enq_1_decoded_isXret; slots_15_decoded_isWfi <= io_enq_1_decoded_isWfi; slots_15_decoded_isAmo <= io_enq_1_decoded_isAmo; slots_15_decoded_amoOp <= io_enq_1_decoded_amoOp; slots_15_decoded_writesRd <= io_enq_1_decoded_writesRd; slots_15_decoded_illegal <= io_enq_1_decoded_illegal; slots_15_decoded_fetchException <= io_enq_1_decoded_fetchException; slots_15_decoded_fetchExceptionCause <= io_enq_1_decoded_fetchExceptionCause; slots_15_decoded_fetchExceptionTval <= io_enq_1_decoded_fetchExceptionTval; slots_15_prs1 <= io_enq_1_prs1; slots_15_prs2 <= io_enq_1_prs2; slots_15_prd <= io_enq_1_prd; slots_15_robIdx <= io_enq_1_robIdx; end else if (_GEN_29) begin slots_15_decoded_pc <= io_enq_0_decoded_pc; slots_15_decoded_inst <= io_enq_0_decoded_inst; slots_15_decoded_rs1 <= io_enq_0_decoded_rs1; slots_15_decoded_rs2 <= io_enq_0_decoded_rs2; slots_15_decoded_funct3 <= io_enq_0_decoded_funct3; slots_15_decoded_immI <= io_enq_0_decoded_immI; slots_15_decoded_immS <= io_enq_0_decoded_immS; slots_15_decoded_immB <= io_enq_0_decoded_immB; slots_15_decoded_immU <= io_enq_0_decoded_immU; slots_15_decoded_immJ <= io_enq_0_decoded_immJ; slots_15_decoded_aluFn <= io_enq_0_decoded_aluFn; slots_15_decoded_memWidth <= io_enq_0_decoded_memWidth; slots_15_decoded_memSigned <= io_enq_0_decoded_memSigned; slots_15_decoded_isLoad <= io_enq_0_decoded_isLoad; slots_15_decoded_isStore <= io_enq_0_decoded_isStore; slots_15_decoded_isBranch <= io_enq_0_decoded_isBranch; slots_15_decoded_isJal <= io_enq_0_decoded_isJal; slots_15_decoded_isJalr <= io_enq_0_decoded_isJalr; slots_15_decoded_isLui <= io_enq_0_decoded_isLui; slots_15_decoded_isAuipc <= io_enq_0_decoded_isAuipc; slots_15_decoded_isOpImm <= io_enq_0_decoded_isOpImm; slots_15_decoded_isWord <= io_enq_0_decoded_isWord; slots_15_decoded_isSystem <= io_enq_0_decoded_isSystem; slots_15_decoded_isFenceI <= io_enq_0_decoded_isFenceI; slots_15_decoded_isEcall <= io_enq_0_decoded_isEcall; slots_15_decoded_isEbreak <= io_enq_0_decoded_isEbreak; slots_15_decoded_isMret <= io_enq_0_decoded_isMret; slots_15_decoded_isSret <= io_enq_0_decoded_isSret; slots_15_decoded_isSfenceVma <= io_enq_0_decoded_isSfenceVma; slots_15_decoded_isXret <= io_enq_0_decoded_isXret; slots_15_decoded_isWfi <= io_enq_0_decoded_isWfi; slots_15_decoded_isAmo <= io_enq_0_decoded_isAmo; slots_15_decoded_amoOp <= io_enq_0_decoded_amoOp; slots_15_decoded_writesRd <= io_enq_0_decoded_writesRd; slots_15_decoded_illegal <= io_enq_0_decoded_illegal; slots_15_decoded_fetchException <= io_enq_0_decoded_fetchException; slots_15_decoded_fetchExceptionCause <= io_enq_0_decoded_fetchExceptionCause; slots_15_decoded_fetchExceptionTval <= io_enq_0_decoded_fetchExceptionTval; slots_15_prs1 <= io_enq_0_prs1; slots_15_prs2 <= io_enq_0_prs2; slots_15_prd <= io_enq_0_prd; slots_15_robIdx <= io_enq_0_robIdx; end slots_15_src1Ready <= _GEN_30 ? io_enq_1_src1Ready : _GEN_29 ? io_enq_0_src1Ready : valid_15 & (io_wakeup_1_valid & _src1Wake_T_62 | io_wakeup_0_valid & _src1Wake_T_60) | slots_15_src1Ready; slots_15_src2Ready <= _GEN_30 ? io_enq_1_src2Ready : _GEN_29 ? io_enq_0_src2Ready : valid_15 & (io_wakeup_1_valid & _src2Wake_T_62 | io_wakeup_0_valid & _src2Wake_T_60) | slots_15_src2Ready; end end // always @(posedge) assign io_enqReady_0 = |freeMask; assign io_enqReady_1 = |_io_enqReady_1_T_1; assign io_issueValid_0 = |_io_issueValid_1_T; assign io_issueValid_1 = |(_io_issueValid_1_T & _io_issueValid_1_T_1); assign io_issue_0_decoded_pc = (issue0OH[0] ? slots_0_decoded_pc : 64'h0) | (issue0OH[1] ? slots_1_decoded_pc : 64'h0) | (issue0OH[2] ? slots_2_decoded_pc : 64'h0) | (issue0OH[3] ? slots_3_decoded_pc : 64'h0) | (issue0OH[4] ? slots_4_decoded_pc : 64'h0) | (issue0OH[5] ? slots_5_decoded_pc : 64'h0) | (issue0OH[6] ? slots_6_decoded_pc : 64'h0) | (issue0OH[7] ? slots_7_decoded_pc : 64'h0) | (issue0OH[8] ? slots_8_decoded_pc : 64'h0) | (issue0OH[9] ? slots_9_decoded_pc : 64'h0) | (issue0OH[10] ? slots_10_decoded_pc : 64'h0) | (issue0OH[11] ? slots_11_decoded_pc : 64'h0) | (issue0OH[12] ? slots_12_decoded_pc : 64'h0) | (issue0OH[13] ? slots_13_decoded_pc : 64'h0) | (issue0OH[14] ? slots_14_decoded_pc : 64'h0) | (issue0OH[15] ? slots_15_decoded_pc : 64'h0); assign io_issue_0_decoded_inst = (issue0OH[0] ? slots_0_decoded_inst : 32'h0) | (issue0OH[1] ? slots_1_decoded_inst : 32'h0) | (issue0OH[2] ? slots_2_decoded_inst : 32'h0) | (issue0OH[3] ? slots_3_decoded_inst : 32'h0) | (issue0OH[4] ? slots_4_decoded_inst : 32'h0) | (issue0OH[5] ? slots_5_decoded_inst : 32'h0) | (issue0OH[6] ? slots_6_decoded_inst : 32'h0) | (issue0OH[7] ? slots_7_decoded_inst : 32'h0) | (issue0OH[8] ? slots_8_decoded_inst : 32'h0) | (issue0OH[9] ? slots_9_decoded_inst : 32'h0) | (issue0OH[10] ? slots_10_decoded_inst : 32'h0) | (issue0OH[11] ? slots_11_decoded_inst : 32'h0) | (issue0OH[12] ? slots_12_decoded_inst : 32'h0) | (issue0OH[13] ? slots_13_decoded_inst : 32'h0) | (issue0OH[14] ? slots_14_decoded_inst : 32'h0) | (issue0OH[15] ? slots_15_decoded_inst : 32'h0); assign io_issue_0_decoded_rs1 = (issue0OH[0] ? slots_0_decoded_rs1 : 5'h0) | (issue0OH[1] ? slots_1_decoded_rs1 : 5'h0) | (issue0OH[2] ? slots_2_decoded_rs1 : 5'h0) | (issue0OH[3] ? slots_3_decoded_rs1 : 5'h0) | (issue0OH[4] ? slots_4_decoded_rs1 : 5'h0) | (issue0OH[5] ? slots_5_decoded_rs1 : 5'h0) | (issue0OH[6] ? slots_6_decoded_rs1 : 5'h0) | (issue0OH[7] ? slots_7_decoded_rs1 : 5'h0) | (issue0OH[8] ? slots_8_decoded_rs1 : 5'h0) | (issue0OH[9] ? slots_9_decoded_rs1 : 5'h0) | (issue0OH[10] ? slots_10_decoded_rs1 : 5'h0) | (issue0OH[11] ? slots_11_decoded_rs1 : 5'h0) | (issue0OH[12] ? slots_12_decoded_rs1 : 5'h0) | (issue0OH[13] ? slots_13_decoded_rs1 : 5'h0) | (issue0OH[14] ? slots_14_decoded_rs1 : 5'h0) | (issue0OH[15] ? slots_15_decoded_rs1 : 5'h0); assign io_issue_0_decoded_funct3 = (issue0OH[0] ? slots_0_decoded_funct3 : 3'h0) | (issue0OH[1] ? slots_1_decoded_funct3 : 3'h0) | (issue0OH[2] ? slots_2_decoded_funct3 : 3'h0) | (issue0OH[3] ? slots_3_decoded_funct3 : 3'h0) | (issue0OH[4] ? slots_4_decoded_funct3 : 3'h0) | (issue0OH[5] ? slots_5_decoded_funct3 : 3'h0) | (issue0OH[6] ? slots_6_decoded_funct3 : 3'h0) | (issue0OH[7] ? slots_7_decoded_funct3 : 3'h0) | (issue0OH[8] ? slots_8_decoded_funct3 : 3'h0) | (issue0OH[9] ? slots_9_decoded_funct3 : 3'h0) | (issue0OH[10] ? slots_10_decoded_funct3 : 3'h0) | (issue0OH[11] ? slots_11_decoded_funct3 : 3'h0) | (issue0OH[12] ? slots_12_decoded_funct3 : 3'h0) | (issue0OH[13] ? slots_13_decoded_funct3 : 3'h0) | (issue0OH[14] ? slots_14_decoded_funct3 : 3'h0) | (issue0OH[15] ? slots_15_decoded_funct3 : 3'h0); assign io_issue_0_decoded_immI = (issue0OH[0] ? slots_0_decoded_immI : 64'h0) | (issue0OH[1] ? slots_1_decoded_immI : 64'h0) | (issue0OH[2] ? slots_2_decoded_immI : 64'h0) | (issue0OH[3] ? slots_3_decoded_immI : 64'h0) | (issue0OH[4] ? slots_4_decoded_immI : 64'h0) | (issue0OH[5] ? slots_5_decoded_immI : 64'h0) | (issue0OH[6] ? slots_6_decoded_immI : 64'h0) | (issue0OH[7] ? slots_7_decoded_immI : 64'h0) | (issue0OH[8] ? slots_8_decoded_immI : 64'h0) | (issue0OH[9] ? slots_9_decoded_immI : 64'h0) | (issue0OH[10] ? slots_10_decoded_immI : 64'h0) | (issue0OH[11] ? slots_11_decoded_immI : 64'h0) | (issue0OH[12] ? slots_12_decoded_immI : 64'h0) | (issue0OH[13] ? slots_13_decoded_immI : 64'h0) | (issue0OH[14] ? slots_14_decoded_immI : 64'h0) | (issue0OH[15] ? slots_15_decoded_immI : 64'h0); assign io_issue_0_decoded_immS = (issue0OH[0] ? slots_0_decoded_immS : 64'h0) | (issue0OH[1] ? slots_1_decoded_immS : 64'h0) | (issue0OH[2] ? slots_2_decoded_immS : 64'h0) | (issue0OH[3] ? slots_3_decoded_immS : 64'h0) | (issue0OH[4] ? slots_4_decoded_immS : 64'h0) | (issue0OH[5] ? slots_5_decoded_immS : 64'h0) | (issue0OH[6] ? slots_6_decoded_immS : 64'h0) | (issue0OH[7] ? slots_7_decoded_immS : 64'h0) | (issue0OH[8] ? slots_8_decoded_immS : 64'h0) | (issue0OH[9] ? slots_9_decoded_immS : 64'h0) | (issue0OH[10] ? slots_10_decoded_immS : 64'h0) | (issue0OH[11] ? slots_11_decoded_immS : 64'h0) | (issue0OH[12] ? slots_12_decoded_immS : 64'h0) | (issue0OH[13] ? slots_13_decoded_immS : 64'h0) | (issue0OH[14] ? slots_14_decoded_immS : 64'h0) | (issue0OH[15] ? slots_15_decoded_immS : 64'h0); assign io_issue_0_decoded_immB = (issue0OH[0] ? slots_0_decoded_immB : 64'h0) | (issue0OH[1] ? slots_1_decoded_immB : 64'h0) | (issue0OH[2] ? slots_2_decoded_immB : 64'h0) | (issue0OH[3] ? slots_3_decoded_immB : 64'h0) | (issue0OH[4] ? slots_4_decoded_immB : 64'h0) | (issue0OH[5] ? slots_5_decoded_immB : 64'h0) | (issue0OH[6] ? slots_6_decoded_immB : 64'h0) | (issue0OH[7] ? slots_7_decoded_immB : 64'h0) | (issue0OH[8] ? slots_8_decoded_immB : 64'h0) | (issue0OH[9] ? slots_9_decoded_immB : 64'h0) | (issue0OH[10] ? slots_10_decoded_immB : 64'h0) | (issue0OH[11] ? slots_11_decoded_immB : 64'h0) | (issue0OH[12] ? slots_12_decoded_immB : 64'h0) | (issue0OH[13] ? slots_13_decoded_immB : 64'h0) | (issue0OH[14] ? slots_14_decoded_immB : 64'h0) | (issue0OH[15] ? slots_15_decoded_immB : 64'h0); assign io_issue_0_decoded_immU = (issue0OH[0] ? slots_0_decoded_immU : 64'h0) | (issue0OH[1] ? slots_1_decoded_immU : 64'h0) | (issue0OH[2] ? slots_2_decoded_immU : 64'h0) | (issue0OH[3] ? slots_3_decoded_immU : 64'h0) | (issue0OH[4] ? slots_4_decoded_immU : 64'h0) | (issue0OH[5] ? slots_5_decoded_immU : 64'h0) | (issue0OH[6] ? slots_6_decoded_immU : 64'h0) | (issue0OH[7] ? slots_7_decoded_immU : 64'h0) | (issue0OH[8] ? slots_8_decoded_immU : 64'h0) | (issue0OH[9] ? slots_9_decoded_immU : 64'h0) | (issue0OH[10] ? slots_10_decoded_immU : 64'h0) | (issue0OH[11] ? slots_11_decoded_immU : 64'h0) | (issue0OH[12] ? slots_12_decoded_immU : 64'h0) | (issue0OH[13] ? slots_13_decoded_immU : 64'h0) | (issue0OH[14] ? slots_14_decoded_immU : 64'h0) | (issue0OH[15] ? slots_15_decoded_immU : 64'h0); assign io_issue_0_decoded_immJ = (issue0OH[0] ? slots_0_decoded_immJ : 64'h0) | (issue0OH[1] ? slots_1_decoded_immJ : 64'h0) | (issue0OH[2] ? slots_2_decoded_immJ : 64'h0) | (issue0OH[3] ? slots_3_decoded_immJ : 64'h0) | (issue0OH[4] ? slots_4_decoded_immJ : 64'h0) | (issue0OH[5] ? slots_5_decoded_immJ : 64'h0) | (issue0OH[6] ? slots_6_decoded_immJ : 64'h0) | (issue0OH[7] ? slots_7_decoded_immJ : 64'h0) | (issue0OH[8] ? slots_8_decoded_immJ : 64'h0) | (issue0OH[9] ? slots_9_decoded_immJ : 64'h0) | (issue0OH[10] ? slots_10_decoded_immJ : 64'h0) | (issue0OH[11] ? slots_11_decoded_immJ : 64'h0) | (issue0OH[12] ? slots_12_decoded_immJ : 64'h0) | (issue0OH[13] ? slots_13_decoded_immJ : 64'h0) | (issue0OH[14] ? slots_14_decoded_immJ : 64'h0) | (issue0OH[15] ? slots_15_decoded_immJ : 64'h0); assign io_issue_0_decoded_aluFn = (issue0OH[0] ? slots_0_decoded_aluFn : 5'h0) | (issue0OH[1] ? slots_1_decoded_aluFn : 5'h0) | (issue0OH[2] ? slots_2_decoded_aluFn : 5'h0) | (issue0OH[3] ? slots_3_decoded_aluFn : 5'h0) | (issue0OH[4] ? slots_4_decoded_aluFn : 5'h0) | (issue0OH[5] ? slots_5_decoded_aluFn : 5'h0) | (issue0OH[6] ? slots_6_decoded_aluFn : 5'h0) | (issue0OH[7] ? slots_7_decoded_aluFn : 5'h0) | (issue0OH[8] ? slots_8_decoded_aluFn : 5'h0) | (issue0OH[9] ? slots_9_decoded_aluFn : 5'h0) | (issue0OH[10] ? slots_10_decoded_aluFn : 5'h0) | (issue0OH[11] ? slots_11_decoded_aluFn : 5'h0) | (issue0OH[12] ? slots_12_decoded_aluFn : 5'h0) | (issue0OH[13] ? slots_13_decoded_aluFn : 5'h0) | (issue0OH[14] ? slots_14_decoded_aluFn : 5'h0) | (issue0OH[15] ? slots_15_decoded_aluFn : 5'h0); assign io_issue_0_decoded_memWidth = (issue0OH[0] ? slots_0_decoded_memWidth : 3'h0) | (issue0OH[1] ? slots_1_decoded_memWidth : 3'h0) | (issue0OH[2] ? slots_2_decoded_memWidth : 3'h0) | (issue0OH[3] ? slots_3_decoded_memWidth : 3'h0) | (issue0OH[4] ? slots_4_decoded_memWidth : 3'h0) | (issue0OH[5] ? slots_5_decoded_memWidth : 3'h0) | (issue0OH[6] ? slots_6_decoded_memWidth : 3'h0) | (issue0OH[7] ? slots_7_decoded_memWidth : 3'h0) | (issue0OH[8] ? slots_8_decoded_memWidth : 3'h0) | (issue0OH[9] ? slots_9_decoded_memWidth : 3'h0) | (issue0OH[10] ? slots_10_decoded_memWidth : 3'h0) | (issue0OH[11] ? slots_11_decoded_memWidth : 3'h0) | (issue0OH[12] ? slots_12_decoded_memWidth : 3'h0) | (issue0OH[13] ? slots_13_decoded_memWidth : 3'h0) | (issue0OH[14] ? slots_14_decoded_memWidth : 3'h0) | (issue0OH[15] ? slots_15_decoded_memWidth : 3'h0); assign io_issue_0_decoded_memSigned = issue0OH[0] & slots_0_decoded_memSigned | issue0OH[1] & slots_1_decoded_memSigned | issue0OH[2] & slots_2_decoded_memSigned | issue0OH[3] & slots_3_decoded_memSigned | issue0OH[4] & slots_4_decoded_memSigned | issue0OH[5] & slots_5_decoded_memSigned | issue0OH[6] & slots_6_decoded_memSigned | issue0OH[7] & slots_7_decoded_memSigned | issue0OH[8] & slots_8_decoded_memSigned | issue0OH[9] & slots_9_decoded_memSigned | issue0OH[10] & slots_10_decoded_memSigned | issue0OH[11] & slots_11_decoded_memSigned | issue0OH[12] & slots_12_decoded_memSigned | issue0OH[13] & slots_13_decoded_memSigned | issue0OH[14] & slots_14_decoded_memSigned | issue0OH[15] & slots_15_decoded_memSigned; assign io_issue_0_decoded_isLoad = issue0OH[0] & slots_0_decoded_isLoad | issue0OH[1] & slots_1_decoded_isLoad | issue0OH[2] & slots_2_decoded_isLoad | issue0OH[3] & slots_3_decoded_isLoad | issue0OH[4] & slots_4_decoded_isLoad | issue0OH[5] & slots_5_decoded_isLoad | issue0OH[6] & slots_6_decoded_isLoad | issue0OH[7] & slots_7_decoded_isLoad | issue0OH[8] & slots_8_decoded_isLoad | issue0OH[9] & slots_9_decoded_isLoad | issue0OH[10] & slots_10_decoded_isLoad | issue0OH[11] & slots_11_decoded_isLoad | issue0OH[12] & slots_12_decoded_isLoad | issue0OH[13] & slots_13_decoded_isLoad | issue0OH[14] & slots_14_decoded_isLoad | issue0OH[15] & slots_15_decoded_isLoad; assign io_issue_0_decoded_isStore = issue0OH[0] & slots_0_decoded_isStore | issue0OH[1] & slots_1_decoded_isStore | issue0OH[2] & slots_2_decoded_isStore | issue0OH[3] & slots_3_decoded_isStore | issue0OH[4] & slots_4_decoded_isStore | issue0OH[5] & slots_5_decoded_isStore | issue0OH[6] & slots_6_decoded_isStore | issue0OH[7] & slots_7_decoded_isStore | issue0OH[8] & slots_8_decoded_isStore | issue0OH[9] & slots_9_decoded_isStore | issue0OH[10] & slots_10_decoded_isStore | issue0OH[11] & slots_11_decoded_isStore | issue0OH[12] & slots_12_decoded_isStore | issue0OH[13] & slots_13_decoded_isStore | issue0OH[14] & slots_14_decoded_isStore | issue0OH[15] & slots_15_decoded_isStore; assign io_issue_0_decoded_isBranch = issue0OH[0] & slots_0_decoded_isBranch | issue0OH[1] & slots_1_decoded_isBranch | issue0OH[2] & slots_2_decoded_isBranch | issue0OH[3] & slots_3_decoded_isBranch | issue0OH[4] & slots_4_decoded_isBranch | issue0OH[5] & slots_5_decoded_isBranch | issue0OH[6] & slots_6_decoded_isBranch | issue0OH[7] & slots_7_decoded_isBranch | issue0OH[8] & slots_8_decoded_isBranch | issue0OH[9] & slots_9_decoded_isBranch | issue0OH[10] & slots_10_decoded_isBranch | issue0OH[11] & slots_11_decoded_isBranch | issue0OH[12] & slots_12_decoded_isBranch | issue0OH[13] & slots_13_decoded_isBranch | issue0OH[14] & slots_14_decoded_isBranch | issue0OH[15] & slots_15_decoded_isBranch; assign io_issue_0_decoded_isJal = issue0OH[0] & slots_0_decoded_isJal | issue0OH[1] & slots_1_decoded_isJal | issue0OH[2] & slots_2_decoded_isJal | issue0OH[3] & slots_3_decoded_isJal | issue0OH[4] & slots_4_decoded_isJal | issue0OH[5] & slots_5_decoded_isJal | issue0OH[6] & slots_6_decoded_isJal | issue0OH[7] & slots_7_decoded_isJal | issue0OH[8] & slots_8_decoded_isJal | issue0OH[9] & slots_9_decoded_isJal | issue0OH[10] & slots_10_decoded_isJal | issue0OH[11] & slots_11_decoded_isJal | issue0OH[12] & slots_12_decoded_isJal | issue0OH[13] & slots_13_decoded_isJal | issue0OH[14] & slots_14_decoded_isJal | issue0OH[15] & slots_15_decoded_isJal; assign io_issue_0_decoded_isJalr = issue0OH[0] & slots_0_decoded_isJalr | issue0OH[1] & slots_1_decoded_isJalr | issue0OH[2] & slots_2_decoded_isJalr | issue0OH[3] & slots_3_decoded_isJalr | issue0OH[4] & slots_4_decoded_isJalr | issue0OH[5] & slots_5_decoded_isJalr | issue0OH[6] & slots_6_decoded_isJalr | issue0OH[7] & slots_7_decoded_isJalr | issue0OH[8] & slots_8_decoded_isJalr | issue0OH[9] & slots_9_decoded_isJalr | issue0OH[10] & slots_10_decoded_isJalr | issue0OH[11] & slots_11_decoded_isJalr | issue0OH[12] & slots_12_decoded_isJalr | issue0OH[13] & slots_13_decoded_isJalr | issue0OH[14] & slots_14_decoded_isJalr | issue0OH[15] & slots_15_decoded_isJalr; assign io_issue_0_decoded_isLui = issue0OH[0] & slots_0_decoded_isLui | issue0OH[1] & slots_1_decoded_isLui | issue0OH[2] & slots_2_decoded_isLui | issue0OH[3] & slots_3_decoded_isLui | issue0OH[4] & slots_4_decoded_isLui | issue0OH[5] & slots_5_decoded_isLui | issue0OH[6] & slots_6_decoded_isLui | issue0OH[7] & slots_7_decoded_isLui | issue0OH[8] & slots_8_decoded_isLui | issue0OH[9] & slots_9_decoded_isLui | issue0OH[10] & slots_10_decoded_isLui | issue0OH[11] & slots_11_decoded_isLui | issue0OH[12] & slots_12_decoded_isLui | issue0OH[13] & slots_13_decoded_isLui | issue0OH[14] & slots_14_decoded_isLui | issue0OH[15] & slots_15_decoded_isLui; assign io_issue_0_decoded_isAuipc = issue0OH[0] & slots_0_decoded_isAuipc | issue0OH[1] & slots_1_decoded_isAuipc | issue0OH[2] & slots_2_decoded_isAuipc | issue0OH[3] & slots_3_decoded_isAuipc | issue0OH[4] & slots_4_decoded_isAuipc | issue0OH[5] & slots_5_decoded_isAuipc | issue0OH[6] & slots_6_decoded_isAuipc | issue0OH[7] & slots_7_decoded_isAuipc | issue0OH[8] & slots_8_decoded_isAuipc | issue0OH[9] & slots_9_decoded_isAuipc | issue0OH[10] & slots_10_decoded_isAuipc | issue0OH[11] & slots_11_decoded_isAuipc | issue0OH[12] & slots_12_decoded_isAuipc | issue0OH[13] & slots_13_decoded_isAuipc | issue0OH[14] & slots_14_decoded_isAuipc | issue0OH[15] & slots_15_decoded_isAuipc; assign io_issue_0_decoded_isOpImm = issue0OH[0] & slots_0_decoded_isOpImm | issue0OH[1] & slots_1_decoded_isOpImm | issue0OH[2] & slots_2_decoded_isOpImm | issue0OH[3] & slots_3_decoded_isOpImm | issue0OH[4] & slots_4_decoded_isOpImm | issue0OH[5] & slots_5_decoded_isOpImm | issue0OH[6] & slots_6_decoded_isOpImm | issue0OH[7] & slots_7_decoded_isOpImm | issue0OH[8] & slots_8_decoded_isOpImm | issue0OH[9] & slots_9_decoded_isOpImm | issue0OH[10] & slots_10_decoded_isOpImm | issue0OH[11] & slots_11_decoded_isOpImm | issue0OH[12] & slots_12_decoded_isOpImm | issue0OH[13] & slots_13_decoded_isOpImm | issue0OH[14] & slots_14_decoded_isOpImm | issue0OH[15] & slots_15_decoded_isOpImm; assign io_issue_0_decoded_isWord = issue0OH[0] & slots_0_decoded_isWord | issue0OH[1] & slots_1_decoded_isWord | issue0OH[2] & slots_2_decoded_isWord | issue0OH[3] & slots_3_decoded_isWord | issue0OH[4] & slots_4_decoded_isWord | issue0OH[5] & slots_5_decoded_isWord | issue0OH[6] & slots_6_decoded_isWord | issue0OH[7] & slots_7_decoded_isWord | issue0OH[8] & slots_8_decoded_isWord | issue0OH[9] & slots_9_decoded_isWord | issue0OH[10] & slots_10_decoded_isWord | issue0OH[11] & slots_11_decoded_isWord | issue0OH[12] & slots_12_decoded_isWord | issue0OH[13] & slots_13_decoded_isWord | issue0OH[14] & slots_14_decoded_isWord | issue0OH[15] & slots_15_decoded_isWord; assign io_issue_0_decoded_isSystem = issue0OH[0] & slots_0_decoded_isSystem | issue0OH[1] & slots_1_decoded_isSystem | issue0OH[2] & slots_2_decoded_isSystem | issue0OH[3] & slots_3_decoded_isSystem | issue0OH[4] & slots_4_decoded_isSystem | issue0OH[5] & slots_5_decoded_isSystem | issue0OH[6] & slots_6_decoded_isSystem | issue0OH[7] & slots_7_decoded_isSystem | issue0OH[8] & slots_8_decoded_isSystem | issue0OH[9] & slots_9_decoded_isSystem | issue0OH[10] & slots_10_decoded_isSystem | issue0OH[11] & slots_11_decoded_isSystem | issue0OH[12] & slots_12_decoded_isSystem | issue0OH[13] & slots_13_decoded_isSystem | issue0OH[14] & slots_14_decoded_isSystem | issue0OH[15] & slots_15_decoded_isSystem; assign io_issue_0_decoded_isFenceI = issue0OH[0] & slots_0_decoded_isFenceI | issue0OH[1] & slots_1_decoded_isFenceI | issue0OH[2] & slots_2_decoded_isFenceI | issue0OH[3] & slots_3_decoded_isFenceI | issue0OH[4] & slots_4_decoded_isFenceI | issue0OH[5] & slots_5_decoded_isFenceI | issue0OH[6] & slots_6_decoded_isFenceI | issue0OH[7] & slots_7_decoded_isFenceI | issue0OH[8] & slots_8_decoded_isFenceI | issue0OH[9] & slots_9_decoded_isFenceI | issue0OH[10] & slots_10_decoded_isFenceI | issue0OH[11] & slots_11_decoded_isFenceI | issue0OH[12] & slots_12_decoded_isFenceI | issue0OH[13] & slots_13_decoded_isFenceI | issue0OH[14] & slots_14_decoded_isFenceI | issue0OH[15] & slots_15_decoded_isFenceI; assign io_issue_0_decoded_isEcall = issue0OH[0] & slots_0_decoded_isEcall | issue0OH[1] & slots_1_decoded_isEcall | issue0OH[2] & slots_2_decoded_isEcall | issue0OH[3] & slots_3_decoded_isEcall | issue0OH[4] & slots_4_decoded_isEcall | issue0OH[5] & slots_5_decoded_isEcall | issue0OH[6] & slots_6_decoded_isEcall | issue0OH[7] & slots_7_decoded_isEcall | issue0OH[8] & slots_8_decoded_isEcall | issue0OH[9] & slots_9_decoded_isEcall | issue0OH[10] & slots_10_decoded_isEcall | issue0OH[11] & slots_11_decoded_isEcall | issue0OH[12] & slots_12_decoded_isEcall | issue0OH[13] & slots_13_decoded_isEcall | issue0OH[14] & slots_14_decoded_isEcall | issue0OH[15] & slots_15_decoded_isEcall; assign io_issue_0_decoded_isEbreak = issue0OH[0] & slots_0_decoded_isEbreak | issue0OH[1] & slots_1_decoded_isEbreak | issue0OH[2] & slots_2_decoded_isEbreak | issue0OH[3] & slots_3_decoded_isEbreak | issue0OH[4] & slots_4_decoded_isEbreak | issue0OH[5] & slots_5_decoded_isEbreak | issue0OH[6] & slots_6_decoded_isEbreak | issue0OH[7] & slots_7_decoded_isEbreak | issue0OH[8] & slots_8_decoded_isEbreak | issue0OH[9] & slots_9_decoded_isEbreak | issue0OH[10] & slots_10_decoded_isEbreak | issue0OH[11] & slots_11_decoded_isEbreak | issue0OH[12] & slots_12_decoded_isEbreak | issue0OH[13] & slots_13_decoded_isEbreak | issue0OH[14] & slots_14_decoded_isEbreak | issue0OH[15] & slots_15_decoded_isEbreak; assign io_issue_0_decoded_isMret = issue0OH[0] & slots_0_decoded_isMret | issue0OH[1] & slots_1_decoded_isMret | issue0OH[2] & slots_2_decoded_isMret | issue0OH[3] & slots_3_decoded_isMret | issue0OH[4] & slots_4_decoded_isMret | issue0OH[5] & slots_5_decoded_isMret | issue0OH[6] & slots_6_decoded_isMret | issue0OH[7] & slots_7_decoded_isMret | issue0OH[8] & slots_8_decoded_isMret | issue0OH[9] & slots_9_decoded_isMret | issue0OH[10] & slots_10_decoded_isMret | issue0OH[11] & slots_11_decoded_isMret | issue0OH[12] & slots_12_decoded_isMret | issue0OH[13] & slots_13_decoded_isMret | issue0OH[14] & slots_14_decoded_isMret | issue0OH[15] & slots_15_decoded_isMret; assign io_issue_0_decoded_isSret = issue0OH[0] & slots_0_decoded_isSret | issue0OH[1] & slots_1_decoded_isSret | issue0OH[2] & slots_2_decoded_isSret | issue0OH[3] & slots_3_decoded_isSret | issue0OH[4] & slots_4_decoded_isSret | issue0OH[5] & slots_5_decoded_isSret | issue0OH[6] & slots_6_decoded_isSret | issue0OH[7] & slots_7_decoded_isSret | issue0OH[8] & slots_8_decoded_isSret | issue0OH[9] & slots_9_decoded_isSret | issue0OH[10] & slots_10_decoded_isSret | issue0OH[11] & slots_11_decoded_isSret | issue0OH[12] & slots_12_decoded_isSret | issue0OH[13] & slots_13_decoded_isSret | issue0OH[14] & slots_14_decoded_isSret | issue0OH[15] & slots_15_decoded_isSret; assign io_issue_0_decoded_isSfenceVma = issue0OH[0] & slots_0_decoded_isSfenceVma | issue0OH[1] & slots_1_decoded_isSfenceVma | issue0OH[2] & slots_2_decoded_isSfenceVma | issue0OH[3] & slots_3_decoded_isSfenceVma | issue0OH[4] & slots_4_decoded_isSfenceVma | issue0OH[5] & slots_5_decoded_isSfenceVma | issue0OH[6] & slots_6_decoded_isSfenceVma | issue0OH[7] & slots_7_decoded_isSfenceVma | issue0OH[8] & slots_8_decoded_isSfenceVma | issue0OH[9] & slots_9_decoded_isSfenceVma | issue0OH[10] & slots_10_decoded_isSfenceVma | issue0OH[11] & slots_11_decoded_isSfenceVma | issue0OH[12] & slots_12_decoded_isSfenceVma | issue0OH[13] & slots_13_decoded_isSfenceVma | issue0OH[14] & slots_14_decoded_isSfenceVma | issue0OH[15] & slots_15_decoded_isSfenceVma; assign io_issue_0_decoded_isXret = issue0OH[0] & slots_0_decoded_isXret | issue0OH[1] & slots_1_decoded_isXret | issue0OH[2] & slots_2_decoded_isXret | issue0OH[3] & slots_3_decoded_isXret | issue0OH[4] & slots_4_decoded_isXret | issue0OH[5] & slots_5_decoded_isXret | issue0OH[6] & slots_6_decoded_isXret | issue0OH[7] & slots_7_decoded_isXret | issue0OH[8] & slots_8_decoded_isXret | issue0OH[9] & slots_9_decoded_isXret | issue0OH[10] & slots_10_decoded_isXret | issue0OH[11] & slots_11_decoded_isXret | issue0OH[12] & slots_12_decoded_isXret | issue0OH[13] & slots_13_decoded_isXret | issue0OH[14] & slots_14_decoded_isXret | issue0OH[15] & slots_15_decoded_isXret; assign io_issue_0_decoded_isWfi = issue0OH[0] & slots_0_decoded_isWfi | issue0OH[1] & slots_1_decoded_isWfi | issue0OH[2] & slots_2_decoded_isWfi | issue0OH[3] & slots_3_decoded_isWfi | issue0OH[4] & slots_4_decoded_isWfi | issue0OH[5] & slots_5_decoded_isWfi | issue0OH[6] & slots_6_decoded_isWfi | issue0OH[7] & slots_7_decoded_isWfi | issue0OH[8] & slots_8_decoded_isWfi | issue0OH[9] & slots_9_decoded_isWfi | issue0OH[10] & slots_10_decoded_isWfi | issue0OH[11] & slots_11_decoded_isWfi | issue0OH[12] & slots_12_decoded_isWfi | issue0OH[13] & slots_13_decoded_isWfi | issue0OH[14] & slots_14_decoded_isWfi | issue0OH[15] & slots_15_decoded_isWfi; assign io_issue_0_decoded_isAmo = issue0OH[0] & slots_0_decoded_isAmo | issue0OH[1] & slots_1_decoded_isAmo | issue0OH[2] & slots_2_decoded_isAmo | issue0OH[3] & slots_3_decoded_isAmo | issue0OH[4] & slots_4_decoded_isAmo | issue0OH[5] & slots_5_decoded_isAmo | issue0OH[6] & slots_6_decoded_isAmo | issue0OH[7] & slots_7_decoded_isAmo | issue0OH[8] & slots_8_decoded_isAmo | issue0OH[9] & slots_9_decoded_isAmo | issue0OH[10] & slots_10_decoded_isAmo | issue0OH[11] & slots_11_decoded_isAmo | issue0OH[12] & slots_12_decoded_isAmo | issue0OH[13] & slots_13_decoded_isAmo | issue0OH[14] & slots_14_decoded_isAmo | issue0OH[15] & slots_15_decoded_isAmo; assign io_issue_0_decoded_amoOp = (issue0OH[0] ? slots_0_decoded_amoOp : 5'h0) | (issue0OH[1] ? slots_1_decoded_amoOp : 5'h0) | (issue0OH[2] ? slots_2_decoded_amoOp : 5'h0) | (issue0OH[3] ? slots_3_decoded_amoOp : 5'h0) | (issue0OH[4] ? slots_4_decoded_amoOp : 5'h0) | (issue0OH[5] ? slots_5_decoded_amoOp : 5'h0) | (issue0OH[6] ? slots_6_decoded_amoOp : 5'h0) | (issue0OH[7] ? slots_7_decoded_amoOp : 5'h0) | (issue0OH[8] ? slots_8_decoded_amoOp : 5'h0) | (issue0OH[9] ? slots_9_decoded_amoOp : 5'h0) | (issue0OH[10] ? slots_10_decoded_amoOp : 5'h0) | (issue0OH[11] ? slots_11_decoded_amoOp : 5'h0) | (issue0OH[12] ? slots_12_decoded_amoOp : 5'h0) | (issue0OH[13] ? slots_13_decoded_amoOp : 5'h0) | (issue0OH[14] ? slots_14_decoded_amoOp : 5'h0) | (issue0OH[15] ? slots_15_decoded_amoOp : 5'h0); assign io_issue_0_decoded_writesRd = issue0OH[0] & slots_0_decoded_writesRd | issue0OH[1] & slots_1_decoded_writesRd | issue0OH[2] & slots_2_decoded_writesRd | issue0OH[3] & slots_3_decoded_writesRd | issue0OH[4] & slots_4_decoded_writesRd | issue0OH[5] & slots_5_decoded_writesRd | issue0OH[6] & slots_6_decoded_writesRd | issue0OH[7] & slots_7_decoded_writesRd | issue0OH[8] & slots_8_decoded_writesRd | issue0OH[9] & slots_9_decoded_writesRd | issue0OH[10] & slots_10_decoded_writesRd | issue0OH[11] & slots_11_decoded_writesRd | issue0OH[12] & slots_12_decoded_writesRd | issue0OH[13] & slots_13_decoded_writesRd | issue0OH[14] & slots_14_decoded_writesRd | issue0OH[15] & slots_15_decoded_writesRd; assign io_issue_0_decoded_illegal = issue0OH[0] & slots_0_decoded_illegal | issue0OH[1] & slots_1_decoded_illegal | issue0OH[2] & slots_2_decoded_illegal | issue0OH[3] & slots_3_decoded_illegal | issue0OH[4] & slots_4_decoded_illegal | issue0OH[5] & slots_5_decoded_illegal | issue0OH[6] & slots_6_decoded_illegal | issue0OH[7] & slots_7_decoded_illegal | issue0OH[8] & slots_8_decoded_illegal | issue0OH[9] & slots_9_decoded_illegal | issue0OH[10] & slots_10_decoded_illegal | issue0OH[11] & slots_11_decoded_illegal | issue0OH[12] & slots_12_decoded_illegal | issue0OH[13] & slots_13_decoded_illegal | issue0OH[14] & slots_14_decoded_illegal | issue0OH[15] & slots_15_decoded_illegal; assign io_issue_0_decoded_fetchException = issue0OH[0] & slots_0_decoded_fetchException | issue0OH[1] & slots_1_decoded_fetchException | issue0OH[2] & slots_2_decoded_fetchException | issue0OH[3] & slots_3_decoded_fetchException | issue0OH[4] & slots_4_decoded_fetchException | issue0OH[5] & slots_5_decoded_fetchException | issue0OH[6] & slots_6_decoded_fetchException | issue0OH[7] & slots_7_decoded_fetchException | issue0OH[8] & slots_8_decoded_fetchException | issue0OH[9] & slots_9_decoded_fetchException | issue0OH[10] & slots_10_decoded_fetchException | issue0OH[11] & slots_11_decoded_fetchException | issue0OH[12] & slots_12_decoded_fetchException | issue0OH[13] & slots_13_decoded_fetchException | issue0OH[14] & slots_14_decoded_fetchException | issue0OH[15] & slots_15_decoded_fetchException; assign io_issue_0_decoded_fetchExceptionCause = (issue0OH[0] ? slots_0_decoded_fetchExceptionCause : 64'h0) | (issue0OH[1] ? slots_1_decoded_fetchExceptionCause : 64'h0) | (issue0OH[2] ? slots_2_decoded_fetchExceptionCause : 64'h0) | (issue0OH[3] ? slots_3_decoded_fetchExceptionCause : 64'h0) | (issue0OH[4] ? slots_4_decoded_fetchExceptionCause : 64'h0) | (issue0OH[5] ? slots_5_decoded_fetchExceptionCause : 64'h0) | (issue0OH[6] ? slots_6_decoded_fetchExceptionCause : 64'h0) | (issue0OH[7] ? slots_7_decoded_fetchExceptionCause : 64'h0) | (issue0OH[8] ? slots_8_decoded_fetchExceptionCause : 64'h0) | (issue0OH[9] ? slots_9_decoded_fetchExceptionCause : 64'h0) | (issue0OH[10] ? slots_10_decoded_fetchExceptionCause : 64'h0) | (issue0OH[11] ? slots_11_decoded_fetchExceptionCause : 64'h0) | (issue0OH[12] ? slots_12_decoded_fetchExceptionCause : 64'h0) | (issue0OH[13] ? slots_13_decoded_fetchExceptionCause : 64'h0) | (issue0OH[14] ? slots_14_decoded_fetchExceptionCause : 64'h0) | (issue0OH[15] ? slots_15_decoded_fetchExceptionCause : 64'h0); assign io_issue_0_decoded_fetchExceptionTval = (issue0OH[0] ? slots_0_decoded_fetchExceptionTval : 64'h0) | (issue0OH[1] ? slots_1_decoded_fetchExceptionTval : 64'h0) | (issue0OH[2] ? slots_2_decoded_fetchExceptionTval : 64'h0) | (issue0OH[3] ? slots_3_decoded_fetchExceptionTval : 64'h0) | (issue0OH[4] ? slots_4_decoded_fetchExceptionTval : 64'h0) | (issue0OH[5] ? slots_5_decoded_fetchExceptionTval : 64'h0) | (issue0OH[6] ? slots_6_decoded_fetchExceptionTval : 64'h0) | (issue0OH[7] ? slots_7_decoded_fetchExceptionTval : 64'h0) | (issue0OH[8] ? slots_8_decoded_fetchExceptionTval : 64'h0) | (issue0OH[9] ? slots_9_decoded_fetchExceptionTval : 64'h0) | (issue0OH[10] ? slots_10_decoded_fetchExceptionTval : 64'h0) | (issue0OH[11] ? slots_11_decoded_fetchExceptionTval : 64'h0) | (issue0OH[12] ? slots_12_decoded_fetchExceptionTval : 64'h0) | (issue0OH[13] ? slots_13_decoded_fetchExceptionTval : 64'h0) | (issue0OH[14] ? slots_14_decoded_fetchExceptionTval : 64'h0) | (issue0OH[15] ? slots_15_decoded_fetchExceptionTval : 64'h0); assign io_issue_0_prs1 = (issue0OH[0] ? slots_0_prs1 : 6'h0) | (issue0OH[1] ? slots_1_prs1 : 6'h0) | (issue0OH[2] ? slots_2_prs1 : 6'h0) | (issue0OH[3] ? slots_3_prs1 : 6'h0) | (issue0OH[4] ? slots_4_prs1 : 6'h0) | (issue0OH[5] ? slots_5_prs1 : 6'h0) | (issue0OH[6] ? slots_6_prs1 : 6'h0) | (issue0OH[7] ? slots_7_prs1 : 6'h0) | (issue0OH[8] ? slots_8_prs1 : 6'h0) | (issue0OH[9] ? slots_9_prs1 : 6'h0) | (issue0OH[10] ? slots_10_prs1 : 6'h0) | (issue0OH[11] ? slots_11_prs1 : 6'h0) | (issue0OH[12] ? slots_12_prs1 : 6'h0) | (issue0OH[13] ? slots_13_prs1 : 6'h0) | (issue0OH[14] ? slots_14_prs1 : 6'h0) | (issue0OH[15] ? slots_15_prs1 : 6'h0); assign io_issue_0_prs2 = (issue0OH[0] ? slots_0_prs2 : 6'h0) | (issue0OH[1] ? slots_1_prs2 : 6'h0) | (issue0OH[2] ? slots_2_prs2 : 6'h0) | (issue0OH[3] ? slots_3_prs2 : 6'h0) | (issue0OH[4] ? slots_4_prs2 : 6'h0) | (issue0OH[5] ? slots_5_prs2 : 6'h0) | (issue0OH[6] ? slots_6_prs2 : 6'h0) | (issue0OH[7] ? slots_7_prs2 : 6'h0) | (issue0OH[8] ? slots_8_prs2 : 6'h0) | (issue0OH[9] ? slots_9_prs2 : 6'h0) | (issue0OH[10] ? slots_10_prs2 : 6'h0) | (issue0OH[11] ? slots_11_prs2 : 6'h0) | (issue0OH[12] ? slots_12_prs2 : 6'h0) | (issue0OH[13] ? slots_13_prs2 : 6'h0) | (issue0OH[14] ? slots_14_prs2 : 6'h0) | (issue0OH[15] ? slots_15_prs2 : 6'h0); assign io_issue_0_prd = (issue0OH[0] ? slots_0_prd : 6'h0) | (issue0OH[1] ? slots_1_prd : 6'h0) | (issue0OH[2] ? slots_2_prd : 6'h0) | (issue0OH[3] ? slots_3_prd : 6'h0) | (issue0OH[4] ? slots_4_prd : 6'h0) | (issue0OH[5] ? slots_5_prd : 6'h0) | (issue0OH[6] ? slots_6_prd : 6'h0) | (issue0OH[7] ? slots_7_prd : 6'h0) | (issue0OH[8] ? slots_8_prd : 6'h0) | (issue0OH[9] ? slots_9_prd : 6'h0) | (issue0OH[10] ? slots_10_prd : 6'h0) | (issue0OH[11] ? slots_11_prd : 6'h0) | (issue0OH[12] ? slots_12_prd : 6'h0) | (issue0OH[13] ? slots_13_prd : 6'h0) | (issue0OH[14] ? slots_14_prd : 6'h0) | (issue0OH[15] ? slots_15_prd : 6'h0); assign io_issue_0_robIdx = (issue0OH[0] ? slots_0_robIdx : 6'h0) | (issue0OH[1] ? slots_1_robIdx : 6'h0) | (issue0OH[2] ? slots_2_robIdx : 6'h0) | (issue0OH[3] ? slots_3_robIdx : 6'h0) | (issue0OH[4] ? slots_4_robIdx : 6'h0) | (issue0OH[5] ? slots_5_robIdx : 6'h0) | (issue0OH[6] ? slots_6_robIdx : 6'h0) | (issue0OH[7] ? slots_7_robIdx : 6'h0) | (issue0OH[8] ? slots_8_robIdx : 6'h0) | (issue0OH[9] ? slots_9_robIdx : 6'h0) | (issue0OH[10] ? slots_10_robIdx : 6'h0) | (issue0OH[11] ? slots_11_robIdx : 6'h0) | (issue0OH[12] ? slots_12_robIdx : 6'h0) | (issue0OH[13] ? slots_13_robIdx : 6'h0) | (issue0OH[14] ? slots_14_robIdx : 6'h0) | (issue0OH[15] ? slots_15_robIdx : 6'h0); assign io_issue_1_decoded_pc = (issue1OH[0] ? slots_0_decoded_pc : 64'h0) | (issue1OH[1] ? slots_1_decoded_pc : 64'h0) | (issue1OH[2] ? slots_2_decoded_pc : 64'h0) | (issue1OH[3] ? slots_3_decoded_pc : 64'h0) | (issue1OH[4] ? slots_4_decoded_pc : 64'h0) | (issue1OH[5] ? slots_5_decoded_pc : 64'h0) | (issue1OH[6] ? slots_6_decoded_pc : 64'h0) | (issue1OH[7] ? slots_7_decoded_pc : 64'h0) | (issue1OH[8] ? slots_8_decoded_pc : 64'h0) | (issue1OH[9] ? slots_9_decoded_pc : 64'h0) | (issue1OH[10] ? slots_10_decoded_pc : 64'h0) | (issue1OH[11] ? slots_11_decoded_pc : 64'h0) | (issue1OH[12] ? slots_12_decoded_pc : 64'h0) | (issue1OH[13] ? slots_13_decoded_pc : 64'h0) | (issue1OH[14] ? slots_14_decoded_pc : 64'h0) | (issue1OH[15] ? slots_15_decoded_pc : 64'h0); assign io_issue_1_decoded_inst = (issue1OH[0] ? slots_0_decoded_inst : 32'h0) | (issue1OH[1] ? slots_1_decoded_inst : 32'h0) | (issue1OH[2] ? slots_2_decoded_inst : 32'h0) | (issue1OH[3] ? slots_3_decoded_inst : 32'h0) | (issue1OH[4] ? slots_4_decoded_inst : 32'h0) | (issue1OH[5] ? slots_5_decoded_inst : 32'h0) | (issue1OH[6] ? slots_6_decoded_inst : 32'h0) | (issue1OH[7] ? slots_7_decoded_inst : 32'h0) | (issue1OH[8] ? slots_8_decoded_inst : 32'h0) | (issue1OH[9] ? slots_9_decoded_inst : 32'h0) | (issue1OH[10] ? slots_10_decoded_inst : 32'h0) | (issue1OH[11] ? slots_11_decoded_inst : 32'h0) | (issue1OH[12] ? slots_12_decoded_inst : 32'h0) | (issue1OH[13] ? slots_13_decoded_inst : 32'h0) | (issue1OH[14] ? slots_14_decoded_inst : 32'h0) | (issue1OH[15] ? slots_15_decoded_inst : 32'h0); assign io_issue_1_decoded_rs1 = (issue1OH[0] ? slots_0_decoded_rs1 : 5'h0) | (issue1OH[1] ? slots_1_decoded_rs1 : 5'h0) | (issue1OH[2] ? slots_2_decoded_rs1 : 5'h0) | (issue1OH[3] ? slots_3_decoded_rs1 : 5'h0) | (issue1OH[4] ? slots_4_decoded_rs1 : 5'h0) | (issue1OH[5] ? slots_5_decoded_rs1 : 5'h0) | (issue1OH[6] ? slots_6_decoded_rs1 : 5'h0) | (issue1OH[7] ? slots_7_decoded_rs1 : 5'h0) | (issue1OH[8] ? slots_8_decoded_rs1 : 5'h0) | (issue1OH[9] ? slots_9_decoded_rs1 : 5'h0) | (issue1OH[10] ? slots_10_decoded_rs1 : 5'h0) | (issue1OH[11] ? slots_11_decoded_rs1 : 5'h0) | (issue1OH[12] ? slots_12_decoded_rs1 : 5'h0) | (issue1OH[13] ? slots_13_decoded_rs1 : 5'h0) | (issue1OH[14] ? slots_14_decoded_rs1 : 5'h0) | (issue1OH[15] ? slots_15_decoded_rs1 : 5'h0); assign io_issue_1_decoded_funct3 = (issue1OH[0] ? slots_0_decoded_funct3 : 3'h0) | (issue1OH[1] ? slots_1_decoded_funct3 : 3'h0) | (issue1OH[2] ? slots_2_decoded_funct3 : 3'h0) | (issue1OH[3] ? slots_3_decoded_funct3 : 3'h0) | (issue1OH[4] ? slots_4_decoded_funct3 : 3'h0) | (issue1OH[5] ? slots_5_decoded_funct3 : 3'h0) | (issue1OH[6] ? slots_6_decoded_funct3 : 3'h0) | (issue1OH[7] ? slots_7_decoded_funct3 : 3'h0) | (issue1OH[8] ? slots_8_decoded_funct3 : 3'h0) | (issue1OH[9] ? slots_9_decoded_funct3 : 3'h0) | (issue1OH[10] ? slots_10_decoded_funct3 : 3'h0) | (issue1OH[11] ? slots_11_decoded_funct3 : 3'h0) | (issue1OH[12] ? slots_12_decoded_funct3 : 3'h0) | (issue1OH[13] ? slots_13_decoded_funct3 : 3'h0) | (issue1OH[14] ? slots_14_decoded_funct3 : 3'h0) | (issue1OH[15] ? slots_15_decoded_funct3 : 3'h0); assign io_issue_1_decoded_immI = (issue1OH[0] ? slots_0_decoded_immI : 64'h0) | (issue1OH[1] ? slots_1_decoded_immI : 64'h0) | (issue1OH[2] ? slots_2_decoded_immI : 64'h0) | (issue1OH[3] ? slots_3_decoded_immI : 64'h0) | (issue1OH[4] ? slots_4_decoded_immI : 64'h0) | (issue1OH[5] ? slots_5_decoded_immI : 64'h0) | (issue1OH[6] ? slots_6_decoded_immI : 64'h0) | (issue1OH[7] ? slots_7_decoded_immI : 64'h0) | (issue1OH[8] ? slots_8_decoded_immI : 64'h0) | (issue1OH[9] ? slots_9_decoded_immI : 64'h0) | (issue1OH[10] ? slots_10_decoded_immI : 64'h0) | (issue1OH[11] ? slots_11_decoded_immI : 64'h0) | (issue1OH[12] ? slots_12_decoded_immI : 64'h0) | (issue1OH[13] ? slots_13_decoded_immI : 64'h0) | (issue1OH[14] ? slots_14_decoded_immI : 64'h0) | (issue1OH[15] ? slots_15_decoded_immI : 64'h0); assign io_issue_1_decoded_immS = (issue1OH[0] ? slots_0_decoded_immS : 64'h0) | (issue1OH[1] ? slots_1_decoded_immS : 64'h0) | (issue1OH[2] ? slots_2_decoded_immS : 64'h0) | (issue1OH[3] ? slots_3_decoded_immS : 64'h0) | (issue1OH[4] ? slots_4_decoded_immS : 64'h0) | (issue1OH[5] ? slots_5_decoded_immS : 64'h0) | (issue1OH[6] ? slots_6_decoded_immS : 64'h0) | (issue1OH[7] ? slots_7_decoded_immS : 64'h0) | (issue1OH[8] ? slots_8_decoded_immS : 64'h0) | (issue1OH[9] ? slots_9_decoded_immS : 64'h0) | (issue1OH[10] ? slots_10_decoded_immS : 64'h0) | (issue1OH[11] ? slots_11_decoded_immS : 64'h0) | (issue1OH[12] ? slots_12_decoded_immS : 64'h0) | (issue1OH[13] ? slots_13_decoded_immS : 64'h0) | (issue1OH[14] ? slots_14_decoded_immS : 64'h0) | (issue1OH[15] ? slots_15_decoded_immS : 64'h0); assign io_issue_1_decoded_immB = (issue1OH[0] ? slots_0_decoded_immB : 64'h0) | (issue1OH[1] ? slots_1_decoded_immB : 64'h0) | (issue1OH[2] ? slots_2_decoded_immB : 64'h0) | (issue1OH[3] ? slots_3_decoded_immB : 64'h0) | (issue1OH[4] ? slots_4_decoded_immB : 64'h0) | (issue1OH[5] ? slots_5_decoded_immB : 64'h0) | (issue1OH[6] ? slots_6_decoded_immB : 64'h0) | (issue1OH[7] ? slots_7_decoded_immB : 64'h0) | (issue1OH[8] ? slots_8_decoded_immB : 64'h0) | (issue1OH[9] ? slots_9_decoded_immB : 64'h0) | (issue1OH[10] ? slots_10_decoded_immB : 64'h0) | (issue1OH[11] ? slots_11_decoded_immB : 64'h0) | (issue1OH[12] ? slots_12_decoded_immB : 64'h0) | (issue1OH[13] ? slots_13_decoded_immB : 64'h0) | (issue1OH[14] ? slots_14_decoded_immB : 64'h0) | (issue1OH[15] ? slots_15_decoded_immB : 64'h0); assign io_issue_1_decoded_immU = (issue1OH[0] ? slots_0_decoded_immU : 64'h0) | (issue1OH[1] ? slots_1_decoded_immU : 64'h0) | (issue1OH[2] ? slots_2_decoded_immU : 64'h0) | (issue1OH[3] ? slots_3_decoded_immU : 64'h0) | (issue1OH[4] ? slots_4_decoded_immU : 64'h0) | (issue1OH[5] ? slots_5_decoded_immU : 64'h0) | (issue1OH[6] ? slots_6_decoded_immU : 64'h0) | (issue1OH[7] ? slots_7_decoded_immU : 64'h0) | (issue1OH[8] ? slots_8_decoded_immU : 64'h0) | (issue1OH[9] ? slots_9_decoded_immU : 64'h0) | (issue1OH[10] ? slots_10_decoded_immU : 64'h0) | (issue1OH[11] ? slots_11_decoded_immU : 64'h0) | (issue1OH[12] ? slots_12_decoded_immU : 64'h0) | (issue1OH[13] ? slots_13_decoded_immU : 64'h0) | (issue1OH[14] ? slots_14_decoded_immU : 64'h0) | (issue1OH[15] ? slots_15_decoded_immU : 64'h0); assign io_issue_1_decoded_immJ = (issue1OH[0] ? slots_0_decoded_immJ : 64'h0) | (issue1OH[1] ? slots_1_decoded_immJ : 64'h0) | (issue1OH[2] ? slots_2_decoded_immJ : 64'h0) | (issue1OH[3] ? slots_3_decoded_immJ : 64'h0) | (issue1OH[4] ? slots_4_decoded_immJ : 64'h0) | (issue1OH[5] ? slots_5_decoded_immJ : 64'h0) | (issue1OH[6] ? slots_6_decoded_immJ : 64'h0) | (issue1OH[7] ? slots_7_decoded_immJ : 64'h0) | (issue1OH[8] ? slots_8_decoded_immJ : 64'h0) | (issue1OH[9] ? slots_9_decoded_immJ : 64'h0) | (issue1OH[10] ? slots_10_decoded_immJ : 64'h0) | (issue1OH[11] ? slots_11_decoded_immJ : 64'h0) | (issue1OH[12] ? slots_12_decoded_immJ : 64'h0) | (issue1OH[13] ? slots_13_decoded_immJ : 64'h0) | (issue1OH[14] ? slots_14_decoded_immJ : 64'h0) | (issue1OH[15] ? slots_15_decoded_immJ : 64'h0); assign io_issue_1_decoded_aluFn = (issue1OH[0] ? slots_0_decoded_aluFn : 5'h0) | (issue1OH[1] ? slots_1_decoded_aluFn : 5'h0) | (issue1OH[2] ? slots_2_decoded_aluFn : 5'h0) | (issue1OH[3] ? slots_3_decoded_aluFn : 5'h0) | (issue1OH[4] ? slots_4_decoded_aluFn : 5'h0) | (issue1OH[5] ? slots_5_decoded_aluFn : 5'h0) | (issue1OH[6] ? slots_6_decoded_aluFn : 5'h0) | (issue1OH[7] ? slots_7_decoded_aluFn : 5'h0) | (issue1OH[8] ? slots_8_decoded_aluFn : 5'h0) | (issue1OH[9] ? slots_9_decoded_aluFn : 5'h0) | (issue1OH[10] ? slots_10_decoded_aluFn : 5'h0) | (issue1OH[11] ? slots_11_decoded_aluFn : 5'h0) | (issue1OH[12] ? slots_12_decoded_aluFn : 5'h0) | (issue1OH[13] ? slots_13_decoded_aluFn : 5'h0) | (issue1OH[14] ? slots_14_decoded_aluFn : 5'h0) | (issue1OH[15] ? slots_15_decoded_aluFn : 5'h0); assign io_issue_1_decoded_memWidth = (issue1OH[0] ? slots_0_decoded_memWidth : 3'h0) | (issue1OH[1] ? slots_1_decoded_memWidth : 3'h0) | (issue1OH[2] ? slots_2_decoded_memWidth : 3'h0) | (issue1OH[3] ? slots_3_decoded_memWidth : 3'h0) | (issue1OH[4] ? slots_4_decoded_memWidth : 3'h0) | (issue1OH[5] ? slots_5_decoded_memWidth : 3'h0) | (issue1OH[6] ? slots_6_decoded_memWidth : 3'h0) | (issue1OH[7] ? slots_7_decoded_memWidth : 3'h0) | (issue1OH[8] ? slots_8_decoded_memWidth : 3'h0) | (issue1OH[9] ? slots_9_decoded_memWidth : 3'h0) | (issue1OH[10] ? slots_10_decoded_memWidth : 3'h0) | (issue1OH[11] ? slots_11_decoded_memWidth : 3'h0) | (issue1OH[12] ? slots_12_decoded_memWidth : 3'h0) | (issue1OH[13] ? slots_13_decoded_memWidth : 3'h0) | (issue1OH[14] ? slots_14_decoded_memWidth : 3'h0) | (issue1OH[15] ? slots_15_decoded_memWidth : 3'h0); assign io_issue_1_decoded_memSigned = issue1OH[0] & slots_0_decoded_memSigned | issue1OH[1] & slots_1_decoded_memSigned | issue1OH[2] & slots_2_decoded_memSigned | issue1OH[3] & slots_3_decoded_memSigned | issue1OH[4] & slots_4_decoded_memSigned | issue1OH[5] & slots_5_decoded_memSigned | issue1OH[6] & slots_6_decoded_memSigned | issue1OH[7] & slots_7_decoded_memSigned | issue1OH[8] & slots_8_decoded_memSigned | issue1OH[9] & slots_9_decoded_memSigned | issue1OH[10] & slots_10_decoded_memSigned | issue1OH[11] & slots_11_decoded_memSigned | issue1OH[12] & slots_12_decoded_memSigned | issue1OH[13] & slots_13_decoded_memSigned | issue1OH[14] & slots_14_decoded_memSigned | issue1OH[15] & slots_15_decoded_memSigned; assign io_issue_1_decoded_isLoad = issue1OH[0] & slots_0_decoded_isLoad | issue1OH[1] & slots_1_decoded_isLoad | issue1OH[2] & slots_2_decoded_isLoad | issue1OH[3] & slots_3_decoded_isLoad | issue1OH[4] & slots_4_decoded_isLoad | issue1OH[5] & slots_5_decoded_isLoad | issue1OH[6] & slots_6_decoded_isLoad | issue1OH[7] & slots_7_decoded_isLoad | issue1OH[8] & slots_8_decoded_isLoad | issue1OH[9] & slots_9_decoded_isLoad | issue1OH[10] & slots_10_decoded_isLoad | issue1OH[11] & slots_11_decoded_isLoad | issue1OH[12] & slots_12_decoded_isLoad | issue1OH[13] & slots_13_decoded_isLoad | issue1OH[14] & slots_14_decoded_isLoad | issue1OH[15] & slots_15_decoded_isLoad; assign io_issue_1_decoded_isStore = issue1OH[0] & slots_0_decoded_isStore | issue1OH[1] & slots_1_decoded_isStore | issue1OH[2] & slots_2_decoded_isStore | issue1OH[3] & slots_3_decoded_isStore | issue1OH[4] & slots_4_decoded_isStore | issue1OH[5] & slots_5_decoded_isStore | issue1OH[6] & slots_6_decoded_isStore | issue1OH[7] & slots_7_decoded_isStore | issue1OH[8] & slots_8_decoded_isStore | issue1OH[9] & slots_9_decoded_isStore | issue1OH[10] & slots_10_decoded_isStore | issue1OH[11] & slots_11_decoded_isStore | issue1OH[12] & slots_12_decoded_isStore | issue1OH[13] & slots_13_decoded_isStore | issue1OH[14] & slots_14_decoded_isStore | issue1OH[15] & slots_15_decoded_isStore; assign io_issue_1_decoded_isBranch = issue1OH[0] & slots_0_decoded_isBranch | issue1OH[1] & slots_1_decoded_isBranch | issue1OH[2] & slots_2_decoded_isBranch | issue1OH[3] & slots_3_decoded_isBranch | issue1OH[4] & slots_4_decoded_isBranch | issue1OH[5] & slots_5_decoded_isBranch | issue1OH[6] & slots_6_decoded_isBranch | issue1OH[7] & slots_7_decoded_isBranch | issue1OH[8] & slots_8_decoded_isBranch | issue1OH[9] & slots_9_decoded_isBranch | issue1OH[10] & slots_10_decoded_isBranch | issue1OH[11] & slots_11_decoded_isBranch | issue1OH[12] & slots_12_decoded_isBranch | issue1OH[13] & slots_13_decoded_isBranch | issue1OH[14] & slots_14_decoded_isBranch | issue1OH[15] & slots_15_decoded_isBranch; assign io_issue_1_decoded_isJal = issue1OH[0] & slots_0_decoded_isJal | issue1OH[1] & slots_1_decoded_isJal | issue1OH[2] & slots_2_decoded_isJal | issue1OH[3] & slots_3_decoded_isJal | issue1OH[4] & slots_4_decoded_isJal | issue1OH[5] & slots_5_decoded_isJal | issue1OH[6] & slots_6_decoded_isJal | issue1OH[7] & slots_7_decoded_isJal | issue1OH[8] & slots_8_decoded_isJal | issue1OH[9] & slots_9_decoded_isJal | issue1OH[10] & slots_10_decoded_isJal | issue1OH[11] & slots_11_decoded_isJal | issue1OH[12] & slots_12_decoded_isJal | issue1OH[13] & slots_13_decoded_isJal | issue1OH[14] & slots_14_decoded_isJal | issue1OH[15] & slots_15_decoded_isJal; assign io_issue_1_decoded_isJalr = issue1OH[0] & slots_0_decoded_isJalr | issue1OH[1] & slots_1_decoded_isJalr | issue1OH[2] & slots_2_decoded_isJalr | issue1OH[3] & slots_3_decoded_isJalr | issue1OH[4] & slots_4_decoded_isJalr | issue1OH[5] & slots_5_decoded_isJalr | issue1OH[6] & slots_6_decoded_isJalr | issue1OH[7] & slots_7_decoded_isJalr | issue1OH[8] & slots_8_decoded_isJalr | issue1OH[9] & slots_9_decoded_isJalr | issue1OH[10] & slots_10_decoded_isJalr | issue1OH[11] & slots_11_decoded_isJalr | issue1OH[12] & slots_12_decoded_isJalr | issue1OH[13] & slots_13_decoded_isJalr | issue1OH[14] & slots_14_decoded_isJalr | issue1OH[15] & slots_15_decoded_isJalr; assign io_issue_1_decoded_isLui = issue1OH[0] & slots_0_decoded_isLui | issue1OH[1] & slots_1_decoded_isLui | issue1OH[2] & slots_2_decoded_isLui | issue1OH[3] & slots_3_decoded_isLui | issue1OH[4] & slots_4_decoded_isLui | issue1OH[5] & slots_5_decoded_isLui | issue1OH[6] & slots_6_decoded_isLui | issue1OH[7] & slots_7_decoded_isLui | issue1OH[8] & slots_8_decoded_isLui | issue1OH[9] & slots_9_decoded_isLui | issue1OH[10] & slots_10_decoded_isLui | issue1OH[11] & slots_11_decoded_isLui | issue1OH[12] & slots_12_decoded_isLui | issue1OH[13] & slots_13_decoded_isLui | issue1OH[14] & slots_14_decoded_isLui | issue1OH[15] & slots_15_decoded_isLui; assign io_issue_1_decoded_isAuipc = issue1OH[0] & slots_0_decoded_isAuipc | issue1OH[1] & slots_1_decoded_isAuipc | issue1OH[2] & slots_2_decoded_isAuipc | issue1OH[3] & slots_3_decoded_isAuipc | issue1OH[4] & slots_4_decoded_isAuipc | issue1OH[5] & slots_5_decoded_isAuipc | issue1OH[6] & slots_6_decoded_isAuipc | issue1OH[7] & slots_7_decoded_isAuipc | issue1OH[8] & slots_8_decoded_isAuipc | issue1OH[9] & slots_9_decoded_isAuipc | issue1OH[10] & slots_10_decoded_isAuipc | issue1OH[11] & slots_11_decoded_isAuipc | issue1OH[12] & slots_12_decoded_isAuipc | issue1OH[13] & slots_13_decoded_isAuipc | issue1OH[14] & slots_14_decoded_isAuipc | issue1OH[15] & slots_15_decoded_isAuipc; assign io_issue_1_decoded_isOpImm = issue1OH[0] & slots_0_decoded_isOpImm | issue1OH[1] & slots_1_decoded_isOpImm | issue1OH[2] & slots_2_decoded_isOpImm | issue1OH[3] & slots_3_decoded_isOpImm | issue1OH[4] & slots_4_decoded_isOpImm | issue1OH[5] & slots_5_decoded_isOpImm | issue1OH[6] & slots_6_decoded_isOpImm | issue1OH[7] & slots_7_decoded_isOpImm | issue1OH[8] & slots_8_decoded_isOpImm | issue1OH[9] & slots_9_decoded_isOpImm | issue1OH[10] & slots_10_decoded_isOpImm | issue1OH[11] & slots_11_decoded_isOpImm | issue1OH[12] & slots_12_decoded_isOpImm | issue1OH[13] & slots_13_decoded_isOpImm | issue1OH[14] & slots_14_decoded_isOpImm | issue1OH[15] & slots_15_decoded_isOpImm; assign io_issue_1_decoded_isWord = issue1OH[0] & slots_0_decoded_isWord | issue1OH[1] & slots_1_decoded_isWord | issue1OH[2] & slots_2_decoded_isWord | issue1OH[3] & slots_3_decoded_isWord | issue1OH[4] & slots_4_decoded_isWord | issue1OH[5] & slots_5_decoded_isWord | issue1OH[6] & slots_6_decoded_isWord | issue1OH[7] & slots_7_decoded_isWord | issue1OH[8] & slots_8_decoded_isWord | issue1OH[9] & slots_9_decoded_isWord | issue1OH[10] & slots_10_decoded_isWord | issue1OH[11] & slots_11_decoded_isWord | issue1OH[12] & slots_12_decoded_isWord | issue1OH[13] & slots_13_decoded_isWord | issue1OH[14] & slots_14_decoded_isWord | issue1OH[15] & slots_15_decoded_isWord; assign io_issue_1_decoded_isSystem = issue1OH[0] & slots_0_decoded_isSystem | issue1OH[1] & slots_1_decoded_isSystem | issue1OH[2] & slots_2_decoded_isSystem | issue1OH[3] & slots_3_decoded_isSystem | issue1OH[4] & slots_4_decoded_isSystem | issue1OH[5] & slots_5_decoded_isSystem | issue1OH[6] & slots_6_decoded_isSystem | issue1OH[7] & slots_7_decoded_isSystem | issue1OH[8] & slots_8_decoded_isSystem | issue1OH[9] & slots_9_decoded_isSystem | issue1OH[10] & slots_10_decoded_isSystem | issue1OH[11] & slots_11_decoded_isSystem | issue1OH[12] & slots_12_decoded_isSystem | issue1OH[13] & slots_13_decoded_isSystem | issue1OH[14] & slots_14_decoded_isSystem | issue1OH[15] & slots_15_decoded_isSystem; assign io_issue_1_decoded_isFenceI = issue1OH[0] & slots_0_decoded_isFenceI | issue1OH[1] & slots_1_decoded_isFenceI | issue1OH[2] & slots_2_decoded_isFenceI | issue1OH[3] & slots_3_decoded_isFenceI | issue1OH[4] & slots_4_decoded_isFenceI | issue1OH[5] & slots_5_decoded_isFenceI | issue1OH[6] & slots_6_decoded_isFenceI | issue1OH[7] & slots_7_decoded_isFenceI | issue1OH[8] & slots_8_decoded_isFenceI | issue1OH[9] & slots_9_decoded_isFenceI | issue1OH[10] & slots_10_decoded_isFenceI | issue1OH[11] & slots_11_decoded_isFenceI | issue1OH[12] & slots_12_decoded_isFenceI | issue1OH[13] & slots_13_decoded_isFenceI | issue1OH[14] & slots_14_decoded_isFenceI | issue1OH[15] & slots_15_decoded_isFenceI; assign io_issue_1_decoded_isEcall = issue1OH[0] & slots_0_decoded_isEcall | issue1OH[1] & slots_1_decoded_isEcall | issue1OH[2] & slots_2_decoded_isEcall | issue1OH[3] & slots_3_decoded_isEcall | issue1OH[4] & slots_4_decoded_isEcall | issue1OH[5] & slots_5_decoded_isEcall | issue1OH[6] & slots_6_decoded_isEcall | issue1OH[7] & slots_7_decoded_isEcall | issue1OH[8] & slots_8_decoded_isEcall | issue1OH[9] & slots_9_decoded_isEcall | issue1OH[10] & slots_10_decoded_isEcall | issue1OH[11] & slots_11_decoded_isEcall | issue1OH[12] & slots_12_decoded_isEcall | issue1OH[13] & slots_13_decoded_isEcall | issue1OH[14] & slots_14_decoded_isEcall | issue1OH[15] & slots_15_decoded_isEcall; assign io_issue_1_decoded_isEbreak = issue1OH[0] & slots_0_decoded_isEbreak | issue1OH[1] & slots_1_decoded_isEbreak | issue1OH[2] & slots_2_decoded_isEbreak | issue1OH[3] & slots_3_decoded_isEbreak | issue1OH[4] & slots_4_decoded_isEbreak | issue1OH[5] & slots_5_decoded_isEbreak | issue1OH[6] & slots_6_decoded_isEbreak | issue1OH[7] & slots_7_decoded_isEbreak | issue1OH[8] & slots_8_decoded_isEbreak | issue1OH[9] & slots_9_decoded_isEbreak | issue1OH[10] & slots_10_decoded_isEbreak | issue1OH[11] & slots_11_decoded_isEbreak | issue1OH[12] & slots_12_decoded_isEbreak | issue1OH[13] & slots_13_decoded_isEbreak | issue1OH[14] & slots_14_decoded_isEbreak | issue1OH[15] & slots_15_decoded_isEbreak; assign io_issue_1_decoded_isMret = issue1OH[0] & slots_0_decoded_isMret | issue1OH[1] & slots_1_decoded_isMret | issue1OH[2] & slots_2_decoded_isMret | issue1OH[3] & slots_3_decoded_isMret | issue1OH[4] & slots_4_decoded_isMret | issue1OH[5] & slots_5_decoded_isMret | issue1OH[6] & slots_6_decoded_isMret | issue1OH[7] & slots_7_decoded_isMret | issue1OH[8] & slots_8_decoded_isMret | issue1OH[9] & slots_9_decoded_isMret | issue1OH[10] & slots_10_decoded_isMret | issue1OH[11] & slots_11_decoded_isMret | issue1OH[12] & slots_12_decoded_isMret | issue1OH[13] & slots_13_decoded_isMret | issue1OH[14] & slots_14_decoded_isMret | issue1OH[15] & slots_15_decoded_isMret; assign io_issue_1_decoded_isSret = issue1OH[0] & slots_0_decoded_isSret | issue1OH[1] & slots_1_decoded_isSret | issue1OH[2] & slots_2_decoded_isSret | issue1OH[3] & slots_3_decoded_isSret | issue1OH[4] & slots_4_decoded_isSret | issue1OH[5] & slots_5_decoded_isSret | issue1OH[6] & slots_6_decoded_isSret | issue1OH[7] & slots_7_decoded_isSret | issue1OH[8] & slots_8_decoded_isSret | issue1OH[9] & slots_9_decoded_isSret | issue1OH[10] & slots_10_decoded_isSret | issue1OH[11] & slots_11_decoded_isSret | issue1OH[12] & slots_12_decoded_isSret | issue1OH[13] & slots_13_decoded_isSret | issue1OH[14] & slots_14_decoded_isSret | issue1OH[15] & slots_15_decoded_isSret; assign io_issue_1_decoded_isSfenceVma = issue1OH[0] & slots_0_decoded_isSfenceVma | issue1OH[1] & slots_1_decoded_isSfenceVma | issue1OH[2] & slots_2_decoded_isSfenceVma | issue1OH[3] & slots_3_decoded_isSfenceVma | issue1OH[4] & slots_4_decoded_isSfenceVma | issue1OH[5] & slots_5_decoded_isSfenceVma | issue1OH[6] & slots_6_decoded_isSfenceVma | issue1OH[7] & slots_7_decoded_isSfenceVma | issue1OH[8] & slots_8_decoded_isSfenceVma | issue1OH[9] & slots_9_decoded_isSfenceVma | issue1OH[10] & slots_10_decoded_isSfenceVma | issue1OH[11] & slots_11_decoded_isSfenceVma | issue1OH[12] & slots_12_decoded_isSfenceVma | issue1OH[13] & slots_13_decoded_isSfenceVma | issue1OH[14] & slots_14_decoded_isSfenceVma | issue1OH[15] & slots_15_decoded_isSfenceVma; assign io_issue_1_decoded_isXret = issue1OH[0] & slots_0_decoded_isXret | issue1OH[1] & slots_1_decoded_isXret | issue1OH[2] & slots_2_decoded_isXret | issue1OH[3] & slots_3_decoded_isXret | issue1OH[4] & slots_4_decoded_isXret | issue1OH[5] & slots_5_decoded_isXret | issue1OH[6] & slots_6_decoded_isXret | issue1OH[7] & slots_7_decoded_isXret | issue1OH[8] & slots_8_decoded_isXret | issue1OH[9] & slots_9_decoded_isXret | issue1OH[10] & slots_10_decoded_isXret | issue1OH[11] & slots_11_decoded_isXret | issue1OH[12] & slots_12_decoded_isXret | issue1OH[13] & slots_13_decoded_isXret | issue1OH[14] & slots_14_decoded_isXret | issue1OH[15] & slots_15_decoded_isXret; assign io_issue_1_decoded_isWfi = issue1OH[0] & slots_0_decoded_isWfi | issue1OH[1] & slots_1_decoded_isWfi | issue1OH[2] & slots_2_decoded_isWfi | issue1OH[3] & slots_3_decoded_isWfi | issue1OH[4] & slots_4_decoded_isWfi | issue1OH[5] & slots_5_decoded_isWfi | issue1OH[6] & slots_6_decoded_isWfi | issue1OH[7] & slots_7_decoded_isWfi | issue1OH[8] & slots_8_decoded_isWfi | issue1OH[9] & slots_9_decoded_isWfi | issue1OH[10] & slots_10_decoded_isWfi | issue1OH[11] & slots_11_decoded_isWfi | issue1OH[12] & slots_12_decoded_isWfi | issue1OH[13] & slots_13_decoded_isWfi | issue1OH[14] & slots_14_decoded_isWfi | issue1OH[15] & slots_15_decoded_isWfi; assign io_issue_1_decoded_isAmo = issue1OH[0] & slots_0_decoded_isAmo | issue1OH[1] & slots_1_decoded_isAmo | issue1OH[2] & slots_2_decoded_isAmo | issue1OH[3] & slots_3_decoded_isAmo | issue1OH[4] & slots_4_decoded_isAmo | issue1OH[5] & slots_5_decoded_isAmo | issue1OH[6] & slots_6_decoded_isAmo | issue1OH[7] & slots_7_decoded_isAmo | issue1OH[8] & slots_8_decoded_isAmo | issue1OH[9] & slots_9_decoded_isAmo | issue1OH[10] & slots_10_decoded_isAmo | issue1OH[11] & slots_11_decoded_isAmo | issue1OH[12] & slots_12_decoded_isAmo | issue1OH[13] & slots_13_decoded_isAmo | issue1OH[14] & slots_14_decoded_isAmo | issue1OH[15] & slots_15_decoded_isAmo; assign io_issue_1_decoded_amoOp = (issue1OH[0] ? slots_0_decoded_amoOp : 5'h0) | (issue1OH[1] ? slots_1_decoded_amoOp : 5'h0) | (issue1OH[2] ? slots_2_decoded_amoOp : 5'h0) | (issue1OH[3] ? slots_3_decoded_amoOp : 5'h0) | (issue1OH[4] ? slots_4_decoded_amoOp : 5'h0) | (issue1OH[5] ? slots_5_decoded_amoOp : 5'h0) | (issue1OH[6] ? slots_6_decoded_amoOp : 5'h0) | (issue1OH[7] ? slots_7_decoded_amoOp : 5'h0) | (issue1OH[8] ? slots_8_decoded_amoOp : 5'h0) | (issue1OH[9] ? slots_9_decoded_amoOp : 5'h0) | (issue1OH[10] ? slots_10_decoded_amoOp : 5'h0) | (issue1OH[11] ? slots_11_decoded_amoOp : 5'h0) | (issue1OH[12] ? slots_12_decoded_amoOp : 5'h0) | (issue1OH[13] ? slots_13_decoded_amoOp : 5'h0) | (issue1OH[14] ? slots_14_decoded_amoOp : 5'h0) | (issue1OH[15] ? slots_15_decoded_amoOp : 5'h0); assign io_issue_1_decoded_writesRd = issue1OH[0] & slots_0_decoded_writesRd | issue1OH[1] & slots_1_decoded_writesRd | issue1OH[2] & slots_2_decoded_writesRd | issue1OH[3] & slots_3_decoded_writesRd | issue1OH[4] & slots_4_decoded_writesRd | issue1OH[5] & slots_5_decoded_writesRd | issue1OH[6] & slots_6_decoded_writesRd | issue1OH[7] & slots_7_decoded_writesRd | issue1OH[8] & slots_8_decoded_writesRd | issue1OH[9] & slots_9_decoded_writesRd | issue1OH[10] & slots_10_decoded_writesRd | issue1OH[11] & slots_11_decoded_writesRd | issue1OH[12] & slots_12_decoded_writesRd | issue1OH[13] & slots_13_decoded_writesRd | issue1OH[14] & slots_14_decoded_writesRd | issue1OH[15] & slots_15_decoded_writesRd; assign io_issue_1_decoded_illegal = issue1OH[0] & slots_0_decoded_illegal | issue1OH[1] & slots_1_decoded_illegal | issue1OH[2] & slots_2_decoded_illegal | issue1OH[3] & slots_3_decoded_illegal | issue1OH[4] & slots_4_decoded_illegal | issue1OH[5] & slots_5_decoded_illegal | issue1OH[6] & slots_6_decoded_illegal | issue1OH[7] & slots_7_decoded_illegal | issue1OH[8] & slots_8_decoded_illegal | issue1OH[9] & slots_9_decoded_illegal | issue1OH[10] & slots_10_decoded_illegal | issue1OH[11] & slots_11_decoded_illegal | issue1OH[12] & slots_12_decoded_illegal | issue1OH[13] & slots_13_decoded_illegal | issue1OH[14] & slots_14_decoded_illegal | issue1OH[15] & slots_15_decoded_illegal; assign io_issue_1_decoded_fetchException = issue1OH[0] & slots_0_decoded_fetchException | issue1OH[1] & slots_1_decoded_fetchException | issue1OH[2] & slots_2_decoded_fetchException | issue1OH[3] & slots_3_decoded_fetchException | issue1OH[4] & slots_4_decoded_fetchException | issue1OH[5] & slots_5_decoded_fetchException | issue1OH[6] & slots_6_decoded_fetchException | issue1OH[7] & slots_7_decoded_fetchException | issue1OH[8] & slots_8_decoded_fetchException | issue1OH[9] & slots_9_decoded_fetchException | issue1OH[10] & slots_10_decoded_fetchException | issue1OH[11] & slots_11_decoded_fetchException | issue1OH[12] & slots_12_decoded_fetchException | issue1OH[13] & slots_13_decoded_fetchException | issue1OH[14] & slots_14_decoded_fetchException | issue1OH[15] & slots_15_decoded_fetchException; assign io_issue_1_decoded_fetchExceptionCause = (issue1OH[0] ? slots_0_decoded_fetchExceptionCause : 64'h0) | (issue1OH[1] ? slots_1_decoded_fetchExceptionCause : 64'h0) | (issue1OH[2] ? slots_2_decoded_fetchExceptionCause : 64'h0) | (issue1OH[3] ? slots_3_decoded_fetchExceptionCause : 64'h0) | (issue1OH[4] ? slots_4_decoded_fetchExceptionCause : 64'h0) | (issue1OH[5] ? slots_5_decoded_fetchExceptionCause : 64'h0) | (issue1OH[6] ? slots_6_decoded_fetchExceptionCause : 64'h0) | (issue1OH[7] ? slots_7_decoded_fetchExceptionCause : 64'h0) | (issue1OH[8] ? slots_8_decoded_fetchExceptionCause : 64'h0) | (issue1OH[9] ? slots_9_decoded_fetchExceptionCause : 64'h0) | (issue1OH[10] ? slots_10_decoded_fetchExceptionCause : 64'h0) | (issue1OH[11] ? slots_11_decoded_fetchExceptionCause : 64'h0) | (issue1OH[12] ? slots_12_decoded_fetchExceptionCause : 64'h0) | (issue1OH[13] ? slots_13_decoded_fetchExceptionCause : 64'h0) | (issue1OH[14] ? slots_14_decoded_fetchExceptionCause : 64'h0) | (issue1OH[15] ? slots_15_decoded_fetchExceptionCause : 64'h0); assign io_issue_1_decoded_fetchExceptionTval = (issue1OH[0] ? slots_0_decoded_fetchExceptionTval : 64'h0) | (issue1OH[1] ? slots_1_decoded_fetchExceptionTval : 64'h0) | (issue1OH[2] ? slots_2_decoded_fetchExceptionTval : 64'h0) | (issue1OH[3] ? slots_3_decoded_fetchExceptionTval : 64'h0) | (issue1OH[4] ? slots_4_decoded_fetchExceptionTval : 64'h0) | (issue1OH[5] ? slots_5_decoded_fetchExceptionTval : 64'h0) | (issue1OH[6] ? slots_6_decoded_fetchExceptionTval : 64'h0) | (issue1OH[7] ? slots_7_decoded_fetchExceptionTval : 64'h0) | (issue1OH[8] ? slots_8_decoded_fetchExceptionTval : 64'h0) | (issue1OH[9] ? slots_9_decoded_fetchExceptionTval : 64'h0) | (issue1OH[10] ? slots_10_decoded_fetchExceptionTval : 64'h0) | (issue1OH[11] ? slots_11_decoded_fetchExceptionTval : 64'h0) | (issue1OH[12] ? slots_12_decoded_fetchExceptionTval : 64'h0) | (issue1OH[13] ? slots_13_decoded_fetchExceptionTval : 64'h0) | (issue1OH[14] ? slots_14_decoded_fetchExceptionTval : 64'h0) | (issue1OH[15] ? slots_15_decoded_fetchExceptionTval : 64'h0); assign io_issue_1_prs1 = (issue1OH[0] ? slots_0_prs1 : 6'h0) | (issue1OH[1] ? slots_1_prs1 : 6'h0) | (issue1OH[2] ? slots_2_prs1 : 6'h0) | (issue1OH[3] ? slots_3_prs1 : 6'h0) | (issue1OH[4] ? slots_4_prs1 : 6'h0) | (issue1OH[5] ? slots_5_prs1 : 6'h0) | (issue1OH[6] ? slots_6_prs1 : 6'h0) | (issue1OH[7] ? slots_7_prs1 : 6'h0) | (issue1OH[8] ? slots_8_prs1 : 6'h0) | (issue1OH[9] ? slots_9_prs1 : 6'h0) | (issue1OH[10] ? slots_10_prs1 : 6'h0) | (issue1OH[11] ? slots_11_prs1 : 6'h0) | (issue1OH[12] ? slots_12_prs1 : 6'h0) | (issue1OH[13] ? slots_13_prs1 : 6'h0) | (issue1OH[14] ? slots_14_prs1 : 6'h0) | (issue1OH[15] ? slots_15_prs1 : 6'h0); assign io_issue_1_prs2 = (issue1OH[0] ? slots_0_prs2 : 6'h0) | (issue1OH[1] ? slots_1_prs2 : 6'h0) | (issue1OH[2] ? slots_2_prs2 : 6'h0) | (issue1OH[3] ? slots_3_prs2 : 6'h0) | (issue1OH[4] ? slots_4_prs2 : 6'h0) | (issue1OH[5] ? slots_5_prs2 : 6'h0) | (issue1OH[6] ? slots_6_prs2 : 6'h0) | (issue1OH[7] ? slots_7_prs2 : 6'h0) | (issue1OH[8] ? slots_8_prs2 : 6'h0) | (issue1OH[9] ? slots_9_prs2 : 6'h0) | (issue1OH[10] ? slots_10_prs2 : 6'h0) | (issue1OH[11] ? slots_11_prs2 : 6'h0) | (issue1OH[12] ? slots_12_prs2 : 6'h0) | (issue1OH[13] ? slots_13_prs2 : 6'h0) | (issue1OH[14] ? slots_14_prs2 : 6'h0) | (issue1OH[15] ? slots_15_prs2 : 6'h0); assign io_issue_1_prd = (issue1OH[0] ? slots_0_prd : 6'h0) | (issue1OH[1] ? slots_1_prd : 6'h0) | (issue1OH[2] ? slots_2_prd : 6'h0) | (issue1OH[3] ? slots_3_prd : 6'h0) | (issue1OH[4] ? slots_4_prd : 6'h0) | (issue1OH[5] ? slots_5_prd : 6'h0) | (issue1OH[6] ? slots_6_prd : 6'h0) | (issue1OH[7] ? slots_7_prd : 6'h0) | (issue1OH[8] ? slots_8_prd : 6'h0) | (issue1OH[9] ? slots_9_prd : 6'h0) | (issue1OH[10] ? slots_10_prd : 6'h0) | (issue1OH[11] ? slots_11_prd : 6'h0) | (issue1OH[12] ? slots_12_prd : 6'h0) | (issue1OH[13] ? slots_13_prd : 6'h0) | (issue1OH[14] ? slots_14_prd : 6'h0) | (issue1OH[15] ? slots_15_prd : 6'h0); assign io_issue_1_robIdx = (issue1OH[0] ? slots_0_robIdx : 6'h0) | (issue1OH[1] ? slots_1_robIdx : 6'h0) | (issue1OH[2] ? slots_2_robIdx : 6'h0) | (issue1OH[3] ? slots_3_robIdx : 6'h0) | (issue1OH[4] ? slots_4_robIdx : 6'h0) | (issue1OH[5] ? slots_5_robIdx : 6'h0) | (issue1OH[6] ? slots_6_robIdx : 6'h0) | (issue1OH[7] ? slots_7_robIdx : 6'h0) | (issue1OH[8] ? slots_8_robIdx : 6'h0) | (issue1OH[9] ? slots_9_robIdx : 6'h0) | (issue1OH[10] ? slots_10_robIdx : 6'h0) | (issue1OH[11] ? slots_11_robIdx : 6'h0) | (issue1OH[12] ? slots_12_robIdx : 6'h0) | (issue1OH[13] ? slots_13_robIdx : 6'h0) | (issue1OH[14] ? slots_14_robIdx : 6'h0) | (issue1OH[15] ? slots_15_robIdx : 6'h0); endmodule