// Generated by CIRCT firtool-1.139.0 module OoOBackend( input clock, reset, io_decodeValid_0, io_decodeValid_1, input [63:0] io_decode_0_pc, input [31:0] io_decode_0_inst, input [4:0] io_decode_0_rs1, io_decode_0_rs2, io_decode_0_rd, input [2:0] io_decode_0_funct3, input [63:0] io_decode_0_immI, io_decode_0_immS, io_decode_0_immB, io_decode_0_immU, io_decode_0_immJ, input [3:0] io_decode_0_opClass, input [4:0] io_decode_0_aluFn, input [2:0] io_decode_0_memWidth, input io_decode_0_memSigned, io_decode_0_isLoad, io_decode_0_isStore, io_decode_0_isBranch, io_decode_0_isJal, io_decode_0_isJalr, io_decode_0_isLui, io_decode_0_isAuipc, io_decode_0_isOpImm, io_decode_0_isWord, io_decode_0_isSystem, io_decode_0_isFenceI, io_decode_0_isEcall, io_decode_0_isEbreak, io_decode_0_isMret, io_decode_0_isSret, io_decode_0_isSfenceVma, io_decode_0_isXret, io_decode_0_isWfi, io_decode_0_isAmo, input [4:0] io_decode_0_amoOp, input io_decode_0_writesRd, io_decode_0_illegal, io_decode_0_fetchException, input [63:0] io_decode_0_fetchExceptionCause, io_decode_0_fetchExceptionTval, io_decode_1_pc, input [31:0] io_decode_1_inst, input [4:0] io_decode_1_rs1, io_decode_1_rs2, io_decode_1_rd, input [2:0] io_decode_1_funct3, input [63:0] io_decode_1_immI, io_decode_1_immS, io_decode_1_immB, io_decode_1_immU, io_decode_1_immJ, input [3:0] io_decode_1_opClass, input [4:0] io_decode_1_aluFn, input [2:0] io_decode_1_memWidth, input io_decode_1_memSigned, io_decode_1_isLoad, io_decode_1_isStore, io_decode_1_isBranch, io_decode_1_isJal, io_decode_1_isJalr, io_decode_1_isLui, io_decode_1_isAuipc, io_decode_1_isOpImm, io_decode_1_isWord, io_decode_1_isSystem, io_decode_1_isFenceI, io_decode_1_isEcall, io_decode_1_isEbreak, io_decode_1_isMret, io_decode_1_isSret, io_decode_1_isSfenceVma, io_decode_1_isXret, io_decode_1_isWfi, io_decode_1_isAmo, input [4:0] io_decode_1_amoOp, input io_decode_1_writesRd, io_decode_1_illegal, io_decode_1_fetchException, input [63:0] io_decode_1_fetchExceptionCause, io_decode_1_fetchExceptionTval, output io_decodeReady, io_flush, output [63:0] io_redirectPc, output io_invalidateICache, io_sfenceVma, io_setPriv, output [1:0] io_targetPriv, output io_dmemReqValid, output [63:0] io_dmemReq_addr, io_dmemReq_data, output io_dmemReq_isStore, output [2:0] io_dmemReq_size, input io_dmemRespValid, input [63:0] io_dmemRespData, output [63:0] io_satpOut, input [1:0] io_currentPriv ); wire storeCheckRespNow; wire [63:0] _csr_io_rdata; wire _csr_io_readIllegal; wire [63:0] _csr_io_trapVector; wire [63:0] _csr_io_satp; wire [63:0] _csr_io_mepc; wire [63:0] _csr_io_sepc; wire [63:0] _csr_io_medeleg; wire [63:0] _csr_io_mstatus; wire _lsu_io_reqReady; wire _lsu_io_respValid; wire [63:0] _lsu_io_respData; wire _lsu_io_pageFault; wire _lsu_io_misaligned; wire [63:0] _lsu_io_faultCause; wire [63:0] _lsu_io_faultAddr; wire [3:0] _sq_io_enqIdx; wire _sq_io_forwardValid; wire [63:0] _sq_io_forwardData; wire _sq_io_forwardBlock; wire _sq_io_olderStoreValid; wire _sq_io_drainValid; wire [63:0] _sq_io_drain_addr; wire [63:0] _sq_io_drain_data; wire [2:0] _sq_io_drain_size; wire [3:0] _lq_io_enqIdx; wire _lq_io_violation; wire _commit_io_commitReady_0; wire _commit_io_commitReady_1; wire _commit_io_freeOldPhys_0; wire _commit_io_freeOldPhys_1; wire [5:0] _commit_io_oldPhys_0; wire [5:0] _commit_io_oldPhys_1; wire _commit_io_commitMapValid_0; wire _commit_io_commitMapValid_1; wire [4:0] _commit_io_commitArch_0; wire [4:0] _commit_io_commitArch_1; wire [5:0] _commit_io_commitPhys_0; wire [5:0] _commit_io_commitPhys_1; wire _commit_io_flush; wire [63:0] _commit_io_redirectPc; wire _commit_io_exception; wire [63:0] _commit_io_exceptionCause; wire [63:0] _commit_io_badAddr; wire [63:0] _commit_io_trapPc; wire _commit_io_sfenceVma; wire _commit_io_xret; wire _commit_io_xretIsMret; wire _wb_1_io_wen; wire [5:0] _wb_1_io_waddr; wire [63:0] _wb_1_io_wdata; wire _wb_0_io_wen; wire [5:0] _wb_0_io_waddr; wire [63:0] _wb_0_io_wdata; wire _exec_1_io_outValid; wire [63:0] _exec_1_io_result; wire _exec_1_io_branchTaken; wire _exec_0_io_outValid; wire [63:0] _exec_0_io_result; wire _exec_0_io_branchTaken; wire [63:0] _prf_io_rdata_0; wire [63:0] _prf_io_rdata_1; wire [63:0] _prf_io_rdata_2; wire [63:0] _prf_io_rdata_3; wire _issue_io_inReady_0; wire _issue_io_inReady_1; wire _issue_io_outValid_0; wire _issue_io_outValid_1; wire [63:0] _issue_io_out_0_decoded_pc; wire [31:0] _issue_io_out_0_decoded_inst; wire [4:0] _issue_io_out_0_decoded_rs1; wire [2:0] _issue_io_out_0_decoded_funct3; wire [63:0] _issue_io_out_0_decoded_immI; wire [63:0] _issue_io_out_0_decoded_immS; wire [63:0] _issue_io_out_0_decoded_immB; wire [63:0] _issue_io_out_0_decoded_immU; wire [63:0] _issue_io_out_0_decoded_immJ; wire [4:0] _issue_io_out_0_decoded_aluFn; wire [2:0] _issue_io_out_0_decoded_memWidth; wire _issue_io_out_0_decoded_memSigned; wire _issue_io_out_0_decoded_isLoad; wire _issue_io_out_0_decoded_isStore; wire _issue_io_out_0_decoded_isBranch; wire _issue_io_out_0_decoded_isJal; wire _issue_io_out_0_decoded_isJalr; wire _issue_io_out_0_decoded_isLui; wire _issue_io_out_0_decoded_isAuipc; wire _issue_io_out_0_decoded_isOpImm; wire _issue_io_out_0_decoded_isWord; wire _issue_io_out_0_decoded_isSystem; wire _issue_io_out_0_decoded_isFenceI; wire _issue_io_out_0_decoded_isEcall; wire _issue_io_out_0_decoded_isEbreak; wire _issue_io_out_0_decoded_isMret; wire _issue_io_out_0_decoded_isSret; wire _issue_io_out_0_decoded_isSfenceVma; wire _issue_io_out_0_decoded_isXret; wire _issue_io_out_0_decoded_isWfi; wire _issue_io_out_0_decoded_isAmo; wire [4:0] _issue_io_out_0_decoded_amoOp; wire _issue_io_out_0_decoded_writesRd; wire _issue_io_out_0_decoded_illegal; wire _issue_io_out_0_decoded_fetchException; wire [63:0] _issue_io_out_0_decoded_fetchExceptionCause; wire [63:0] _issue_io_out_0_decoded_fetchExceptionTval; wire [5:0] _issue_io_out_0_prs1; wire [5:0] _issue_io_out_0_prs2; wire [5:0] _issue_io_out_0_prd; wire [5:0] _issue_io_out_0_robIdx; wire [63:0] _issue_io_out_1_decoded_pc; wire [31:0] _issue_io_out_1_decoded_inst; wire [4:0] _issue_io_out_1_decoded_rs1; wire [2:0] _issue_io_out_1_decoded_funct3; wire [63:0] _issue_io_out_1_decoded_immI; wire [63:0] _issue_io_out_1_decoded_immS; wire [63:0] _issue_io_out_1_decoded_immB; wire [63:0] _issue_io_out_1_decoded_immU; wire [63:0] _issue_io_out_1_decoded_immJ; wire [4:0] _issue_io_out_1_decoded_aluFn; wire [2:0] _issue_io_out_1_decoded_memWidth; wire _issue_io_out_1_decoded_memSigned; wire _issue_io_out_1_decoded_isLoad; wire _issue_io_out_1_decoded_isStore; wire _issue_io_out_1_decoded_isBranch; wire _issue_io_out_1_decoded_isJal; wire _issue_io_out_1_decoded_isJalr; wire _issue_io_out_1_decoded_isLui; wire _issue_io_out_1_decoded_isAuipc; wire _issue_io_out_1_decoded_isOpImm; wire _issue_io_out_1_decoded_isWord; wire _issue_io_out_1_decoded_isSystem; wire _issue_io_out_1_decoded_isFenceI; wire _issue_io_out_1_decoded_isEcall; wire _issue_io_out_1_decoded_isEbreak; wire _issue_io_out_1_decoded_isMret; wire _issue_io_out_1_decoded_isSret; wire _issue_io_out_1_decoded_isSfenceVma; wire _issue_io_out_1_decoded_isXret; wire _issue_io_out_1_decoded_isWfi; wire _issue_io_out_1_decoded_isAmo; wire [4:0] _issue_io_out_1_decoded_amoOp; wire _issue_io_out_1_decoded_writesRd; wire _issue_io_out_1_decoded_illegal; wire _issue_io_out_1_decoded_fetchException; wire [63:0] _issue_io_out_1_decoded_fetchExceptionCause; wire [63:0] _issue_io_out_1_decoded_fetchExceptionTval; wire [5:0] _issue_io_out_1_prs1; wire [5:0] _issue_io_out_1_prs2; wire [5:0] _issue_io_out_1_prd; wire [5:0] _issue_io_out_1_robIdx; wire _rename_io_outValid_0; wire _rename_io_outValid_1; wire [63:0] _rename_io_out_0_decoded_pc; wire [31:0] _rename_io_out_0_decoded_inst; wire [4:0] _rename_io_out_0_decoded_rs1; wire [4:0] _rename_io_out_0_decoded_rs2; wire [2:0] _rename_io_out_0_decoded_funct3; wire [63:0] _rename_io_out_0_decoded_immI; wire [63:0] _rename_io_out_0_decoded_immS; wire [63:0] _rename_io_out_0_decoded_immB; wire [63:0] _rename_io_out_0_decoded_immU; wire [63:0] _rename_io_out_0_decoded_immJ; wire [4:0] _rename_io_out_0_decoded_aluFn; wire [2:0] _rename_io_out_0_decoded_memWidth; wire _rename_io_out_0_decoded_memSigned; wire _rename_io_out_0_decoded_isLoad; wire _rename_io_out_0_decoded_isStore; wire _rename_io_out_0_decoded_isBranch; wire _rename_io_out_0_decoded_isJal; wire _rename_io_out_0_decoded_isJalr; wire _rename_io_out_0_decoded_isLui; wire _rename_io_out_0_decoded_isAuipc; wire _rename_io_out_0_decoded_isOpImm; wire _rename_io_out_0_decoded_isWord; wire _rename_io_out_0_decoded_isSystem; wire _rename_io_out_0_decoded_isFenceI; wire _rename_io_out_0_decoded_isEcall; wire _rename_io_out_0_decoded_isEbreak; wire _rename_io_out_0_decoded_isMret; wire _rename_io_out_0_decoded_isSret; wire _rename_io_out_0_decoded_isSfenceVma; wire _rename_io_out_0_decoded_isXret; wire _rename_io_out_0_decoded_isWfi; wire _rename_io_out_0_decoded_isAmo; wire [4:0] _rename_io_out_0_decoded_amoOp; wire _rename_io_out_0_decoded_writesRd; wire _rename_io_out_0_decoded_illegal; wire _rename_io_out_0_decoded_fetchException; wire [63:0] _rename_io_out_0_decoded_fetchExceptionCause; wire [63:0] _rename_io_out_0_decoded_fetchExceptionTval; wire [5:0] _rename_io_out_0_prs1; wire [5:0] _rename_io_out_0_prs2; wire _rename_io_out_0_src1Ready; wire _rename_io_out_0_src2Ready; wire [5:0] _rename_io_out_0_prd; wire [5:0] _rename_io_out_0_robIdx; wire [63:0] _rename_io_out_1_decoded_pc; wire [31:0] _rename_io_out_1_decoded_inst; wire [4:0] _rename_io_out_1_decoded_rs1; wire [4:0] _rename_io_out_1_decoded_rs2; wire [2:0] _rename_io_out_1_decoded_funct3; wire [63:0] _rename_io_out_1_decoded_immI; wire [63:0] _rename_io_out_1_decoded_immS; wire [63:0] _rename_io_out_1_decoded_immB; wire [63:0] _rename_io_out_1_decoded_immU; wire [63:0] _rename_io_out_1_decoded_immJ; wire [4:0] _rename_io_out_1_decoded_aluFn; wire [2:0] _rename_io_out_1_decoded_memWidth; wire _rename_io_out_1_decoded_memSigned; wire _rename_io_out_1_decoded_isLoad; wire _rename_io_out_1_decoded_isStore; wire _rename_io_out_1_decoded_isBranch; wire _rename_io_out_1_decoded_isJal; wire _rename_io_out_1_decoded_isJalr; wire _rename_io_out_1_decoded_isLui; wire _rename_io_out_1_decoded_isAuipc; wire _rename_io_out_1_decoded_isOpImm; wire _rename_io_out_1_decoded_isWord; wire _rename_io_out_1_decoded_isSystem; wire _rename_io_out_1_decoded_isFenceI; wire _rename_io_out_1_decoded_isEcall; wire _rename_io_out_1_decoded_isEbreak; wire _rename_io_out_1_decoded_isMret; wire _rename_io_out_1_decoded_isSret; wire _rename_io_out_1_decoded_isSfenceVma; wire _rename_io_out_1_decoded_isXret; wire _rename_io_out_1_decoded_isWfi; wire _rename_io_out_1_decoded_isAmo; wire [4:0] _rename_io_out_1_decoded_amoOp; wire _rename_io_out_1_decoded_writesRd; wire _rename_io_out_1_decoded_illegal; wire _rename_io_out_1_decoded_fetchException; wire [63:0] _rename_io_out_1_decoded_fetchExceptionCause; wire [63:0] _rename_io_out_1_decoded_fetchExceptionTval; wire [5:0] _rename_io_out_1_prs1; wire [5:0] _rename_io_out_1_prs2; wire _rename_io_out_1_src1Ready; wire _rename_io_out_1_src2Ready; wire [5:0] _rename_io_out_1_prd; wire [5:0] _rename_io_out_1_robIdx; wire _rename_io_canAccept; wire _rename_io_commitValid_0; wire _rename_io_commitValid_1; wire _rename_io_commitEntry_0_valid; wire [5:0] _rename_io_commitEntry_0_robIdx; wire [63:0] _rename_io_commitEntry_0_pc; wire [4:0] _rename_io_commitEntry_0_archDest; wire _rename_io_commitEntry_0_writesDest; wire [3:0] _rename_io_commitEntry_0_opClass; wire [5:0] _rename_io_commitEntry_0_dest; wire [5:0] _rename_io_commitEntry_0_oldDest; wire _rename_io_commitEntry_0_exception; wire [63:0] _rename_io_commitEntry_0_exceptionCause; wire [63:0] _rename_io_commitEntry_0_badAddr; wire _rename_io_commitEntry_0_branchMispredict; wire [63:0] _rename_io_commitEntry_0_redirectPc; wire _rename_io_commitEntry_0_csrValid; wire [11:0] _rename_io_commitEntry_0_csrAddr; wire [2:0] _rename_io_commitEntry_0_csrCmd; wire [63:0] _rename_io_commitEntry_0_csrRs1; wire [4:0] _rename_io_commitEntry_0_csrZimm; wire _rename_io_commitEntry_0_fenceI; wire _rename_io_commitEntry_0_sfenceVma; wire _rename_io_commitEntry_0_xret; wire _rename_io_commitEntry_0_xretIsMret; wire [5:0] _rename_io_commitEntry_1_robIdx; wire [63:0] _rename_io_commitEntry_1_pc; wire [4:0] _rename_io_commitEntry_1_archDest; wire _rename_io_commitEntry_1_writesDest; wire [3:0] _rename_io_commitEntry_1_opClass; wire [5:0] _rename_io_commitEntry_1_dest; wire [5:0] _rename_io_commitEntry_1_oldDest; wire _rename_io_commitEntry_1_exception; wire [63:0] _rename_io_commitEntry_1_exceptionCause; wire [63:0] _rename_io_commitEntry_1_badAddr; wire _rename_io_commitEntry_1_branchMispredict; wire [63:0] _rename_io_commitEntry_1_redirectPc; wire _rename_io_commitEntry_1_csrValid; wire [11:0] _rename_io_commitEntry_1_csrAddr; wire [2:0] _rename_io_commitEntry_1_csrCmd; wire [63:0] _rename_io_commitEntry_1_csrRs1; wire [4:0] _rename_io_commitEntry_1_csrZimm; wire _rename_io_commitEntry_1_fenceI; wire _rename_io_commitEntry_1_sfenceVma; wire _rename_io_commitEntry_1_xret; wire _rename_io_commitEntry_1_xretIsMret; wire [3:0][7:0] _GEN = '{8'hB, 8'hB, 8'h9, 8'h8}; reg wakeupReg_0_valid; reg [5:0] wakeupReg_0_phys; reg [63:0] wakeupReg_0_data; reg wakeupReg_1_valid; reg [5:0] wakeupReg_1_phys; reg [63:0] wakeupReg_1_data; reg loadPending; reg [5:0] loadPendingRob; reg [5:0] loadPendingPhys; reg [3:0] loadPendingLq; reg forwardPending; reg [5:0] forwardPendingRob; reg [5:0] forwardPendingPhys; reg [3:0] forwardPendingLq; reg [63:0] forwardPendingData; wire loadRespValid = _lsu_io_respValid & loadPending | forwardPending; reg storeCheckPending; reg [5:0] storeCheckPendingRob; wire storeCheckRespPending = storeCheckPending & _lsu_io_respValid; wire storeCheckFault = (storeCheckRespNow | storeCheckRespPending) & (_lsu_io_pageFault | _lsu_io_misaligned); wire isMem0 = _issue_io_out_0_decoded_isLoad | _issue_io_out_0_decoded_isStore; wire memIssue_0 = _issue_io_outValid_0 & isMem0; wire isMem1 = _issue_io_out_1_decoded_isLoad | _issue_io_out_1_decoded_isStore; wire csrReadReq_0 = _issue_io_outValid_0 & _issue_io_out_0_decoded_isSystem & (|_issue_io_out_0_decoded_funct3); wire csrReadReq_1 = _issue_io_outValid_1 & _issue_io_out_1_decoded_isSystem & (|_issue_io_out_1_decoded_funct3); wire serializing0 = _issue_io_out_0_decoded_isSystem | _issue_io_out_0_decoded_isFenceI | _issue_io_out_0_decoded_isSfenceVma | _issue_io_out_0_decoded_isWfi; wire serializing1 = _issue_io_out_1_decoded_isSystem | _issue_io_out_1_decoded_isFenceI | _issue_io_out_1_decoded_isSfenceVma | _issue_io_out_1_decoded_isWfi; wire _issue0AtHead_T = _rename_io_commitEntry_0_robIdx == _issue_io_out_0_robIdx; wire serializingReady0 = ~serializing0 | _rename_io_commitEntry_0_valid & _issue0AtHead_T; wire _issue1AtHead_T = _rename_io_commitEntry_0_robIdx == _issue_io_out_1_robIdx; wire serializingReady1 = ~serializing1 | _rename_io_commitEntry_0_valid & _issue1AtHead_T; wire _amoBlocked1_T = _sq_io_olderStoreValid | _sq_io_drainValid; wire _olderSerializingAtHead1_T_2 = _rename_io_commitEntry_0_csrValid | _rename_io_commitEntry_0_fenceI; wire _memReady1_T_1 = _lsu_io_reqReady & ~loadPending & ~forwardPending & ~storeCheckPending; wire baseIssueReady0 = (~isMem0 | _memReady1_T_1 & ~(_issue_io_out_0_decoded_isAmo & _amoBlocked1_T) & ~(_issue_io_out_0_decoded_isLoad & _sq_io_forwardBlock)) & ~loadPending & ~forwardPending & serializingReady0 & ~(_rename_io_commitEntry_0_valid & ~(_rename_io_commitEntry_0_valid & _issue0AtHead_T) & (_olderSerializingAtHead1_T_2 | _rename_io_commitEntry_0_sfenceVma | _rename_io_commitEntry_0_xret)) & ~storeCheckPending; wire baseIssueReady1 = (~isMem1 | _memReady1_T_1 & ~memIssue_0 & ~(_issue_io_out_1_decoded_isAmo & _amoBlocked1_T) & ~(_issue_io_out_1_decoded_isLoad & _sq_io_forwardBlock)) & serializingReady1 & ~(_rename_io_commitEntry_0_valid & ~(_rename_io_commitEntry_0_valid & _issue1AtHead_T) & (_olderSerializingAtHead1_T_2 | _rename_io_commitEntry_0_sfenceVma | _rename_io_commitEntry_0_xret)) & ~storeCheckPending; wire issue_io_outReady_0 = baseIssueReady0 & ~(_issue_io_outValid_1 & baseIssueReady1 & serializing1); wire issue_io_outReady_1 = baseIssueReady1 & ~(_issue_io_outValid_0 & baseIssueReady0 & serializing0) & ~(csrReadReq_0 & csrReadReq_1 & issue_io_outReady_0); wire issueFire_0 = _issue_io_outValid_0 & issue_io_outReady_0; wire issueFire_1 = _issue_io_outValid_1 & issue_io_outReady_1; wire [63:0] memSrc2 = memIssue_0 ? _prf_io_rdata_1 : _prf_io_rdata_3; wire [2:0] sq_io_size = memIssue_0 ? _issue_io_out_0_decoded_memWidth : _issue_io_out_1_decoded_memWidth; wire _GEN_0 = memIssue_0 ? _issue_io_out_0_decoded_memSigned : _issue_io_out_1_decoded_memSigned; wire _GEN_1 = memIssue_0 ? _issue_io_out_0_decoded_isStore : _issue_io_out_1_decoded_isStore; wire loadReq_isAmo = memIssue_0 ? _issue_io_out_0_decoded_isAmo : _issue_io_out_1_decoded_isAmo; wire [5:0] sq_io_enqRobIdx = memIssue_0 ? _issue_io_out_0_robIdx : _issue_io_out_1_robIdx; wire [63:0] _memAddr_T_2 = (memIssue_0 ? _prf_io_rdata_0 : _prf_io_rdata_2) + (loadReq_isAmo ? 64'h0 : _GEN_1 ? (memIssue_0 ? _issue_io_out_0_decoded_immS : _issue_io_out_1_decoded_immS) : memIssue_0 ? _issue_io_out_0_decoded_immI : _issue_io_out_1_decoded_immI); wire _storeEnq_T = memIssue_0 | ~memIssue_0 & _issue_io_outValid_1 & isMem1; wire _GEN_2 = memIssue_0 ? issue_io_outReady_0 : issue_io_outReady_1; wire loadEnq = _storeEnq_T & (memIssue_0 ? _issue_io_out_0_decoded_isLoad : _issue_io_out_1_decoded_isLoad) & _GEN_2; wire storeEnq = _storeEnq_T & _GEN_1 & _GEN_2; wire sqForwardValid = _sq_io_forwardValid & ~loadReq_isAmo; wire lsuLoadReq = loadEnq & ~sqForwardValid; wire _commitCsr0_T = _commit_io_commitReady_0 & _rename_io_commitValid_0; wire _commitCsr1_T = _commit_io_commitReady_1 & _rename_io_commitValid_1; wire commitStore0 = _commitCsr0_T & _rename_io_commitEntry_0_opClass == 4'h4; wire storeDrainFire = _sq_io_drainValid & ~lsuLoadReq & ~storeEnq & _lsu_io_reqReady; wire _GEN_3 = lsuLoadReq | storeEnq; assign storeCheckRespNow = storeEnq & _lsu_io_respValid; wire csrReadFire_0 = csrReadReq_0 & issue_io_outReady_0; wire _illegalPriv_T_7 = io_currentPriv != 2'h3; wire [63:0] _trapTargetPriv_toSupervisor_T_2 = _csr_io_medeleg >> _commit_io_exceptionCause[5:0]; wire [1:0] trapTargetPriv = {~(_illegalPriv_T_7 & _trapTargetPriv_toSupervisor_T_2[0]), 1'h1}; wire commitCsr0 = _commitCsr0_T & _rename_io_commitEntry_0_csrValid; wire [63:0] src1 = wakeupReg_0_valid & (|wakeupReg_0_phys) & wakeupReg_0_phys == _issue_io_out_0_prs1 ? wakeupReg_0_data : wakeupReg_1_valid & (|wakeupReg_1_phys) & wakeupReg_1_phys == _issue_io_out_0_prs1 ? wakeupReg_1_data : _prf_io_rdata_0; wire [63:0] _branchTarget_T = _issue_io_out_0_decoded_pc + _issue_io_out_0_decoded_immB; wire [63:0] _jalTarget_T = _issue_io_out_0_decoded_pc + _issue_io_out_0_decoded_immJ; wire [63:0] _jalrTarget_T = src1 + _issue_io_out_0_decoded_immI; wire [63:0] jalrTarget = {_jalrTarget_T[63:1], 1'h0}; wire [63:0] controlTarget = _issue_io_out_0_decoded_isJal ? _jalTarget_T : _issue_io_out_0_decoded_isJalr ? jalrTarget : _branchTarget_T; wire _completeMispredict_0_T = _issue_io_out_0_decoded_isJal | _issue_io_out_0_decoded_isJalr; wire _completeMispredict_0_T_5 = _issue_io_out_0_decoded_isBranch & _exec_0_io_branchTaken; wire controlTargetMisaligned = issueFire_0 & (_completeMispredict_0_T | _completeMispredict_0_T_5) & (|(controlTarget[1:0])); wire [63:0] _completeRedirectPc_0_T_2 = _issue_io_out_0_decoded_pc + 64'h4; wire _completeCause_1_T_6 = io_currentPriv == 2'h0; wire _completeCsrValid_0_T_4 = _issue_io_out_0_decoded_rs1 == 5'h0; wire _csrWriteIllegal_T_76 = _issue_io_out_0_decoded_inst[31:20] == 12'h300; wire _csrWriteIllegal_T_77 = _issue_io_out_0_decoded_inst[31:20] == 12'h301; wire _csrWriteIllegal_T_79 = _issue_io_out_0_decoded_inst[31:20] == 12'h302; wire _csrWriteIllegal_T_81 = _issue_io_out_0_decoded_inst[31:20] == 12'h303; wire _csrWriteIllegal_T_83 = _issue_io_out_0_decoded_inst[31:20] == 12'h304; wire _csrWriteIllegal_T_85 = _issue_io_out_0_decoded_inst[31:20] == 12'h305; wire _csrWriteIllegal_T_87 = _issue_io_out_0_decoded_inst[31:20] == 12'h306; wire _csrWriteIllegal_T_89 = _issue_io_out_0_decoded_inst[31:20] == 12'h340; wire _csrWriteIllegal_T_91 = _issue_io_out_0_decoded_inst[31:20] == 12'h341; wire _csrWriteIllegal_T_93 = _issue_io_out_0_decoded_inst[31:20] == 12'h342; wire _csrWriteIllegal_T_95 = _issue_io_out_0_decoded_inst[31:20] == 12'h343; wire _csrWriteIllegal_T_97 = _issue_io_out_0_decoded_inst[31:20] == 12'h344; wire _csrWriteIllegal_T_99 = _issue_io_out_0_decoded_inst[31:20] == 12'h3A0; wire _csrWriteIllegal_T_101 = _issue_io_out_0_decoded_inst[31:20] == 12'h3B0; wire _csrWriteIllegal_T_103 = _issue_io_out_0_decoded_inst[31:20] == 12'h7A0; wire _csrWriteIllegal_T_105 = _issue_io_out_0_decoded_inst[31:20] == 12'h7A1; wire _csrWriteIllegal_T_107 = _issue_io_out_0_decoded_inst[31:20] == 12'h7A2; wire _csrWriteIllegal_T_109 = _issue_io_out_0_decoded_inst[31:20] == 12'h7A5; wire _csrWriteIllegal_T_111 = _issue_io_out_0_decoded_inst[31:20] == 12'h744; wire _csrWriteIllegal_T_113 = _issue_io_out_0_decoded_inst[31:20] == 12'h320; wire _csrWriteIllegal_T_115 = _issue_io_out_0_decoded_inst[31:20] == 12'hB02; wire _csrWriteIllegal_T_149 = _issue_io_out_0_decoded_inst[31:20] == 12'hF11; wire _csrWriteIllegal_T_150 = _issue_io_out_0_decoded_inst[31:20] == 12'hF12; wire _csrWriteIllegal_T_152 = _issue_io_out_0_decoded_inst[31:20] == 12'hF13; wire _csrWriteIllegal_T_154 = _issue_io_out_0_decoded_inst[31:20] == 12'hF14; wire _csrWriteIllegal_T_126 = _issue_io_out_0_decoded_inst[31:20] == 12'h100; wire _csrWriteIllegal_T_127 = _issue_io_out_0_decoded_inst[31:20] == 12'h104; wire _csrWriteIllegal_T_129 = _issue_io_out_0_decoded_inst[31:20] == 12'h105; wire _csrWriteIllegal_T_131 = _issue_io_out_0_decoded_inst[31:20] == 12'h140; wire _csrWriteIllegal_T_133 = _issue_io_out_0_decoded_inst[31:20] == 12'h106; wire _csrWriteIllegal_T_135 = _issue_io_out_0_decoded_inst[31:20] == 12'h141; wire _csrWriteIllegal_T_137 = _issue_io_out_0_decoded_inst[31:20] == 12'h142; wire _csrWriteIllegal_T_139 = _issue_io_out_0_decoded_inst[31:20] == 12'h143; wire _csrWriteIllegal_T_141 = _issue_io_out_0_decoded_inst[31:20] == 12'h144; wire _csrWriteIllegal_T_143 = _issue_io_out_0_decoded_inst[31:20] == 12'h180; wire _csrWriteIllegal_T_156 = _issue_io_out_0_decoded_inst[31:20] == 12'hC00; wire _csrWriteIllegal_T_157 = _issue_io_out_0_decoded_inst[31:20] == 12'hC01; wire _csrWriteIllegal_T_159 = _issue_io_out_0_decoded_inst[31:20] == 12'hC02; wire illegalInst = ~_issue_io_out_0_decoded_fetchException & (_issue_io_out_0_decoded_illegal | _issue_io_out_0_decoded_isMret & _illegalPriv_T_7 | _issue_io_out_0_decoded_isSret & _completeCause_1_T_6 | _issue_io_out_0_decoded_isSfenceVma & _completeCause_1_T_6 | csrReadFire_0 & _csr_io_readIllegal | _issue_io_out_0_decoded_isSystem & (|_issue_io_out_0_decoded_funct3) & ~(_issue_io_out_0_decoded_funct3[1] & _completeCsrValid_0_T_4) & ~((_csrWriteIllegal_T_76 | _csrWriteIllegal_T_77 | _csrWriteIllegal_T_79 | _csrWriteIllegal_T_81 | _csrWriteIllegal_T_83 | _csrWriteIllegal_T_85 | _csrWriteIllegal_T_87 | _csrWriteIllegal_T_89 | _csrWriteIllegal_T_91 | _csrWriteIllegal_T_93 | _csrWriteIllegal_T_95 | _csrWriteIllegal_T_97 | _csrWriteIllegal_T_99 | _csrWriteIllegal_T_101 | _csrWriteIllegal_T_103 | _csrWriteIllegal_T_105 | _csrWriteIllegal_T_107 | _csrWriteIllegal_T_109 | _csrWriteIllegal_T_111 | _csrWriteIllegal_T_113 | _csrWriteIllegal_T_115 | _csrWriteIllegal_T_149 | _csrWriteIllegal_T_150 | _csrWriteIllegal_T_152 | _csrWriteIllegal_T_154 | _csrWriteIllegal_T_126 | _csrWriteIllegal_T_127 | _csrWriteIllegal_T_129 | _csrWriteIllegal_T_131 | _csrWriteIllegal_T_133 | _csrWriteIllegal_T_135 | _csrWriteIllegal_T_137 | _csrWriteIllegal_T_139 | _csrWriteIllegal_T_141 | _csrWriteIllegal_T_143 | _csrWriteIllegal_T_156 | _csrWriteIllegal_T_157 | _csrWriteIllegal_T_159) & (_csrWriteIllegal_T_76 | _csrWriteIllegal_T_77 | _csrWriteIllegal_T_79 | _csrWriteIllegal_T_81 | _csrWriteIllegal_T_83 | _csrWriteIllegal_T_85 | _csrWriteIllegal_T_87 | _csrWriteIllegal_T_89 | _csrWriteIllegal_T_91 | _csrWriteIllegal_T_93 | _csrWriteIllegal_T_95 | _csrWriteIllegal_T_97 | _csrWriteIllegal_T_99 | _csrWriteIllegal_T_101 | _csrWriteIllegal_T_103 | _csrWriteIllegal_T_105 | _csrWriteIllegal_T_107 | _csrWriteIllegal_T_109 | _csrWriteIllegal_T_111 | _csrWriteIllegal_T_113 | _csrWriteIllegal_T_115 | _csrWriteIllegal_T_149 | _csrWriteIllegal_T_150 | _csrWriteIllegal_T_152 | _csrWriteIllegal_T_154 ? (&io_currentPriv) : ~(_csrWriteIllegal_T_126 | _csrWriteIllegal_T_127 | _csrWriteIllegal_T_129 | _csrWriteIllegal_T_131 | _csrWriteIllegal_T_133 | _csrWriteIllegal_T_135 | _csrWriteIllegal_T_137 | _csrWriteIllegal_T_139 | _csrWriteIllegal_T_141 | _csrWriteIllegal_T_143) | (|io_currentPriv)) & ~(_csrWriteIllegal_T_149 | _csrWriteIllegal_T_150 | _csrWriteIllegal_T_152 | _csrWriteIllegal_T_154 | _csrWriteIllegal_T_156 | _csrWriteIllegal_T_157 | _csrWriteIllegal_T_159))); wire [63:0] _dataAddr_T_1 = src1 + (_issue_io_out_0_decoded_isStore ? _issue_io_out_0_decoded_immS : _issue_io_out_0_decoded_immI); wire storeMisaligned = issueFire_0 & _issue_io_out_0_decoded_isStore & (|((_issue_io_out_0_decoded_memWidth == 3'h3 ? 3'h0 : _issue_io_out_0_decoded_memWidth == 3'h2 ? 3'h4 : _issue_io_out_0_decoded_memWidth == 3'h1 ? 3'h2 : {2'h0, _issue_io_out_0_decoded_memWidth == 3'h0}) - 3'h1 & _dataAddr_T_1[2:0])); wire loadFaultNow = lsuLoadReq & _lsu_io_respValid & (_lsu_io_misaligned | _lsu_io_pageFault); wire issueRaisesException = issueFire_0 & (_issue_io_out_0_decoded_fetchException | illegalInst | _issue_io_out_0_decoded_isEcall | _issue_io_out_0_decoded_isEbreak | _lq_io_violation | storeMisaligned | controlTargetMisaligned); wire loadRespHasFault = ~forwardPending & (_lsu_io_pageFault | _lsu_io_misaligned) | loadFaultNow; wire isLoadRespSlot = loadRespValid & ~loadRespHasFault; wire completeLoadResp = loadRespValid | loadFaultNow; wire completeStoreResp = storeCheckRespPending | storeCheckRespNow & issueFire_0 & _issue_io_out_0_decoded_isStore; wire completeValid_0 = issueFire_0 & ~_issue_io_out_0_decoded_isLoad & ~_issue_io_out_0_decoded_isStore | completeLoadResp | completeStoreResp; wire [5:0] completeIdx_0 = completeStoreResp ? (storeCheckRespPending ? storeCheckPendingRob : _issue_io_out_0_robIdx) : completeLoadResp ? (loadFaultNow ? sq_io_enqRobIdx : forwardPending ? forwardPendingRob : loadPendingRob) : _issue_io_out_0_robIdx; wire thisStoreCheckFault = completeStoreResp & storeCheckFault; wire completeException_0 = issueRaisesException | completeLoadResp & loadRespHasFault | thisStoreCheckFault; wire _completeBadAddr_0_T_3 = issueFire_0 & _issue_io_out_0_decoded_fetchException; wire _completeBadAddr_0_T_4 = issueFire_0 & illegalInst; wire [63:0] completeCause_0 = thisStoreCheckFault | completeLoadResp & loadRespHasFault ? _lsu_io_faultCause : _completeBadAddr_0_T_3 ? _issue_io_out_0_decoded_fetchExceptionCause : {56'h0, issueFire_0 & _issue_io_out_0_decoded_isEbreak ? 8'h3 : issueFire_0 & _issue_io_out_0_decoded_isEcall ? _GEN[io_currentPriv] : storeMisaligned ? 8'h6 : controlTargetMisaligned ? 8'h0 : {6'h0, _completeBadAddr_0_T_4, 1'h0}}; wire [63:0] completeRedirectPc_0 = _issue_io_out_0_decoded_isEcall | _issue_io_out_0_decoded_isEbreak ? _csr_io_trapVector : _issue_io_out_0_decoded_isXret ? (_issue_io_out_0_decoded_isMret ? _csr_io_mepc : _csr_io_sepc) : _issue_io_out_0_decoded_isWfi ? _completeRedirectPc_0_T_2 : _issue_io_out_0_decoded_isJal ? _jalTarget_T : _issue_io_out_0_decoded_isJalr ? jalrTarget : _completeMispredict_0_T_5 ? _branchTarget_T : _completeRedirectPc_0_T_2; wire [63:0] src1_1 = wakeupReg_0_valid & (|wakeupReg_0_phys) & wakeupReg_0_phys == _issue_io_out_1_prs1 ? wakeupReg_0_data : wakeupReg_1_valid & (|wakeupReg_1_phys) & wakeupReg_1_phys == _issue_io_out_1_prs1 ? wakeupReg_1_data : _prf_io_rdata_2; wire [63:0] _branchTarget_T_1 = _issue_io_out_1_decoded_pc + _issue_io_out_1_decoded_immB; wire [63:0] _jalTarget_T_1 = _issue_io_out_1_decoded_pc + _issue_io_out_1_decoded_immJ; wire [63:0] _jalrTarget_T_3 = src1_1 + _issue_io_out_1_decoded_immI; wire [63:0] jalrTarget_1 = {_jalrTarget_T_3[63:1], 1'h0}; wire [63:0] controlTarget_1 = _issue_io_out_1_decoded_isJal ? _jalTarget_T_1 : _issue_io_out_1_decoded_isJalr ? jalrTarget_1 : _branchTarget_T_1; wire _completeMispredict_1_T = _issue_io_out_1_decoded_isJal | _issue_io_out_1_decoded_isJalr; wire _completeMispredict_1_T_5 = _issue_io_out_1_decoded_isBranch & _exec_1_io_branchTaken; wire controlTargetMisaligned_1 = issueFire_1 & (_completeMispredict_1_T | _completeMispredict_1_T_5) & (|(controlTarget_1[1:0])); wire [63:0] _completeRedirectPc_1_T_2 = _issue_io_out_1_decoded_pc + 64'h4; wire _completeCsrValid_1_T_4 = _issue_io_out_1_decoded_rs1 == 5'h0; wire _csrWriteIllegal_T_241 = _issue_io_out_1_decoded_inst[31:20] == 12'h300; wire _csrWriteIllegal_T_242 = _issue_io_out_1_decoded_inst[31:20] == 12'h301; wire _csrWriteIllegal_T_244 = _issue_io_out_1_decoded_inst[31:20] == 12'h302; wire _csrWriteIllegal_T_246 = _issue_io_out_1_decoded_inst[31:20] == 12'h303; wire _csrWriteIllegal_T_248 = _issue_io_out_1_decoded_inst[31:20] == 12'h304; wire _csrWriteIllegal_T_250 = _issue_io_out_1_decoded_inst[31:20] == 12'h305; wire _csrWriteIllegal_T_252 = _issue_io_out_1_decoded_inst[31:20] == 12'h306; wire _csrWriteIllegal_T_254 = _issue_io_out_1_decoded_inst[31:20] == 12'h340; wire _csrWriteIllegal_T_256 = _issue_io_out_1_decoded_inst[31:20] == 12'h341; wire _csrWriteIllegal_T_258 = _issue_io_out_1_decoded_inst[31:20] == 12'h342; wire _csrWriteIllegal_T_260 = _issue_io_out_1_decoded_inst[31:20] == 12'h343; wire _csrWriteIllegal_T_262 = _issue_io_out_1_decoded_inst[31:20] == 12'h344; wire _csrWriteIllegal_T_264 = _issue_io_out_1_decoded_inst[31:20] == 12'h3A0; wire _csrWriteIllegal_T_266 = _issue_io_out_1_decoded_inst[31:20] == 12'h3B0; wire _csrWriteIllegal_T_268 = _issue_io_out_1_decoded_inst[31:20] == 12'h7A0; wire _csrWriteIllegal_T_270 = _issue_io_out_1_decoded_inst[31:20] == 12'h7A1; wire _csrWriteIllegal_T_272 = _issue_io_out_1_decoded_inst[31:20] == 12'h7A2; wire _csrWriteIllegal_T_274 = _issue_io_out_1_decoded_inst[31:20] == 12'h7A5; wire _csrWriteIllegal_T_276 = _issue_io_out_1_decoded_inst[31:20] == 12'h744; wire _csrWriteIllegal_T_278 = _issue_io_out_1_decoded_inst[31:20] == 12'h320; wire _csrWriteIllegal_T_280 = _issue_io_out_1_decoded_inst[31:20] == 12'hB02; wire _csrWriteIllegal_T_314 = _issue_io_out_1_decoded_inst[31:20] == 12'hF11; wire _csrWriteIllegal_T_315 = _issue_io_out_1_decoded_inst[31:20] == 12'hF12; wire _csrWriteIllegal_T_317 = _issue_io_out_1_decoded_inst[31:20] == 12'hF13; wire _csrWriteIllegal_T_319 = _issue_io_out_1_decoded_inst[31:20] == 12'hF14; wire _csrWriteIllegal_T_291 = _issue_io_out_1_decoded_inst[31:20] == 12'h100; wire _csrWriteIllegal_T_292 = _issue_io_out_1_decoded_inst[31:20] == 12'h104; wire _csrWriteIllegal_T_294 = _issue_io_out_1_decoded_inst[31:20] == 12'h105; wire _csrWriteIllegal_T_296 = _issue_io_out_1_decoded_inst[31:20] == 12'h140; wire _csrWriteIllegal_T_298 = _issue_io_out_1_decoded_inst[31:20] == 12'h106; wire _csrWriteIllegal_T_300 = _issue_io_out_1_decoded_inst[31:20] == 12'h141; wire _csrWriteIllegal_T_302 = _issue_io_out_1_decoded_inst[31:20] == 12'h142; wire _csrWriteIllegal_T_304 = _issue_io_out_1_decoded_inst[31:20] == 12'h143; wire _csrWriteIllegal_T_306 = _issue_io_out_1_decoded_inst[31:20] == 12'h144; wire _csrWriteIllegal_T_308 = _issue_io_out_1_decoded_inst[31:20] == 12'h180; wire _csrWriteIllegal_T_321 = _issue_io_out_1_decoded_inst[31:20] == 12'hC00; wire _csrWriteIllegal_T_322 = _issue_io_out_1_decoded_inst[31:20] == 12'hC01; wire _csrWriteIllegal_T_324 = _issue_io_out_1_decoded_inst[31:20] == 12'hC02; wire illegalInst_1 = ~_issue_io_out_1_decoded_fetchException & (_issue_io_out_1_decoded_illegal | _issue_io_out_1_decoded_isMret & _illegalPriv_T_7 | _issue_io_out_1_decoded_isSret & _completeCause_1_T_6 | _issue_io_out_1_decoded_isSfenceVma & _completeCause_1_T_6 | csrReadReq_1 & issue_io_outReady_1 & _csr_io_readIllegal | _issue_io_out_1_decoded_isSystem & (|_issue_io_out_1_decoded_funct3) & ~(_issue_io_out_1_decoded_funct3[1] & _completeCsrValid_1_T_4) & ~((_csrWriteIllegal_T_241 | _csrWriteIllegal_T_242 | _csrWriteIllegal_T_244 | _csrWriteIllegal_T_246 | _csrWriteIllegal_T_248 | _csrWriteIllegal_T_250 | _csrWriteIllegal_T_252 | _csrWriteIllegal_T_254 | _csrWriteIllegal_T_256 | _csrWriteIllegal_T_258 | _csrWriteIllegal_T_260 | _csrWriteIllegal_T_262 | _csrWriteIllegal_T_264 | _csrWriteIllegal_T_266 | _csrWriteIllegal_T_268 | _csrWriteIllegal_T_270 | _csrWriteIllegal_T_272 | _csrWriteIllegal_T_274 | _csrWriteIllegal_T_276 | _csrWriteIllegal_T_278 | _csrWriteIllegal_T_280 | _csrWriteIllegal_T_314 | _csrWriteIllegal_T_315 | _csrWriteIllegal_T_317 | _csrWriteIllegal_T_319 | _csrWriteIllegal_T_291 | _csrWriteIllegal_T_292 | _csrWriteIllegal_T_294 | _csrWriteIllegal_T_296 | _csrWriteIllegal_T_298 | _csrWriteIllegal_T_300 | _csrWriteIllegal_T_302 | _csrWriteIllegal_T_304 | _csrWriteIllegal_T_306 | _csrWriteIllegal_T_308 | _csrWriteIllegal_T_321 | _csrWriteIllegal_T_322 | _csrWriteIllegal_T_324) & (_csrWriteIllegal_T_241 | _csrWriteIllegal_T_242 | _csrWriteIllegal_T_244 | _csrWriteIllegal_T_246 | _csrWriteIllegal_T_248 | _csrWriteIllegal_T_250 | _csrWriteIllegal_T_252 | _csrWriteIllegal_T_254 | _csrWriteIllegal_T_256 | _csrWriteIllegal_T_258 | _csrWriteIllegal_T_260 | _csrWriteIllegal_T_262 | _csrWriteIllegal_T_264 | _csrWriteIllegal_T_266 | _csrWriteIllegal_T_268 | _csrWriteIllegal_T_270 | _csrWriteIllegal_T_272 | _csrWriteIllegal_T_274 | _csrWriteIllegal_T_276 | _csrWriteIllegal_T_278 | _csrWriteIllegal_T_280 | _csrWriteIllegal_T_314 | _csrWriteIllegal_T_315 | _csrWriteIllegal_T_317 | _csrWriteIllegal_T_319 ? (&io_currentPriv) : ~(_csrWriteIllegal_T_291 | _csrWriteIllegal_T_292 | _csrWriteIllegal_T_294 | _csrWriteIllegal_T_296 | _csrWriteIllegal_T_298 | _csrWriteIllegal_T_300 | _csrWriteIllegal_T_302 | _csrWriteIllegal_T_304 | _csrWriteIllegal_T_306 | _csrWriteIllegal_T_308) | (|io_currentPriv)) & ~(_csrWriteIllegal_T_314 | _csrWriteIllegal_T_315 | _csrWriteIllegal_T_317 | _csrWriteIllegal_T_319 | _csrWriteIllegal_T_321 | _csrWriteIllegal_T_322 | _csrWriteIllegal_T_324))); wire [63:0] _dataAddr_T_3 = src1_1 + (_issue_io_out_1_decoded_isStore ? _issue_io_out_1_decoded_immS : _issue_io_out_1_decoded_immI); wire storeMisaligned_1 = issueFire_1 & _issue_io_out_1_decoded_isStore & (|((_issue_io_out_1_decoded_memWidth == 3'h3 ? 3'h0 : _issue_io_out_1_decoded_memWidth == 3'h2 ? 3'h4 : _issue_io_out_1_decoded_memWidth == 3'h1 ? 3'h2 : {2'h0, _issue_io_out_1_decoded_memWidth == 3'h0}) - 3'h1 & _dataAddr_T_3[2:0])); wire issueRaisesException_1 = issueFire_1 & (_issue_io_out_1_decoded_fetchException | illegalInst_1 | _issue_io_out_1_decoded_isEcall | _issue_io_out_1_decoded_isEbreak | _lq_io_violation | storeMisaligned_1 | controlTargetMisaligned_1); wire completeStoreResp_1 = storeCheckRespNow & issueFire_1 & _issue_io_out_1_decoded_isStore; wire completeValid_1 = issueFire_1 & ~_issue_io_out_1_decoded_isLoad & ~_issue_io_out_1_decoded_isStore | completeStoreResp_1; wire [5:0] completeIdx_1 = completeStoreResp_1 & storeCheckRespPending ? storeCheckPendingRob : _issue_io_out_1_robIdx; wire thisStoreCheckFault_1 = completeStoreResp_1 & storeCheckFault; wire completeException_1 = issueRaisesException_1 | thisStoreCheckFault_1; wire _completeBadAddr_1_T_3 = issueFire_1 & _issue_io_out_1_decoded_fetchException; wire _completeBadAddr_1_T_4 = issueFire_1 & illegalInst_1; wire [63:0] completeCause_1 = thisStoreCheckFault_1 ? _lsu_io_faultCause : _completeBadAddr_1_T_3 ? _issue_io_out_1_decoded_fetchExceptionCause : {56'h0, issueFire_1 & _issue_io_out_1_decoded_isEbreak ? 8'h3 : issueFire_1 & _issue_io_out_1_decoded_isEcall ? _GEN[io_currentPriv] : storeMisaligned_1 ? 8'h6 : controlTargetMisaligned_1 ? 8'h0 : {6'h0, _completeBadAddr_1_T_4, 1'h0}}; wire [63:0] completeRedirectPc_1 = _issue_io_out_1_decoded_isEcall | _issue_io_out_1_decoded_isEbreak ? _csr_io_trapVector : _issue_io_out_1_decoded_isXret ? (_issue_io_out_1_decoded_isMret ? _csr_io_mepc : _csr_io_sepc) : _issue_io_out_1_decoded_isWfi ? _completeRedirectPc_1_T_2 : _issue_io_out_1_decoded_isJal ? _jalTarget_T_1 : _issue_io_out_1_decoded_isJalr ? jalrTarget_1 : _completeMispredict_1_T_5 ? _branchTarget_T_1 : _completeRedirectPc_1_T_2; wire [63:0] xretRedirectPc = _commit_io_xretIsMret ? _csr_io_mepc : _csr_io_sepc; always @(posedge clock) begin automatic logic [5:0] _GEN_4; automatic logic forwardLoad; automatic logic _GEN_5; automatic logic _GEN_6; automatic logic _GEN_7; _GEN_4 = memIssue_0 ? _issue_io_out_0_prd : _issue_io_out_1_prd; forwardLoad = loadEnq & sqForwardValid; _GEN_5 = loadEnq & ~sqForwardValid; _GEN_6 = forwardLoad | forwardPending; _GEN_7 = storeEnq & ~storeCheckRespNow; if (reset) begin wakeupReg_0_valid <= 1'h0; wakeupReg_0_phys <= 6'h0; wakeupReg_0_data <= 64'h0; wakeupReg_1_valid <= 1'h0; wakeupReg_1_phys <= 6'h0; wakeupReg_1_data <= 64'h0; loadPending <= 1'h0; forwardPending <= 1'h0; storeCheckPending <= 1'h0; end else begin automatic logic _GEN_8 = ~_commit_io_flush & storeCheckPending; wakeupReg_0_valid <= _wb_0_io_wen; wakeupReg_0_phys <= _wb_0_io_waddr; wakeupReg_0_data <= _wb_0_io_wdata; wakeupReg_1_valid <= _wb_1_io_wen; wakeupReg_1_phys <= _wb_1_io_waddr; wakeupReg_1_data <= _wb_1_io_wdata; loadPending <= ~_commit_io_flush & (_GEN_6 ? loadPending : _GEN_5 | ~loadRespValid & loadPending); forwardPending <= ~_commit_io_flush & forwardLoad; storeCheckPending <= _commit_io_flush ? _GEN_8 : ~storeCheckRespPending & (_GEN_7 | _GEN_8); end if (_commit_io_flush | _GEN_6 | ~_GEN_5) begin end else begin loadPendingRob <= sq_io_enqRobIdx; loadPendingPhys <= _GEN_4; loadPendingLq <= _lq_io_enqIdx; end if (_commit_io_flush | ~forwardLoad) begin end else begin forwardPendingRob <= sq_io_enqRobIdx; forwardPendingPhys <= _GEN_4; forwardPendingLq <= _lq_io_enqIdx; forwardPendingData <= sq_io_size == 3'h3 ? _sq_io_forwardData : sq_io_size == 3'h2 ? {_GEN_0 ? {32{_sq_io_forwardData[31]}} : 32'h0, _sq_io_forwardData[31:0]} : sq_io_size == 3'h1 ? {_GEN_0 ? {48{_sq_io_forwardData[15]}} : 48'h0, _sq_io_forwardData[15:0]} : sq_io_size == 3'h0 ? {_GEN_0 ? {56{_sq_io_forwardData[7]}} : 56'h0, _sq_io_forwardData[7:0]} : _sq_io_forwardData; end if (_commit_io_flush | storeCheckRespPending | ~_GEN_7) begin end else storeCheckPendingRob <= sq_io_enqRobIdx; end // always @(posedge) RenameStage rename ( .clock (clock), .reset (reset), .io_inValid_0 (io_decodeValid_0 & _issue_io_inReady_0), .io_inValid_1 (io_decodeValid_1 & _issue_io_inReady_1), .io_in_0_pc (io_decode_0_pc), .io_in_0_inst (io_decode_0_inst), .io_in_0_rs1 (io_decode_0_rs1), .io_in_0_rs2 (io_decode_0_rs2), .io_in_0_rd (io_decode_0_rd), .io_in_0_funct3 (io_decode_0_funct3), .io_in_0_immI (io_decode_0_immI), .io_in_0_immS (io_decode_0_immS), .io_in_0_immB (io_decode_0_immB), .io_in_0_immU (io_decode_0_immU), .io_in_0_immJ (io_decode_0_immJ), .io_in_0_opClass (io_decode_0_opClass), .io_in_0_aluFn (io_decode_0_aluFn), .io_in_0_memWidth (io_decode_0_memWidth), .io_in_0_memSigned (io_decode_0_memSigned), .io_in_0_isLoad (io_decode_0_isLoad), .io_in_0_isStore (io_decode_0_isStore), .io_in_0_isBranch (io_decode_0_isBranch), .io_in_0_isJal (io_decode_0_isJal), .io_in_0_isJalr (io_decode_0_isJalr), .io_in_0_isLui (io_decode_0_isLui), .io_in_0_isAuipc (io_decode_0_isAuipc), .io_in_0_isOpImm (io_decode_0_isOpImm), .io_in_0_isWord (io_decode_0_isWord), .io_in_0_isSystem (io_decode_0_isSystem), .io_in_0_isFenceI (io_decode_0_isFenceI), .io_in_0_isEcall (io_decode_0_isEcall), .io_in_0_isEbreak (io_decode_0_isEbreak), .io_in_0_isMret (io_decode_0_isMret), .io_in_0_isSret (io_decode_0_isSret), .io_in_0_isSfenceVma (io_decode_0_isSfenceVma), .io_in_0_isXret (io_decode_0_isXret), .io_in_0_isWfi (io_decode_0_isWfi), .io_in_0_isAmo (io_decode_0_isAmo), .io_in_0_amoOp (io_decode_0_amoOp), .io_in_0_writesRd (io_decode_0_writesRd), .io_in_0_illegal (io_decode_0_illegal), .io_in_0_fetchException (io_decode_0_fetchException), .io_in_0_fetchExceptionCause (io_decode_0_fetchExceptionCause), .io_in_0_fetchExceptionTval (io_decode_0_fetchExceptionTval), .io_in_1_pc (io_decode_1_pc), .io_in_1_inst (io_decode_1_inst), .io_in_1_rs1 (io_decode_1_rs1), .io_in_1_rs2 (io_decode_1_rs2), .io_in_1_rd (io_decode_1_rd), .io_in_1_funct3 (io_decode_1_funct3), .io_in_1_immI (io_decode_1_immI), .io_in_1_immS (io_decode_1_immS), .io_in_1_immB (io_decode_1_immB), .io_in_1_immU (io_decode_1_immU), .io_in_1_immJ (io_decode_1_immJ), .io_in_1_opClass (io_decode_1_opClass), .io_in_1_aluFn (io_decode_1_aluFn), .io_in_1_memWidth (io_decode_1_memWidth), .io_in_1_memSigned (io_decode_1_memSigned), .io_in_1_isLoad (io_decode_1_isLoad), .io_in_1_isStore (io_decode_1_isStore), .io_in_1_isBranch (io_decode_1_isBranch), .io_in_1_isJal (io_decode_1_isJal), .io_in_1_isJalr (io_decode_1_isJalr), .io_in_1_isLui (io_decode_1_isLui), .io_in_1_isAuipc (io_decode_1_isAuipc), .io_in_1_isOpImm (io_decode_1_isOpImm), .io_in_1_isWord (io_decode_1_isWord), .io_in_1_isSystem (io_decode_1_isSystem), .io_in_1_isFenceI (io_decode_1_isFenceI), .io_in_1_isEcall (io_decode_1_isEcall), .io_in_1_isEbreak (io_decode_1_isEbreak), .io_in_1_isMret (io_decode_1_isMret), .io_in_1_isSret (io_decode_1_isSret), .io_in_1_isSfenceVma (io_decode_1_isSfenceVma), .io_in_1_isXret (io_decode_1_isXret), .io_in_1_isWfi (io_decode_1_isWfi), .io_in_1_isAmo (io_decode_1_isAmo), .io_in_1_amoOp (io_decode_1_amoOp), .io_in_1_writesRd (io_decode_1_writesRd), .io_in_1_illegal (io_decode_1_illegal), .io_in_1_fetchException (io_decode_1_fetchException), .io_in_1_fetchExceptionCause (io_decode_1_fetchExceptionCause), .io_in_1_fetchExceptionTval (io_decode_1_fetchExceptionTval), .io_outValid_0 (_rename_io_outValid_0), .io_outValid_1 (_rename_io_outValid_1), .io_out_0_decoded_pc (_rename_io_out_0_decoded_pc), .io_out_0_decoded_inst (_rename_io_out_0_decoded_inst), .io_out_0_decoded_rs1 (_rename_io_out_0_decoded_rs1), .io_out_0_decoded_rs2 (_rename_io_out_0_decoded_rs2), .io_out_0_decoded_funct3 (_rename_io_out_0_decoded_funct3), .io_out_0_decoded_immI (_rename_io_out_0_decoded_immI), .io_out_0_decoded_immS (_rename_io_out_0_decoded_immS), .io_out_0_decoded_immB (_rename_io_out_0_decoded_immB), .io_out_0_decoded_immU (_rename_io_out_0_decoded_immU), .io_out_0_decoded_immJ (_rename_io_out_0_decoded_immJ), .io_out_0_decoded_aluFn (_rename_io_out_0_decoded_aluFn), .io_out_0_decoded_memWidth (_rename_io_out_0_decoded_memWidth), .io_out_0_decoded_memSigned (_rename_io_out_0_decoded_memSigned), .io_out_0_decoded_isLoad (_rename_io_out_0_decoded_isLoad), .io_out_0_decoded_isStore (_rename_io_out_0_decoded_isStore), .io_out_0_decoded_isBranch (_rename_io_out_0_decoded_isBranch), .io_out_0_decoded_isJal (_rename_io_out_0_decoded_isJal), .io_out_0_decoded_isJalr (_rename_io_out_0_decoded_isJalr), .io_out_0_decoded_isLui (_rename_io_out_0_decoded_isLui), .io_out_0_decoded_isAuipc (_rename_io_out_0_decoded_isAuipc), .io_out_0_decoded_isOpImm (_rename_io_out_0_decoded_isOpImm), .io_out_0_decoded_isWord (_rename_io_out_0_decoded_isWord), .io_out_0_decoded_isSystem (_rename_io_out_0_decoded_isSystem), .io_out_0_decoded_isFenceI (_rename_io_out_0_decoded_isFenceI), .io_out_0_decoded_isEcall (_rename_io_out_0_decoded_isEcall), .io_out_0_decoded_isEbreak (_rename_io_out_0_decoded_isEbreak), .io_out_0_decoded_isMret (_rename_io_out_0_decoded_isMret), .io_out_0_decoded_isSret (_rename_io_out_0_decoded_isSret), .io_out_0_decoded_isSfenceVma (_rename_io_out_0_decoded_isSfenceVma), .io_out_0_decoded_isXret (_rename_io_out_0_decoded_isXret), .io_out_0_decoded_isWfi (_rename_io_out_0_decoded_isWfi), .io_out_0_decoded_isAmo (_rename_io_out_0_decoded_isAmo), .io_out_0_decoded_amoOp (_rename_io_out_0_decoded_amoOp), .io_out_0_decoded_writesRd (_rename_io_out_0_decoded_writesRd), .io_out_0_decoded_illegal (_rename_io_out_0_decoded_illegal), .io_out_0_decoded_fetchException (_rename_io_out_0_decoded_fetchException), .io_out_0_decoded_fetchExceptionCause (_rename_io_out_0_decoded_fetchExceptionCause), .io_out_0_decoded_fetchExceptionTval (_rename_io_out_0_decoded_fetchExceptionTval), .io_out_0_prs1 (_rename_io_out_0_prs1), .io_out_0_prs2 (_rename_io_out_0_prs2), .io_out_0_src1Ready (_rename_io_out_0_src1Ready), .io_out_0_src2Ready (_rename_io_out_0_src2Ready), .io_out_0_prd (_rename_io_out_0_prd), .io_out_0_robIdx (_rename_io_out_0_robIdx), .io_out_1_decoded_pc (_rename_io_out_1_decoded_pc), .io_out_1_decoded_inst (_rename_io_out_1_decoded_inst), .io_out_1_decoded_rs1 (_rename_io_out_1_decoded_rs1), .io_out_1_decoded_rs2 (_rename_io_out_1_decoded_rs2), .io_out_1_decoded_funct3 (_rename_io_out_1_decoded_funct3), .io_out_1_decoded_immI (_rename_io_out_1_decoded_immI), .io_out_1_decoded_immS (_rename_io_out_1_decoded_immS), .io_out_1_decoded_immB (_rename_io_out_1_decoded_immB), .io_out_1_decoded_immU (_rename_io_out_1_decoded_immU), .io_out_1_decoded_immJ (_rename_io_out_1_decoded_immJ), .io_out_1_decoded_aluFn (_rename_io_out_1_decoded_aluFn), .io_out_1_decoded_memWidth (_rename_io_out_1_decoded_memWidth), .io_out_1_decoded_memSigned (_rename_io_out_1_decoded_memSigned), .io_out_1_decoded_isLoad (_rename_io_out_1_decoded_isLoad), .io_out_1_decoded_isStore (_rename_io_out_1_decoded_isStore), .io_out_1_decoded_isBranch (_rename_io_out_1_decoded_isBranch), .io_out_1_decoded_isJal (_rename_io_out_1_decoded_isJal), .io_out_1_decoded_isJalr (_rename_io_out_1_decoded_isJalr), .io_out_1_decoded_isLui (_rename_io_out_1_decoded_isLui), .io_out_1_decoded_isAuipc (_rename_io_out_1_decoded_isAuipc), .io_out_1_decoded_isOpImm (_rename_io_out_1_decoded_isOpImm), .io_out_1_decoded_isWord (_rename_io_out_1_decoded_isWord), .io_out_1_decoded_isSystem (_rename_io_out_1_decoded_isSystem), .io_out_1_decoded_isFenceI (_rename_io_out_1_decoded_isFenceI), .io_out_1_decoded_isEcall (_rename_io_out_1_decoded_isEcall), .io_out_1_decoded_isEbreak (_rename_io_out_1_decoded_isEbreak), .io_out_1_decoded_isMret (_rename_io_out_1_decoded_isMret), .io_out_1_decoded_isSret (_rename_io_out_1_decoded_isSret), .io_out_1_decoded_isSfenceVma (_rename_io_out_1_decoded_isSfenceVma), .io_out_1_decoded_isXret (_rename_io_out_1_decoded_isXret), .io_out_1_decoded_isWfi (_rename_io_out_1_decoded_isWfi), .io_out_1_decoded_isAmo (_rename_io_out_1_decoded_isAmo), .io_out_1_decoded_amoOp (_rename_io_out_1_decoded_amoOp), .io_out_1_decoded_writesRd (_rename_io_out_1_decoded_writesRd), .io_out_1_decoded_illegal (_rename_io_out_1_decoded_illegal), .io_out_1_decoded_fetchException (_rename_io_out_1_decoded_fetchException), .io_out_1_decoded_fetchExceptionCause (_rename_io_out_1_decoded_fetchExceptionCause), .io_out_1_decoded_fetchExceptionTval (_rename_io_out_1_decoded_fetchExceptionTval), .io_out_1_prs1 (_rename_io_out_1_prs1), .io_out_1_prs2 (_rename_io_out_1_prs2), .io_out_1_src1Ready (_rename_io_out_1_src1Ready), .io_out_1_src2Ready (_rename_io_out_1_src2Ready), .io_out_1_prd (_rename_io_out_1_prd), .io_out_1_robIdx (_rename_io_out_1_robIdx), .io_canAccept (_rename_io_canAccept), .io_wbValid_0 (_wb_0_io_wen), .io_wbValid_1 (_wb_1_io_wen), .io_wbPhys_0 (_wb_0_io_waddr), .io_wbPhys_1 (_wb_1_io_waddr), .io_completeValid_0 (completeValid_0), .io_completeValid_1 (completeValid_1), .io_completeIdx_0 (completeIdx_0), .io_completeIdx_1 (completeIdx_1), .io_completeException_0 (completeException_0), .io_completeException_1 (completeException_1), .io_completeCause_0 (completeCause_0), .io_completeCause_1 (completeCause_1), .io_completeBadAddr_0 (thisStoreCheckFault | completeLoadResp & loadRespHasFault ? _lsu_io_faultAddr : storeMisaligned ? _dataAddr_T_1 : _completeBadAddr_0_T_3 ? _issue_io_out_0_decoded_fetchExceptionTval : controlTargetMisaligned ? controlTarget : _completeBadAddr_0_T_4 ? {32'h0, _issue_io_out_0_decoded_inst} : 64'h0), .io_completeBadAddr_1 (thisStoreCheckFault_1 ? _lsu_io_faultAddr : storeMisaligned_1 ? _dataAddr_T_3 : _completeBadAddr_1_T_3 ? _issue_io_out_1_decoded_fetchExceptionTval : controlTargetMisaligned_1 ? controlTarget_1 : _completeBadAddr_1_T_4 ? {32'h0, _issue_io_out_1_decoded_inst} : 64'h0), .io_completeMispredict_0 (issueFire_0 & (_completeMispredict_0_T | _issue_io_out_0_decoded_isXret | _issue_io_out_0_decoded_isFenceI | _issue_io_out_0_decoded_isSfenceVma | _issue_io_out_0_decoded_isWfi | _completeMispredict_0_T_5)), .io_completeMispredict_1 (issueFire_1 & (_completeMispredict_1_T | _issue_io_out_1_decoded_isXret | _issue_io_out_1_decoded_isFenceI | _issue_io_out_1_decoded_isSfenceVma | _issue_io_out_1_decoded_isWfi | _completeMispredict_1_T_5)), .io_completeRedirectPc_0 (completeRedirectPc_0), .io_completeRedirectPc_1 (completeRedirectPc_1), .io_completeCsrValid_0 (issueFire_0 & _issue_io_out_0_decoded_isSystem & (|_issue_io_out_0_decoded_funct3) & ~(_issue_io_out_0_decoded_funct3[1] & _completeCsrValid_0_T_4) & ~illegalInst), .io_completeCsrValid_1 (issueFire_1 & _issue_io_out_1_decoded_isSystem & (|_issue_io_out_1_decoded_funct3) & ~(_issue_io_out_1_decoded_funct3[1] & _completeCsrValid_1_T_4) & ~illegalInst_1), .io_completeCsrAddr_0 (_issue_io_out_0_decoded_inst[31:20]), .io_completeCsrAddr_1 (_issue_io_out_1_decoded_inst[31:20]), .io_completeCsrCmd_0 (_issue_io_out_0_decoded_funct3), .io_completeCsrCmd_1 (_issue_io_out_1_decoded_funct3), .io_completeCsrRs1_0 (src1), .io_completeCsrRs1_1 (src1_1), .io_completeCsrZimm_0 (_issue_io_out_0_decoded_rs1), .io_completeCsrZimm_1 (_issue_io_out_1_decoded_rs1), .io_completeFenceI_0 (issueFire_0 & _issue_io_out_0_decoded_isFenceI), .io_completeFenceI_1 (issueFire_1 & _issue_io_out_1_decoded_isFenceI), .io_completeSfenceVma_0 (issueFire_0 & _issue_io_out_0_decoded_isSfenceVma), .io_completeSfenceVma_1 (issueFire_1 & _issue_io_out_1_decoded_isSfenceVma), .io_completeXret_0 (issueFire_0 & _issue_io_out_0_decoded_isXret), .io_completeXret_1 (issueFire_1 & _issue_io_out_1_decoded_isXret), .io_completeXretIsMret_0 (issueFire_0 & _issue_io_out_0_decoded_isMret), .io_completeXretIsMret_1 (issueFire_1 & _issue_io_out_1_decoded_isMret), .io_commitReady_0 (_commit_io_commitReady_0), .io_commitReady_1 (_commit_io_commitReady_1), .io_commitValid_0 (_rename_io_commitValid_0), .io_commitValid_1 (_rename_io_commitValid_1), .io_commitEntry_0_valid (_rename_io_commitEntry_0_valid), .io_commitEntry_0_robIdx (_rename_io_commitEntry_0_robIdx), .io_commitEntry_0_pc (_rename_io_commitEntry_0_pc), .io_commitEntry_0_archDest (_rename_io_commitEntry_0_archDest), .io_commitEntry_0_writesDest (_rename_io_commitEntry_0_writesDest), .io_commitEntry_0_opClass (_rename_io_commitEntry_0_opClass), .io_commitEntry_0_dest (_rename_io_commitEntry_0_dest), .io_commitEntry_0_oldDest (_rename_io_commitEntry_0_oldDest), .io_commitEntry_0_exception (_rename_io_commitEntry_0_exception), .io_commitEntry_0_exceptionCause (_rename_io_commitEntry_0_exceptionCause), .io_commitEntry_0_badAddr (_rename_io_commitEntry_0_badAddr), .io_commitEntry_0_branchMispredict (_rename_io_commitEntry_0_branchMispredict), .io_commitEntry_0_redirectPc (_rename_io_commitEntry_0_redirectPc), .io_commitEntry_0_csrValid (_rename_io_commitEntry_0_csrValid), .io_commitEntry_0_csrAddr (_rename_io_commitEntry_0_csrAddr), .io_commitEntry_0_csrCmd (_rename_io_commitEntry_0_csrCmd), .io_commitEntry_0_csrRs1 (_rename_io_commitEntry_0_csrRs1), .io_commitEntry_0_csrZimm (_rename_io_commitEntry_0_csrZimm), .io_commitEntry_0_fenceI (_rename_io_commitEntry_0_fenceI), .io_commitEntry_0_sfenceVma (_rename_io_commitEntry_0_sfenceVma), .io_commitEntry_0_xret (_rename_io_commitEntry_0_xret), .io_commitEntry_0_xretIsMret (_rename_io_commitEntry_0_xretIsMret), .io_commitEntry_1_robIdx (_rename_io_commitEntry_1_robIdx), .io_commitEntry_1_pc (_rename_io_commitEntry_1_pc), .io_commitEntry_1_archDest (_rename_io_commitEntry_1_archDest), .io_commitEntry_1_writesDest (_rename_io_commitEntry_1_writesDest), .io_commitEntry_1_opClass (_rename_io_commitEntry_1_opClass), .io_commitEntry_1_dest (_rename_io_commitEntry_1_dest), .io_commitEntry_1_oldDest (_rename_io_commitEntry_1_oldDest), .io_commitEntry_1_exception (_rename_io_commitEntry_1_exception), .io_commitEntry_1_exceptionCause (_rename_io_commitEntry_1_exceptionCause), .io_commitEntry_1_badAddr (_rename_io_commitEntry_1_badAddr), .io_commitEntry_1_branchMispredict (_rename_io_commitEntry_1_branchMispredict), .io_commitEntry_1_redirectPc (_rename_io_commitEntry_1_redirectPc), .io_commitEntry_1_csrValid (_rename_io_commitEntry_1_csrValid), .io_commitEntry_1_csrAddr (_rename_io_commitEntry_1_csrAddr), .io_commitEntry_1_csrCmd (_rename_io_commitEntry_1_csrCmd), .io_commitEntry_1_csrRs1 (_rename_io_commitEntry_1_csrRs1), .io_commitEntry_1_csrZimm (_rename_io_commitEntry_1_csrZimm), .io_commitEntry_1_fenceI (_rename_io_commitEntry_1_fenceI), .io_commitEntry_1_sfenceVma (_rename_io_commitEntry_1_sfenceVma), .io_commitEntry_1_xret (_rename_io_commitEntry_1_xret), .io_commitEntry_1_xretIsMret (_rename_io_commitEntry_1_xretIsMret), .io_commitMapValid_0 (_commit_io_commitMapValid_0), .io_commitMapValid_1 (_commit_io_commitMapValid_1), .io_commitArch_0 (_commit_io_commitArch_0), .io_commitArch_1 (_commit_io_commitArch_1), .io_commitPhys_0 (_commit_io_commitPhys_0), .io_commitPhys_1 (_commit_io_commitPhys_1), .io_commitFreeOld_0 (_commit_io_freeOldPhys_0), .io_commitFreeOld_1 (_commit_io_freeOldPhys_1), .io_commitOldPhys_0 (_commit_io_oldPhys_0), .io_commitOldPhys_1 (_commit_io_oldPhys_1), .io_flush (_commit_io_flush) ); IssueStage issue ( .clock (clock), .reset (reset), .io_inValid_0 (_rename_io_outValid_0), .io_inValid_1 (_rename_io_outValid_1), .io_in_0_decoded_pc (_rename_io_out_0_decoded_pc), .io_in_0_decoded_inst (_rename_io_out_0_decoded_inst), .io_in_0_decoded_rs1 (_rename_io_out_0_decoded_rs1), .io_in_0_decoded_rs2 (_rename_io_out_0_decoded_rs2), .io_in_0_decoded_funct3 (_rename_io_out_0_decoded_funct3), .io_in_0_decoded_immI (_rename_io_out_0_decoded_immI), .io_in_0_decoded_immS (_rename_io_out_0_decoded_immS), .io_in_0_decoded_immB (_rename_io_out_0_decoded_immB), .io_in_0_decoded_immU (_rename_io_out_0_decoded_immU), .io_in_0_decoded_immJ (_rename_io_out_0_decoded_immJ), .io_in_0_decoded_aluFn (_rename_io_out_0_decoded_aluFn), .io_in_0_decoded_memWidth (_rename_io_out_0_decoded_memWidth), .io_in_0_decoded_memSigned (_rename_io_out_0_decoded_memSigned), .io_in_0_decoded_isLoad (_rename_io_out_0_decoded_isLoad), .io_in_0_decoded_isStore (_rename_io_out_0_decoded_isStore), .io_in_0_decoded_isBranch (_rename_io_out_0_decoded_isBranch), .io_in_0_decoded_isJal (_rename_io_out_0_decoded_isJal), .io_in_0_decoded_isJalr (_rename_io_out_0_decoded_isJalr), .io_in_0_decoded_isLui (_rename_io_out_0_decoded_isLui), .io_in_0_decoded_isAuipc (_rename_io_out_0_decoded_isAuipc), .io_in_0_decoded_isOpImm (_rename_io_out_0_decoded_isOpImm), .io_in_0_decoded_isWord (_rename_io_out_0_decoded_isWord), .io_in_0_decoded_isSystem (_rename_io_out_0_decoded_isSystem), .io_in_0_decoded_isFenceI (_rename_io_out_0_decoded_isFenceI), .io_in_0_decoded_isEcall (_rename_io_out_0_decoded_isEcall), .io_in_0_decoded_isEbreak (_rename_io_out_0_decoded_isEbreak), .io_in_0_decoded_isMret (_rename_io_out_0_decoded_isMret), .io_in_0_decoded_isSret (_rename_io_out_0_decoded_isSret), .io_in_0_decoded_isSfenceVma (_rename_io_out_0_decoded_isSfenceVma), .io_in_0_decoded_isXret (_rename_io_out_0_decoded_isXret), .io_in_0_decoded_isWfi (_rename_io_out_0_decoded_isWfi), .io_in_0_decoded_isAmo (_rename_io_out_0_decoded_isAmo), .io_in_0_decoded_amoOp (_rename_io_out_0_decoded_amoOp), .io_in_0_decoded_writesRd (_rename_io_out_0_decoded_writesRd), .io_in_0_decoded_illegal (_rename_io_out_0_decoded_illegal), .io_in_0_decoded_fetchException (_rename_io_out_0_decoded_fetchException), .io_in_0_decoded_fetchExceptionCause (_rename_io_out_0_decoded_fetchExceptionCause), .io_in_0_decoded_fetchExceptionTval (_rename_io_out_0_decoded_fetchExceptionTval), .io_in_0_prs1 (_rename_io_out_0_prs1), .io_in_0_prs2 (_rename_io_out_0_prs2), .io_in_0_src1Ready (_rename_io_out_0_src1Ready), .io_in_0_src2Ready (_rename_io_out_0_src2Ready), .io_in_0_prd (_rename_io_out_0_prd), .io_in_0_robIdx (_rename_io_out_0_robIdx), .io_in_1_decoded_pc (_rename_io_out_1_decoded_pc), .io_in_1_decoded_inst (_rename_io_out_1_decoded_inst), .io_in_1_decoded_rs1 (_rename_io_out_1_decoded_rs1), .io_in_1_decoded_rs2 (_rename_io_out_1_decoded_rs2), .io_in_1_decoded_funct3 (_rename_io_out_1_decoded_funct3), .io_in_1_decoded_immI (_rename_io_out_1_decoded_immI), .io_in_1_decoded_immS (_rename_io_out_1_decoded_immS), .io_in_1_decoded_immB (_rename_io_out_1_decoded_immB), .io_in_1_decoded_immU (_rename_io_out_1_decoded_immU), .io_in_1_decoded_immJ (_rename_io_out_1_decoded_immJ), .io_in_1_decoded_aluFn (_rename_io_out_1_decoded_aluFn), .io_in_1_decoded_memWidth (_rename_io_out_1_decoded_memWidth), .io_in_1_decoded_memSigned (_rename_io_out_1_decoded_memSigned), .io_in_1_decoded_isLoad (_rename_io_out_1_decoded_isLoad), .io_in_1_decoded_isStore (_rename_io_out_1_decoded_isStore), .io_in_1_decoded_isBranch (_rename_io_out_1_decoded_isBranch), .io_in_1_decoded_isJal (_rename_io_out_1_decoded_isJal), .io_in_1_decoded_isJalr (_rename_io_out_1_decoded_isJalr), .io_in_1_decoded_isLui (_rename_io_out_1_decoded_isLui), .io_in_1_decoded_isAuipc (_rename_io_out_1_decoded_isAuipc), .io_in_1_decoded_isOpImm (_rename_io_out_1_decoded_isOpImm), .io_in_1_decoded_isWord (_rename_io_out_1_decoded_isWord), .io_in_1_decoded_isSystem (_rename_io_out_1_decoded_isSystem), .io_in_1_decoded_isFenceI (_rename_io_out_1_decoded_isFenceI), .io_in_1_decoded_isEcall (_rename_io_out_1_decoded_isEcall), .io_in_1_decoded_isEbreak (_rename_io_out_1_decoded_isEbreak), .io_in_1_decoded_isMret (_rename_io_out_1_decoded_isMret), .io_in_1_decoded_isSret (_rename_io_out_1_decoded_isSret), .io_in_1_decoded_isSfenceVma (_rename_io_out_1_decoded_isSfenceVma), .io_in_1_decoded_isXret (_rename_io_out_1_decoded_isXret), .io_in_1_decoded_isWfi (_rename_io_out_1_decoded_isWfi), .io_in_1_decoded_isAmo (_rename_io_out_1_decoded_isAmo), .io_in_1_decoded_amoOp (_rename_io_out_1_decoded_amoOp), .io_in_1_decoded_writesRd (_rename_io_out_1_decoded_writesRd), .io_in_1_decoded_illegal (_rename_io_out_1_decoded_illegal), .io_in_1_decoded_fetchException (_rename_io_out_1_decoded_fetchException), .io_in_1_decoded_fetchExceptionCause (_rename_io_out_1_decoded_fetchExceptionCause), .io_in_1_decoded_fetchExceptionTval (_rename_io_out_1_decoded_fetchExceptionTval), .io_in_1_prs1 (_rename_io_out_1_prs1), .io_in_1_prs2 (_rename_io_out_1_prs2), .io_in_1_src1Ready (_rename_io_out_1_src1Ready), .io_in_1_src2Ready (_rename_io_out_1_src2Ready), .io_in_1_prd (_rename_io_out_1_prd), .io_in_1_robIdx (_rename_io_out_1_robIdx), .io_inReady_0 (_issue_io_inReady_0), .io_inReady_1 (_issue_io_inReady_1), .io_wakeup_0_valid (wakeupReg_0_valid), .io_wakeup_0_phys (wakeupReg_0_phys), .io_wakeup_1_valid (wakeupReg_1_valid), .io_wakeup_1_phys (wakeupReg_1_phys), .io_outValid_0 (_issue_io_outValid_0), .io_outValid_1 (_issue_io_outValid_1), .io_out_0_decoded_pc (_issue_io_out_0_decoded_pc), .io_out_0_decoded_inst (_issue_io_out_0_decoded_inst), .io_out_0_decoded_rs1 (_issue_io_out_0_decoded_rs1), .io_out_0_decoded_funct3 (_issue_io_out_0_decoded_funct3), .io_out_0_decoded_immI (_issue_io_out_0_decoded_immI), .io_out_0_decoded_immS (_issue_io_out_0_decoded_immS), .io_out_0_decoded_immB (_issue_io_out_0_decoded_immB), .io_out_0_decoded_immU (_issue_io_out_0_decoded_immU), .io_out_0_decoded_immJ (_issue_io_out_0_decoded_immJ), .io_out_0_decoded_aluFn (_issue_io_out_0_decoded_aluFn), .io_out_0_decoded_memWidth (_issue_io_out_0_decoded_memWidth), .io_out_0_decoded_memSigned (_issue_io_out_0_decoded_memSigned), .io_out_0_decoded_isLoad (_issue_io_out_0_decoded_isLoad), .io_out_0_decoded_isStore (_issue_io_out_0_decoded_isStore), .io_out_0_decoded_isBranch (_issue_io_out_0_decoded_isBranch), .io_out_0_decoded_isJal (_issue_io_out_0_decoded_isJal), .io_out_0_decoded_isJalr (_issue_io_out_0_decoded_isJalr), .io_out_0_decoded_isLui (_issue_io_out_0_decoded_isLui), .io_out_0_decoded_isAuipc (_issue_io_out_0_decoded_isAuipc), .io_out_0_decoded_isOpImm (_issue_io_out_0_decoded_isOpImm), .io_out_0_decoded_isWord (_issue_io_out_0_decoded_isWord), .io_out_0_decoded_isSystem (_issue_io_out_0_decoded_isSystem), .io_out_0_decoded_isFenceI (_issue_io_out_0_decoded_isFenceI), .io_out_0_decoded_isEcall (_issue_io_out_0_decoded_isEcall), .io_out_0_decoded_isEbreak (_issue_io_out_0_decoded_isEbreak), .io_out_0_decoded_isMret (_issue_io_out_0_decoded_isMret), .io_out_0_decoded_isSret (_issue_io_out_0_decoded_isSret), .io_out_0_decoded_isSfenceVma (_issue_io_out_0_decoded_isSfenceVma), .io_out_0_decoded_isXret (_issue_io_out_0_decoded_isXret), .io_out_0_decoded_isWfi (_issue_io_out_0_decoded_isWfi), .io_out_0_decoded_isAmo (_issue_io_out_0_decoded_isAmo), .io_out_0_decoded_amoOp (_issue_io_out_0_decoded_amoOp), .io_out_0_decoded_writesRd (_issue_io_out_0_decoded_writesRd), .io_out_0_decoded_illegal (_issue_io_out_0_decoded_illegal), .io_out_0_decoded_fetchException (_issue_io_out_0_decoded_fetchException), .io_out_0_decoded_fetchExceptionCause (_issue_io_out_0_decoded_fetchExceptionCause), .io_out_0_decoded_fetchExceptionTval (_issue_io_out_0_decoded_fetchExceptionTval), .io_out_0_prs1 (_issue_io_out_0_prs1), .io_out_0_prs2 (_issue_io_out_0_prs2), .io_out_0_prd (_issue_io_out_0_prd), .io_out_0_robIdx (_issue_io_out_0_robIdx), .io_out_1_decoded_pc (_issue_io_out_1_decoded_pc), .io_out_1_decoded_inst (_issue_io_out_1_decoded_inst), .io_out_1_decoded_rs1 (_issue_io_out_1_decoded_rs1), .io_out_1_decoded_funct3 (_issue_io_out_1_decoded_funct3), .io_out_1_decoded_immI (_issue_io_out_1_decoded_immI), .io_out_1_decoded_immS (_issue_io_out_1_decoded_immS), .io_out_1_decoded_immB (_issue_io_out_1_decoded_immB), .io_out_1_decoded_immU (_issue_io_out_1_decoded_immU), .io_out_1_decoded_immJ (_issue_io_out_1_decoded_immJ), .io_out_1_decoded_aluFn (_issue_io_out_1_decoded_aluFn), .io_out_1_decoded_memWidth (_issue_io_out_1_decoded_memWidth), .io_out_1_decoded_memSigned (_issue_io_out_1_decoded_memSigned), .io_out_1_decoded_isLoad (_issue_io_out_1_decoded_isLoad), .io_out_1_decoded_isStore (_issue_io_out_1_decoded_isStore), .io_out_1_decoded_isBranch (_issue_io_out_1_decoded_isBranch), .io_out_1_decoded_isJal (_issue_io_out_1_decoded_isJal), .io_out_1_decoded_isJalr (_issue_io_out_1_decoded_isJalr), .io_out_1_decoded_isLui (_issue_io_out_1_decoded_isLui), .io_out_1_decoded_isAuipc (_issue_io_out_1_decoded_isAuipc), .io_out_1_decoded_isOpImm (_issue_io_out_1_decoded_isOpImm), .io_out_1_decoded_isWord (_issue_io_out_1_decoded_isWord), .io_out_1_decoded_isSystem (_issue_io_out_1_decoded_isSystem), .io_out_1_decoded_isFenceI (_issue_io_out_1_decoded_isFenceI), .io_out_1_decoded_isEcall (_issue_io_out_1_decoded_isEcall), .io_out_1_decoded_isEbreak (_issue_io_out_1_decoded_isEbreak), .io_out_1_decoded_isMret (_issue_io_out_1_decoded_isMret), .io_out_1_decoded_isSret (_issue_io_out_1_decoded_isSret), .io_out_1_decoded_isSfenceVma (_issue_io_out_1_decoded_isSfenceVma), .io_out_1_decoded_isXret (_issue_io_out_1_decoded_isXret), .io_out_1_decoded_isWfi (_issue_io_out_1_decoded_isWfi), .io_out_1_decoded_isAmo (_issue_io_out_1_decoded_isAmo), .io_out_1_decoded_amoOp (_issue_io_out_1_decoded_amoOp), .io_out_1_decoded_writesRd (_issue_io_out_1_decoded_writesRd), .io_out_1_decoded_illegal (_issue_io_out_1_decoded_illegal), .io_out_1_decoded_fetchException (_issue_io_out_1_decoded_fetchException), .io_out_1_decoded_fetchExceptionCause (_issue_io_out_1_decoded_fetchExceptionCause), .io_out_1_decoded_fetchExceptionTval (_issue_io_out_1_decoded_fetchExceptionTval), .io_out_1_prs1 (_issue_io_out_1_prs1), .io_out_1_prs2 (_issue_io_out_1_prs2), .io_out_1_prd (_issue_io_out_1_prd), .io_out_1_robIdx (_issue_io_out_1_robIdx), .io_outReady_0 (issue_io_outReady_0), .io_outReady_1 (issue_io_outReady_1), .io_robHeadValid (_rename_io_commitEntry_0_valid), .io_robHeadIdx (_rename_io_commitEntry_0_robIdx), .io_flush (_commit_io_flush) ); PhysicalRegFile prf ( .clock (clock), .reset (reset), .io_raddr_0 (_issue_io_out_0_prs1), .io_raddr_1 (_issue_io_out_0_prs2), .io_raddr_2 (_issue_io_out_1_prs1), .io_raddr_3 (_issue_io_out_1_prs2), .io_rdata_0 (_prf_io_rdata_0), .io_rdata_1 (_prf_io_rdata_1), .io_rdata_2 (_prf_io_rdata_2), .io_rdata_3 (_prf_io_rdata_3), .io_wen_0 (_wb_0_io_wen), .io_wen_1 (_wb_1_io_wen), .io_waddr_0 (_wb_0_io_waddr), .io_waddr_1 (_wb_1_io_waddr), .io_wdata_0 (_wb_0_io_wdata), .io_wdata_1 (_wb_1_io_wdata) ); ExecStage exec_0 ( .io_inValid (issueFire_0), .io_in_funct3 (_issue_io_out_0_decoded_funct3), .io_in_aluFn (_issue_io_out_0_decoded_aluFn), .io_in_isWord (_issue_io_out_0_decoded_isWord), .io_src1 (src1), .io_src2 (_issue_io_out_0_decoded_isOpImm | _issue_io_out_0_decoded_isLoad | _issue_io_out_0_decoded_isJalr ? _issue_io_out_0_decoded_immI : wakeupReg_0_valid & (|wakeupReg_0_phys) & wakeupReg_0_phys == _issue_io_out_0_prs2 ? wakeupReg_0_data : wakeupReg_1_valid & (|wakeupReg_1_phys) & wakeupReg_1_phys == _issue_io_out_0_prs2 ? wakeupReg_1_data : _prf_io_rdata_1), .io_outValid (_exec_0_io_outValid), .io_result (_exec_0_io_result), .io_branchTaken (_exec_0_io_branchTaken) ); ExecStage exec_1 ( .io_inValid (issueFire_1), .io_in_funct3 (_issue_io_out_1_decoded_funct3), .io_in_aluFn (_issue_io_out_1_decoded_aluFn), .io_in_isWord (_issue_io_out_1_decoded_isWord), .io_src1 (src1_1), .io_src2 (_issue_io_out_1_decoded_isOpImm | _issue_io_out_1_decoded_isLoad | _issue_io_out_1_decoded_isJalr ? _issue_io_out_1_decoded_immI : wakeupReg_0_valid & (|wakeupReg_0_phys) & wakeupReg_0_phys == _issue_io_out_1_prs2 ? wakeupReg_0_data : wakeupReg_1_valid & (|wakeupReg_1_phys) & wakeupReg_1_phys == _issue_io_out_1_prs2 ? wakeupReg_1_data : _prf_io_rdata_3), .io_outValid (_exec_1_io_outValid), .io_result (_exec_1_io_result), .io_branchTaken (_exec_1_io_branchTaken) ); WriteBackStage wb_0 ( .io_valid (_exec_0_io_outValid & _issue_io_out_0_decoded_writesRd & ~_issue_io_out_0_decoded_isLoad & ~issueRaisesException | isLoadRespSlot), .io_physDest (isLoadRespSlot ? (forwardPending ? forwardPendingPhys : loadPendingPhys) : _issue_io_out_0_prd), .io_data (isLoadRespSlot ? (forwardPending ? forwardPendingData : _lsu_io_respData) : _issue_io_out_0_decoded_isLui ? _issue_io_out_0_decoded_immU : _issue_io_out_0_decoded_isAuipc ? _issue_io_out_0_decoded_pc + _issue_io_out_0_decoded_immU : _completeMispredict_0_T ? _completeRedirectPc_0_T_2 : _issue_io_out_0_decoded_isSystem & (|_issue_io_out_0_decoded_funct3) ? _csr_io_rdata : _exec_0_io_result), .io_wen (_wb_0_io_wen), .io_waddr (_wb_0_io_waddr), .io_wdata (_wb_0_io_wdata) ); WriteBackStage wb_1 ( .io_valid (_exec_1_io_outValid & _issue_io_out_1_decoded_writesRd & ~_issue_io_out_1_decoded_isLoad & ~issueRaisesException_1), .io_physDest (_issue_io_out_1_prd), .io_data (_issue_io_out_1_decoded_isLui ? _issue_io_out_1_decoded_immU : _issue_io_out_1_decoded_isAuipc ? _issue_io_out_1_decoded_pc + _issue_io_out_1_decoded_immU : _completeMispredict_1_T ? _completeRedirectPc_1_T_2 : _issue_io_out_1_decoded_isSystem & (|_issue_io_out_1_decoded_funct3) ? _csr_io_rdata : _exec_1_io_result), .io_wen (_wb_1_io_wen), .io_waddr (_wb_1_io_waddr), .io_wdata (_wb_1_io_wdata) ); CommitStage commit ( .io_robValid_0 (_rename_io_commitValid_0), .io_robValid_1 (_rename_io_commitValid_1), .io_robEntry_0_pc (_rename_io_commitEntry_0_pc), .io_robEntry_0_archDest (_rename_io_commitEntry_0_archDest), .io_robEntry_0_writesDest (_rename_io_commitEntry_0_writesDest), .io_robEntry_0_opClass (_rename_io_commitEntry_0_opClass), .io_robEntry_0_dest (_rename_io_commitEntry_0_dest), .io_robEntry_0_oldDest (_rename_io_commitEntry_0_oldDest), .io_robEntry_0_exception (_rename_io_commitEntry_0_exception), .io_robEntry_0_exceptionCause (_rename_io_commitEntry_0_exceptionCause), .io_robEntry_0_badAddr (_rename_io_commitEntry_0_badAddr), .io_robEntry_0_branchMispredict (_rename_io_commitEntry_0_branchMispredict), .io_robEntry_0_redirectPc (_rename_io_commitEntry_0_redirectPc), .io_robEntry_0_csrValid (_rename_io_commitEntry_0_csrValid), .io_robEntry_0_fenceI (_rename_io_commitEntry_0_fenceI), .io_robEntry_0_sfenceVma (_rename_io_commitEntry_0_sfenceVma), .io_robEntry_0_xret (_rename_io_commitEntry_0_xret), .io_robEntry_0_xretIsMret (_rename_io_commitEntry_0_xretIsMret), .io_robEntry_1_pc (_rename_io_commitEntry_1_pc), .io_robEntry_1_archDest (_rename_io_commitEntry_1_archDest), .io_robEntry_1_writesDest (_rename_io_commitEntry_1_writesDest), .io_robEntry_1_dest (_rename_io_commitEntry_1_dest), .io_robEntry_1_oldDest (_rename_io_commitEntry_1_oldDest), .io_robEntry_1_exception (_rename_io_commitEntry_1_exception), .io_robEntry_1_exceptionCause (_rename_io_commitEntry_1_exceptionCause), .io_robEntry_1_badAddr (_rename_io_commitEntry_1_badAddr), .io_robEntry_1_branchMispredict (_rename_io_commitEntry_1_branchMispredict), .io_robEntry_1_redirectPc (_rename_io_commitEntry_1_redirectPc), .io_robEntry_1_csrValid (_rename_io_commitEntry_1_csrValid), .io_robEntry_1_fenceI (_rename_io_commitEntry_1_fenceI), .io_robEntry_1_sfenceVma (_rename_io_commitEntry_1_sfenceVma), .io_robEntry_1_xret (_rename_io_commitEntry_1_xret), .io_robEntry_1_xretIsMret (_rename_io_commitEntry_1_xretIsMret), .io_commitReady_0 (_commit_io_commitReady_0), .io_commitReady_1 (_commit_io_commitReady_1), .io_freeOldPhys_0 (_commit_io_freeOldPhys_0), .io_freeOldPhys_1 (_commit_io_freeOldPhys_1), .io_oldPhys_0 (_commit_io_oldPhys_0), .io_oldPhys_1 (_commit_io_oldPhys_1), .io_commitMapValid_0 (_commit_io_commitMapValid_0), .io_commitMapValid_1 (_commit_io_commitMapValid_1), .io_commitArch_0 (_commit_io_commitArch_0), .io_commitArch_1 (_commit_io_commitArch_1), .io_commitPhys_0 (_commit_io_commitPhys_0), .io_commitPhys_1 (_commit_io_commitPhys_1), .io_flush (_commit_io_flush), .io_redirectPc (_commit_io_redirectPc), .io_exception (_commit_io_exception), .io_exceptionCause (_commit_io_exceptionCause), .io_badAddr (_commit_io_badAddr), .io_trapPc (_commit_io_trapPc), .io_fenceI (io_invalidateICache), .io_sfenceVma (_commit_io_sfenceVma), .io_xret (_commit_io_xret), .io_xretIsMret (_commit_io_xretIsMret), .io_setPriv (io_setPriv) ); LoadQueue lq ( .clock (clock), .reset (reset), .io_enqValid (loadEnq), .io_enqRobIdx (sq_io_enqRobIdx), .io_enqIdx (_lq_io_enqIdx), .io_addrValid (loadEnq), .io_addrIdx (_lq_io_enqIdx), .io_addr (_memAddr_T_2), .io_size (sq_io_size), .io_complete (loadRespValid), .io_completeIdx (forwardPending ? forwardPendingLq : loadPendingLq), .io_commitValid_0 (_commitCsr0_T & _rename_io_commitEntry_0_opClass == 4'h3), .io_commitValid_1 (_commitCsr1_T & _rename_io_commitEntry_1_opClass == 4'h3), .io_commitRobIdx_0 (_rename_io_commitEntry_0_robIdx), .io_commitRobIdx_1 (_rename_io_commitEntry_1_robIdx), .io_storeAddrValid (storeEnq), .io_storeRobIdx (sq_io_enqRobIdx), .io_storeAddr (_memAddr_T_2), .io_storeSize (sq_io_size), .io_violation (_lq_io_violation), .io_flush (_commit_io_flush) ); StoreQueue sq ( .clock (clock), .reset (reset), .io_enqValid (storeEnq), .io_enqRobIdx (sq_io_enqRobIdx), .io_enqIdx (_sq_io_enqIdx), .io_writeAddr (storeEnq), .io_writeData (storeEnq), .io_writeIdx (_sq_io_enqIdx), .io_addr (_memAddr_T_2), .io_data (memSrc2), .io_size (sq_io_size), .io_loadAddr (_memAddr_T_2), .io_loadSize (sq_io_size), .io_loadRobIdx (sq_io_enqRobIdx), .io_forwardValid (_sq_io_forwardValid), .io_forwardData (_sq_io_forwardData), .io_forwardBlock (_sq_io_forwardBlock), .io_olderStoreValid (_sq_io_olderStoreValid), .io_commitValid (commitStore0 | _commitCsr1_T & _rename_io_commitEntry_1_opClass == 4'h4), .io_commitRobIdx (commitStore0 ? _rename_io_commitEntry_0_robIdx : _rename_io_commitEntry_1_robIdx), .io_drainValid (_sq_io_drainValid), .io_drain_addr (_sq_io_drain_addr), .io_drain_data (_sq_io_drain_data), .io_drain_size (_sq_io_drain_size), .io_drainReady (storeDrainFire), .io_flush (_commit_io_flush) ); LSU lsu ( .clock (clock), .reset (reset), .io_reqValid (lsuLoadReq | storeEnq | storeDrainFire), .io_req_addr (_GEN_3 ? _memAddr_T_2 : _sq_io_drain_addr), .io_req_data (_GEN_3 ? memSrc2 : _sq_io_drain_data), .io_req_isStore (~lsuLoadReq), .io_req_isSigned (lsuLoadReq & (_GEN_0 | loadReq_isAmo)), .io_req_isAmo (lsuLoadReq & loadReq_isAmo), .io_req_amoOp (lsuLoadReq ? (memIssue_0 ? _issue_io_out_0_decoded_amoOp : _issue_io_out_1_decoded_amoOp) : 5'h0), .io_req_size (_GEN_3 ? sq_io_size : _sq_io_drain_size), .io_checkOnly (storeEnq), .io_sfenceVma (_commit_io_sfenceVma), .io_currentPriv (io_currentPriv), .io_mstatus (_csr_io_mstatus), .io_reqReady (_lsu_io_reqReady), .io_satp (_csr_io_satp), .io_dmemReqValid (io_dmemReqValid), .io_dmemReq_addr (io_dmemReq_addr), .io_dmemReq_data (io_dmemReq_data), .io_dmemReq_isStore (io_dmemReq_isStore), .io_dmemReq_size (io_dmemReq_size), .io_dmemRespValid (io_dmemRespValid), .io_dmemRespData (io_dmemRespData), .io_respValid (_lsu_io_respValid), .io_respData (_lsu_io_respData), .io_pageFault (_lsu_io_pageFault), .io_misaligned (_lsu_io_misaligned), .io_faultCause (_lsu_io_faultCause), .io_faultAddr (_lsu_io_faultAddr) ); CSRFile csr ( .clock (clock), .reset (reset), .io_cmd_valid (commitCsr0 | _commitCsr1_T & _rename_io_commitEntry_1_csrValid), .io_cmd_addr (commitCsr0 ? _rename_io_commitEntry_0_csrAddr : _rename_io_commitEntry_1_csrAddr), .io_cmd_cmd (commitCsr0 ? _rename_io_commitEntry_0_csrCmd : _rename_io_commitEntry_1_csrCmd), .io_cmd_rs1 (commitCsr0 ? _rename_io_commitEntry_0_csrRs1 : _rename_io_commitEntry_1_csrRs1), .io_cmd_zimm (commitCsr0 ? _rename_io_commitEntry_0_csrZimm : _rename_io_commitEntry_1_csrZimm), .io_readAddr (csrReadFire_0 ? _issue_io_out_0_decoded_inst[31:20] : _issue_io_out_1_decoded_inst[31:20]), .io_currentPriv (io_currentPriv), .io_rdata (_csr_io_rdata), .io_readIllegal (_csr_io_readIllegal), .io_trap (_commit_io_flush & _commit_io_exception), .io_trapPc (_commit_io_trapPc), .io_trapCause (_commit_io_exceptionCause), .io_trapTval (_commit_io_badAddr), .io_trapTargetPriv (trapTargetPriv), .io_trapVector (_csr_io_trapVector), .io_xret (_commit_io_flush & _commit_io_xret), .io_xretIsMret (_commit_io_xretIsMret), .io_satp (_csr_io_satp), .io_mepc (_csr_io_mepc), .io_sepc (_csr_io_sepc), .io_medeleg (_csr_io_medeleg), .io_mstatus (_csr_io_mstatus) ); assign io_decodeReady = _rename_io_canAccept & (&{_issue_io_inReady_1, _issue_io_inReady_0}); assign io_flush = _commit_io_flush; assign io_redirectPc = _commit_io_exception ? _csr_io_trapVector : _commit_io_xret ? xretRedirectPc : _commit_io_redirectPc; assign io_sfenceVma = _commit_io_sfenceVma; assign io_targetPriv = _commit_io_exception ? trapTargetPriv : _commit_io_xret ? (_commit_io_xretIsMret ? _csr_io_mstatus[12:11] : {1'h0, _csr_io_mstatus[8]}) : io_currentPriv; assign io_satpOut = _csr_io_satp; endmodule