# RISC-V RV64G 双发射乱序处理器架构设计

## 目标规格
- **ISA**: RV64IMAFD (RV64G without C extension)
- **Issue Width**: 双发射（每周期2条指令）
- **Physical Registers**: 64个物理寄存器
- **Branch Predictor**: Gshare
- **Memory**: Sv39分页，分离的L1 ICache/DCache
- **Pipeline**: 11级流水线，乱序执行

---

## 1. 流水线架构

### 流水线阶段

```
┌─────┐   ┌─────┐   ┌────┐   ┌────┐   ┌────┐   ┌────┐   ┌─────┐   ┌─────┐   ┌─────┐   ┌────┐
│ IF1 │ → │ IF2 │ → │ ID │ → │ RN │ → │ DP │ → │ IS │ → │ EX1 │ → │ EX2 │ → │ MEM │ → │ WB │ → │ CM │
└─────┘   └─────┘   └────┘   └────┘   └────┘   └────┘   └─────┘   └─────┘   └─────┘   └────┘
  TLB      ICache    Decode  Rename  Dispatch  Issue    Execute   Execute   DCache    Write   Commit
  BPU                2-way                                                    Access    Back    ROB
```

### 各阶段功能

1. **IF1 (Instruction Fetch 1)**
   - PC生成与选择
   - ITLB查询（虚拟地址 → 物理地址）
   - Gshare分支预测
   - 取两条指令（双发射）

2. **IF2 (Instruction Fetch 2)**
   - ICache访问（64B缓存行）
   - 指令对齐与缓冲

3. **ID (Instruction Decode)**
   - 双路译码器（每周期译码2条指令）
   - 指令类型识别
   - 立即数生成
   - 依赖分析（RAW检测）

4. **RN (Rename)**
   - 寄存器重命名（32逻辑寄存器 → 64物理寄存器）
   - 空闲列表(Free List)管理
   - 重命名表(Rename Map Table)更新
   - ROB分配

5. **DP (Dispatch)**
   - 分发到保留站(Reservation Station)
   - 根据指令类型选择功能单元队列

6. **IS (Issue)**
   - 从保留站唤醒就绪指令
   - 乱序发射到执行单元
   - 读取物理寄存器文件

7. **EX1 (Execute 1)**
   - ALU运算
   - 分支计算
   - 地址生成（load/store）
   - 浮点运算第一阶段

8. **EX2 (Execute 2)**
   - 多周期运算完成
   - 浮点运算完成
   - 分支结果检查

9. **MEM (Memory)**
   - DTLB查询
   - DCache访问
   - Load/Store执行
   - Store Buffer管理

10. **WB (Write Back)**
    - 写回物理寄存器
    - 唤醒依赖指令
    - 更新ROB状态

11. **CM (Commit)**
    - ROB按序提交
    - 架构状态更新
    - 异常/中断处理
    - 物理寄存器释放

---

## 2. 核心部件设计

### 2.1 前端 (Front-End)

#### Gshare 分支预测器

```
├── Global History Register (GHR): 12-bit
├── Pattern History Table (PHT): 4096 entries × 2-bit saturating counter
├── Branch Target Buffer (BTB): 512 entries
│   ├── Tag: 20-bit
│   ├── Target Address: 64-bit
│   └── Valid bit
└── Return Address Stack (RAS): 16 entries
```

**Gshare索引计算**: `index = (PC[13:2] XOR GHR[11:0])`

要求：Branch Target Buffer大小可配置；Return Address Stack大小可配置

#### ICache
```
├── Capacity: 32 KB
├── Associativity: 4-way set-associative
├── Line Size: 64 bytes
├── Sets: 128
└── Replacement: Pseudo-LRU
```

要求：Capacity大小可配置；Associativity大小可配置

#### ITLB
```
├── Entries: 32 (Fully associative)
├── Page Size: 4KB (Sv39)
├── Replacement: LRU
└── Support: Mega pages (2MB), Giga pages (1GB)
```

要求：Entries大小可配置

### 2.2 乱序执行核心

#### 重命名逻辑
```
Rename Map Table (RMT)
├── Arch Regs: 32 (x0-x31)
├── Phys Regs: 64 (p0-p63)
└── Mapping: arch_reg → phys_reg

Free List
├── Available physical registers
└── FIFO allocation

Committed Map Table (CMT)
└── For precise exception recovery
```

#### Reorder Buffer (ROB)
```
├── Entries: 64
├── Fields per entry:
│   ├── Valid
│   ├── PC
│   ├── Instruction Type
│   ├── Destination Physical Register
│   ├── Old Physical Register (for freeing)
│   ├── Exception Info
│   ├── Completed
│   └── Branch Mispredict
├── Head Pointer (commit)
└── Tail Pointer (allocate)
```

要求：Entries可配置

#### Reservation Stations
```
Integer RS
├── Entries: 16
└── ALU, Branch, Integer Multiply/Divide

Load/Store RS
├── Entries: 12
└── Address generation, Memory ops

FP RS
├── Entries: 16
└── FP Add, FP Multiply, FP Divide
```

#### Physical Register File
```
Integer PRF
├── Registers: 64 × 64-bit
└── Read Ports: 4 (dual-issue × 2 operands)
└── Write Ports: 2 (dual-issue)

FP PRF
├── Registers: 64 × 64-bit
└── Read Ports: 4
└── Write Ports: 2
```

### 2.3 执行单元

```
├── ALU0: Integer ALU (ADD, SUB, AND, OR, XOR, SLT, etc.)
├── ALU1: Integer ALU
├── Branch Unit: Branch comparison
├── AGU: Address Generation Unit (Load/Store)
├── MDU: Multiply/Divide Unit (3-cycle latency for MUL, iterative for DIV)
├── FPU0: FP Add/Sub (4-cycle latency)
├── FPU1: FP Multiply (5-cycle latency)
└── FPU2: FP Divide/Sqrt (iterative, variable latency)
```

### 2.4 后端 (Memory Subsystem)

#### DCache
```
├── Capacity: 32 KB
├── Associativity: 8-way set-associative
├── Line Size: 64 bytes
├── Sets: 64
├── Replacement: Pseudo-LRU
├── Write Policy: Write-back
└── MSHR: 4 entries (Miss Status Holding Registers)
```

要求：Capacity大小可配置；Associativity大小可配置

#### DTLB
```
├── Entries: 32 (Fully associative)
├── Page Size: 4KB (Sv39)
├── Replacement: LRU
└── Support: Mega pages (2MB), Giga pages (1GB)
```

要求：Entries大小可配置

#### MMU (Sv39)
```
├── Virtual Address: 39-bit
├── Physical Address: 56-bit (RISC-V spec allows up to 56)
├── Page Table Walker:
│   ├── 3-level page table
│   ├── Hardware page table walk
│   └── PTE cache (8 entries per level)
└── CSR Support:
    ├── satp (Supervisor Address Translation and Protection)
    ├── sstatus, sie, sip, stvec
    └── sepc, scause, stval, sscratch
```

#### Load/Store Queue
```
Load Queue (LQ)
├── Entries: 16
└── Track in-flight loads

Store Queue (SQ)
├── Entries: 16
├── Store-to-Load forwarding
└── Drain on fence/commit
```

要求：Entries大小可配置

### 2.5 提交阶段

```
Commit Logic
├── Commit Width: 2 instructions per cycle
├── In-order commit from ROB head
├── Exception handling:
│   ├── Flush pipeline
│   ├── Restore architectural state from CMT
│   └── Free speculative physical registers
└── Branch mispredict recovery:
    ├── Flush younger instructions
    ├── Restore RMT from ROB checkpoint
    └── Redirect fetch
```

---

## 3. 数据通路

### 3.1 指令流
```
PC → ITLB → ICache → Instruction Buffer → Decoder (×2) → Rename → 
Dispatch → Reservation Stations → Issue → Execute → Write Back → ROB → Commit
```

### 3.2 数据流
```
Read PRF → Execute → Write Result → Broadcast (Bypass) → Write PRF → Update ROB
                                                        └→ Wakeup dependent instructions
```

### 3.3 控制流
```
Branch Predictor → Speculative Fetch → Execute Branch → Compare → 
[Match: Continue] / [Mispredict: Flush + Redirect]
```

---

## 4. 关键设计决策

### 4.1 双发射策略
- **静态配对**: 在ID阶段检查指令间依赖
- **限制**: 不允许同时发射两条分支指令、两条访存指令
- **对齐**: 指令对必须来自连续的PC

### 4.2 物理寄存器分配
- **64个物理寄存器**: 32个用于映射当前架构状态，32个用于投机执行
- **回收时机**: 指令提交时，释放旧的物理寄存器

### 4.3 分支预测恢复
- **检查点机制**: 每条分支在RN阶段创建RMT快照
- **恢复**: 分支错误预测时，恢复到该分支的RMT快照

### 4.4 内存一致性
- **顺序模型**: RISC-V Weak Memory Order (RVWMO)
- **Load乱序**: 可以越过Store执行（需要地址消歧）
- **Store Buffer**: Store指令提交后写入，按序释放到Cache

### 4.5 异常处理
- **精确异常**: 通过ROB实现
- **异常类型**: 
  - Page Fault (ITLB/DTLB miss)
  - Illegal Instruction
  - Misaligned Access
  - Breakpoint
  - System Call

---

## 5. 性能参数估算

| 指标 | 目标值 |
|------|--------|
| IPC (理想) | 1.8-2.0 |
| IPC (实际) | 1.2-1.5 (考虑分支错误、Cache miss) |
| 分支预测准确率 | >90% (Gshare) |
| ICache命中率 | >95% |
| DCache命中率 | >90% |
| TLB命中率 | >98% |
| 频率目标 | 100-200 MHz (FPGA) |

---

## 6. Linux启动需求

要成功启动Linux，CPU必须支持：

### 6.1 特权级
- **M-mode** (Machine): 最高特权级，处理异常/中断
- **S-mode** (Supervisor): Linux内核运行在此
- **U-mode** (User): 用户程序

### 6.2 必需的CSR
```
Machine Mode:
- mstatus, misa, medeleg, mideleg
- mtvec, mepc, mcause, mtval
- mip, mie, mtime, mtimecmp

Supervisor Mode:
- sstatus, stvec, sepc, scause, stval
- satp (MMU配置)
- sip, sie

Counters:
- cycle, time, instret
```

### 6.3 中断/异常
- Timer interrupt (CLINT)
- External interrupt (PLIC)
- Software interrupt
- 所有RISC-V异常类型

### 6.4 原子指令 (A扩展)
- LR/SC (Load-Reserved/Store-Conditional)
- AMO (Atomic Memory Operations): AMOSWAP, AMOADD, AMOXOR, AMOAND, AMOOR, AMOMIN, AMOMAX

### 6.5 外设接口
- UART (串口输出)
- CLINT (核心本地中断器)
- PLIC (平台级中断控制器)

---

## 7. 验证策略

### 7.1 单元测试
- 每个模块的功能验证
- Chisel Unit Tests

### 7.2 ISA测试
- riscv-tests (官方ISA测试套件)
- rv64ui, rv64um, rv64ua, rv64uf, rv64ud

### 7.3 随机测试
- riscv-torture (随机指令生成)

### 7.4 系统测试
- CoreMark, Dhrystone (性能基准测试)
- Linux boot (最终目标)

---

## 8. Chisel实现模块划分

```
src/main/scala/
├── common/
│   ├── Consts.scala          // 常量定义
│   ├── Parameters.scala      // 参数配置
│   └── Bundles.scala         // 数据结构定义
├── frontend/
│   ├── ICache.scala
│   ├── ITLB.scala
│   ├── BranchPredictor.scala // Gshare
│   ├── BTB.scala
│   ├── RAS.scala
│   └── Frontend.scala        // 前端顶层
├── decode/
│   ├── Decoder.scala
│   └── IDStage.scala
├── rename/
│   ├── RenameTable.scala
│   ├── FreeList.scala
│   ├── ROB.scala
│   └── RenameStage.scala
├── issue/
│   ├── ReservationStation.scala
│   ├── IssueQueue.scala
│   └── IssueStage.scala
├── execute/
│   ├── ALU.scala
│   ├── BranchUnit.scala
│   ├── Multiplier.scala
│   ├── Divider.scala
│   ├── FPU.scala
│   └── ExecStage.scala
├── memory/
│   ├── DCache.scala
│   ├── DTLB.scala
│   ├── MMU.scala
│   ├── LSU.scala             // Load/Store Unit
│   ├── LoadQueue.scala
│   ├── StoreQueue.scala
│   └── MemStage.scala
├── writeback/
│   └── WriteBackStage.scala
├── commit/
│   └── CommitStage.scala
├── regfile/
│   └── PhysicalRegFile.scala
├── csr/
│   ├── CSRFile.scala
│   └── PrivilegeControl.scala
└── Core.scala                // 处理器顶层
```

---

## 9. 参考资料

- **RISC-V Spec**: https://riscv.org/technical/specifications/
- **Sv39 Paging**: RISC-V Privileged Spec Chapter 4
- **Gshare Predictor**: "Two-Level Adaptive Training Branch Prediction" (Yeh & Patt, 1991)
- **BOOM Processor**: Berkeley Out-of-Order Machine (参考设计)
- **Rocket Chip**: 顺序发射RISC-V处理器（前端参考）