feat: implement privileged mode support

This commit is contained in:
abnerhexu
2026-06-29 07:00:55 +00:00
parent a32db39c80
commit b6afa61e66
89 changed files with 49571 additions and 43647 deletions

View File

@@ -2,20 +2,14 @@ import chisel3._
class PrivilegeControl(p: CoreParams = CoreParams()) extends Module {
val io = IO(new Bundle {
val trap = Input(Bool())
val mret = Input(Bool())
val sret = Input(Bool())
val privilege = Output(UInt(2.W))
val nextPriv = Input(UInt(2.W))
val setPriv = Input(Bool())
val priv = Output(UInt(2.W))
})
val mode = RegInit(3.U(2.W))
when(io.trap) {
mode := 3.U
}.elsewhen(io.mret) {
mode := 0.U
}.elsewhen(io.sret) {
mode := 0.U
val privReg = RegInit(Privileged.PRV_M)
when(io.setPriv) {
privReg := io.nextPriv
}
io.privilege := mode
io.priv := privReg
}