feat: implement privileged mode support
This commit is contained in:
abnerhexu
@@ -16,12 +16,17 @@ class OoOBackend(p: CoreParams = CoreParams()) extends Module {
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val flush = Output(Bool())
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val redirectPc = Output(UInt(p.xlen.W))
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val invalidateICache = Output(Bool())
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val sfenceVma = Output(Bool())
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val setPriv = Output(Bool())
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val targetPriv = Output(UInt(2.W))
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val dmemReqValid = Output(Bool())
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val dmemReq = Output(new MemRequest(p))
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val dmemRespValid = Input(Bool())
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val dmemRespData = Input(UInt(p.xlen.W))
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val satp = Input(UInt(p.xlen.W))
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val satpOut = Output(UInt(p.xlen.W))
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val currentPriv = Input(UInt(2.W))
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})
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val rename = Module(new RenameStage(p))
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@@ -47,9 +52,18 @@ class OoOBackend(p: CoreParams = CoreParams()) extends Module {
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val completeCsrCmd = Wire(Vec(p.issueWidth, UInt(3.W)))
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val completeCsrRs1 = Wire(Vec(p.issueWidth, UInt(p.xlen.W)))
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val completeCsrZimm = Wire(Vec(p.issueWidth, UInt(5.W)))
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val completeFenceI = Wire(Vec(p.issueWidth, Bool()))
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val completeSfenceVma = Wire(Vec(p.issueWidth, Bool()))
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val completeXret = Wire(Vec(p.issueWidth, Bool()))
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val completeXretIsMret = Wire(Vec(p.issueWidth, Bool()))
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val wakeup = Wire(Vec(p.issueWidth, new Wakeup(p)))
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val wakeupReg = RegInit(VecInit(Seq.fill(p.issueWidth)(0.U.asTypeOf(new Wakeup(p)))))
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val csrRData = Wire(Vec(p.issueWidth, UInt(p.xlen.W)))
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dontTouch(completeValid)
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dontTouch(completeIdx)
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dontTouch(completeException)
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dontTouch(completeCause)
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dontTouch(completeRedirectPc)
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rename.io.inValid := VecInit((0 until p.issueWidth).map(i => io.decodeValid(i) && issue.io.inReady(i)))
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rename.io.in := io.decode
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@@ -67,6 +81,10 @@ class OoOBackend(p: CoreParams = CoreParams()) extends Module {
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rename.io.completeCsrCmd := completeCsrCmd
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rename.io.completeCsrRs1 := completeCsrRs1
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rename.io.completeCsrZimm := completeCsrZimm
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rename.io.completeFenceI := completeFenceI
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rename.io.completeSfenceVma := completeSfenceVma
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rename.io.completeXret := completeXret
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rename.io.completeXretIsMret := completeXretIsMret
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rename.io.commitReady := commit.io.commitReady
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rename.io.commitMapValid := commit.io.commitMapValid
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rename.io.commitArch := commit.io.commitArch
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@@ -78,6 +96,8 @@ class OoOBackend(p: CoreParams = CoreParams()) extends Module {
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issue.io.inValid := rename.io.outValid
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issue.io.in := rename.io.out
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issue.io.wakeup := wakeupReg
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issue.io.robHeadValid := rename.io.commitEntry(0).valid
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issue.io.robHeadIdx := rename.io.commitEntry(0).robIdx
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val loadPending = RegInit(false.B)
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val loadPendingRob = Reg(UInt(robBits.W))
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val loadPendingPhys = Reg(UInt(physBits.W))
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@@ -89,7 +109,14 @@ class OoOBackend(p: CoreParams = CoreParams()) extends Module {
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val forwardPendingData = Reg(UInt(p.xlen.W))
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val loadRespValid = (lsu.io.respValid && loadPending) || forwardPending
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val loadRespData = Mux(forwardPending, forwardPendingData, lsu.io.respData)
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val loadRespPageFault = !forwardPending && lsu.io.pageFault
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val loadRespFault = !forwardPending && (lsu.io.pageFault || lsu.io.accessFault || lsu.io.misaligned)
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val storeCheckPending = RegInit(false.B)
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val storeCheckPendingRob = Reg(UInt(robBits.W))
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dontTouch(storeCheckPending)
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val storeCheckRespNow = Wire(Bool())
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val storeCheckRespPending = storeCheckPending && lsu.io.respValid
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val storeCheckResp = storeCheckRespNow || storeCheckRespPending
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val storeCheckFault = storeCheckResp && (lsu.io.pageFault || lsu.io.accessFault || lsu.io.misaligned)
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val memIssue = Wire(Vec(p.issueWidth, Bool()))
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for (i <- 0 until p.issueWidth) {
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memIssue(i) := issue.io.outValid(i) && (issue.io.out(i).decoded.isLoad || issue.io.out(i).decoded.isStore)
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@@ -103,22 +130,47 @@ class OoOBackend(p: CoreParams = CoreParams()) extends Module {
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val memSlot0 = memIssue(0)
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val memSlot1 = !memSlot0 && memIssue(1)
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val memSlot = Mux(memSlot0, 0.U, 1.U)
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val canIssueMem = !loadPending && !forwardPending
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val canIssueMem = !loadPending && !forwardPending && !storeCheckPending
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val issue_io_outReady_0 = Wire(Bool())
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val issue_io_outReady_1 = Wire(Bool())
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dontTouch(issue_io_outReady_0)
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dontTouch(issue_io_outReady_1)
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val isMem0 = issue.io.out(0).decoded.isLoad || issue.io.out(0).decoded.isStore
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val isMem1 = issue.io.out(1).decoded.isLoad || issue.io.out(1).decoded.isStore
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val serializing0 = issue.io.out(0).decoded.isSystem || issue.io.out(0).decoded.isFenceI ||
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issue.io.out(0).decoded.isSfenceVma || issue.io.out(0).decoded.isWfi
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val serializing1 = issue.io.out(1).decoded.isSystem || issue.io.out(1).decoded.isFenceI ||
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issue.io.out(1).decoded.isSfenceVma || issue.io.out(1).decoded.isWfi
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val serializingReady0 = !serializing0 ||
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(rename.io.commitEntry(0).valid && rename.io.commitEntry(0).robIdx === issue.io.out(0).robIdx)
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val serializingReady1 = !serializing1 ||
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(rename.io.commitEntry(0).valid && rename.io.commitEntry(0).robIdx === issue.io.out(1).robIdx)
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dontTouch(serializingReady0)
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dontTouch(serializingReady1)
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val loadBlocked0 = issue.io.out(0).decoded.isLoad && sq.io.forwardBlock
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val loadBlocked1 = issue.io.out(1).decoded.isLoad && sq.io.forwardBlock
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val amoBlocked0 = issue.io.out(0).decoded.isAmo && (sq.io.olderStoreValid || sq.io.drainValid)
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val amoBlocked1 = issue.io.out(1).decoded.isAmo && (sq.io.olderStoreValid || sq.io.drainValid)
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val robHeadValid = rename.io.commitEntry(0).valid
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val issue0AtHead = robHeadValid && rename.io.commitEntry(0).robIdx === issue.io.out(0).robIdx
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val issue1AtHead = robHeadValid && rename.io.commitEntry(0).robIdx === issue.io.out(1).robIdx
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val olderSerializingAtHead0 = robHeadValid && !issue0AtHead &&
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(rename.io.commitEntry(0).csrValid || rename.io.commitEntry(0).fenceI ||
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rename.io.commitEntry(0).sfenceVma || rename.io.commitEntry(0).xret)
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val olderSerializingAtHead1 = robHeadValid && !issue1AtHead &&
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(rename.io.commitEntry(0).csrValid || rename.io.commitEntry(0).fenceI ||
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rename.io.commitEntry(0).sfenceVma || rename.io.commitEntry(0).xret)
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val memReady0 = (!isMem0 || (lsu.io.reqReady && canIssueMem && !amoBlocked0 && !loadBlocked0)) &&
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!loadPending && !forwardPending
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val memReady1 = !isMem1 || (lsu.io.reqReady && canIssueMem && !memSlot0 && !amoBlocked1 && !loadBlocked1)
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issue_io_outReady_0 := memReady0
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issue_io_outReady_1 := memReady1 && !stallSecondCsrRead
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!loadPending && !forwardPending && serializingReady0 && !olderSerializingAtHead0
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val memReady1 = (!isMem1 || (lsu.io.reqReady && canIssueMem && !memSlot0 && !amoBlocked1 && !loadBlocked1)) &&
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serializingReady1 && !olderSerializingAtHead1
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val baseIssueReady0 = memReady0 && !storeCheckPending
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val baseIssueReady1 = memReady1 && !storeCheckPending
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val slot0WouldIssueSerializing = issue.io.outValid(0) && baseIssueReady0 && serializing0
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val slot1WouldIssueSerializing = issue.io.outValid(1) && baseIssueReady1 && serializing1
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issue_io_outReady_0 := baseIssueReady0 && !slot1WouldIssueSerializing
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issue_io_outReady_1 := baseIssueReady1 && !slot0WouldIssueSerializing &&
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!(stallSecondCsrRead && issue_io_outReady_0)
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issue.io.outReady := VecInit(Seq(issue_io_outReady_0, issue_io_outReady_1))
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val issueFire = Wire(Vec(p.issueWidth, Bool()))
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for (i <- 0 until p.issueWidth) {
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@@ -132,12 +184,19 @@ class OoOBackend(p: CoreParams = CoreParams()) extends Module {
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val memSrc1 = Mux(memSlot0, prf.io.rdata(0), prf.io.rdata(2))
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val memSrc2 = Mux(memSlot0, prf.io.rdata(1), prf.io.rdata(3))
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val memAddr = memSrc1 + Mux(memDecoded.isAmo, 0.U, Mux(memDecoded.isStore, memDecoded.immS, memDecoded.immI))
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def accessBytes(size: UInt): UInt = MuxLookup(size, 8.U(4.W))(Seq(
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0.U -> 1.U(4.W),
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1.U -> 2.U(4.W),
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2.U -> 4.U(4.W),
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3.U -> 8.U(4.W)
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))
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val loadEnq = (memSlot0 || memSlot1) && memDecoded.isLoad && issue.io.outReady(memSlot)
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val storeEnq = (memSlot0 || memSlot1) && memDecoded.isStore && issue.io.outReady(memSlot)
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val sqForwardValid = sq.io.forwardValid && !memDecoded.isAmo
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val forwardLoad = loadEnq && sqForwardValid
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val lsuLoadReq = loadEnq && !sqForwardValid
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val lsuStoreCheckReq = storeEnq
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val forwardByte = sq.io.forwardData(7, 0)
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val forwardHalf = sq.io.forwardData(15, 0)
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val forwardWord = sq.io.forwardData(31, 0)
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@@ -183,10 +242,15 @@ class OoOBackend(p: CoreParams = CoreParams()) extends Module {
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rename.io.commitEntry(1).opClass === Consts.OP_STORE
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sq.io.commitValid := commitStore0 || commitStore1
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sq.io.commitRobIdx := Mux(commitStore0, rename.io.commitEntry(0).robIdx, rename.io.commitEntry(1).robIdx)
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sq.io.drainReady := !lsuLoadReq && lsu.io.reqReady
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val storeDrainFire = sq.io.drainValid && !lsuLoadReq && !lsuStoreCheckReq && lsu.io.reqReady
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sq.io.drainReady := storeDrainFire
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sq.io.flush := commit.io.flush
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lsu.io.reqValid := lsuLoadReq || sq.io.drainValid
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lsu.io.reqValid := lsuLoadReq || lsuStoreCheckReq || storeDrainFire
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lsu.io.checkOnly := lsuStoreCheckReq
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lsu.io.sfenceVma := commit.io.sfenceVma
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lsu.io.currentPriv := io.currentPriv
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lsu.io.mstatus := csr.io.mstatus
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val loadReq = WireDefault(0.U.asTypeOf(new MemRequest(p)))
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loadReq.addr := memAddr
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loadReq.data := memSrc2
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@@ -195,20 +259,42 @@ class OoOBackend(p: CoreParams = CoreParams()) extends Module {
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loadReq.isAmo := memDecoded.isAmo
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loadReq.amoOp := memDecoded.amoOp
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loadReq.size := memDecoded.memWidth
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lsu.io.req := Mux(lsuLoadReq, loadReq, sq.io.drain)
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val storeCheckReq = WireDefault(0.U.asTypeOf(new MemRequest(p)))
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storeCheckReq.addr := memAddr
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storeCheckReq.data := memSrc2
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storeCheckReq.isStore := true.B
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storeCheckReq.isSigned := false.B
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storeCheckReq.isAmo := false.B
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storeCheckReq.amoOp := 0.U
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storeCheckReq.size := memDecoded.memWidth
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lsu.io.req := Mux(lsuLoadReq, loadReq, Mux(lsuStoreCheckReq, storeCheckReq, sq.io.drain))
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storeCheckRespNow := lsuStoreCheckReq && lsu.io.respValid
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lsu.io.dmemRespValid := io.dmemRespValid
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lsu.io.dmemRespData := io.dmemRespData
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lsu.io.satp := csr.io.satp
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io.satpOut := csr.io.satp
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io.dmemReqValid := lsu.io.dmemReqValid
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io.dmemReq := lsu.io.dmemReq
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val csrReadFire = VecInit((0 until p.issueWidth).map(i => csrReadReq(i) && issue.io.outReady(i)))
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csr.io.readAddr := Mux(csrReadFire(0), issue.io.out(0).decoded.inst(31, 20), issue.io.out(1).decoded.inst(31, 20))
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csr.io.currentPriv := io.currentPriv
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csrRData(0) := csr.io.rdata
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csrRData(1) := csr.io.rdata
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csr.io.trap := commit.io.flush && commit.io.exception
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csr.io.trapPc := commit.io.badAddr
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csr.io.trapPc := commit.io.trapPc
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csr.io.trapCause := commit.io.exceptionCause
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csr.io.trapTval := commit.io.badAddr
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val trapTargetPriv = PrivilegeTransitions.trapTargetPriv(
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io.currentPriv,
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commit.io.exceptionCause,
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false.B,
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csr.io.medeleg,
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csr.io.mideleg)
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csr.io.trapTargetPriv := trapTargetPriv
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csr.io.trapIsInterrupt := false.B
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csr.io.xret := commit.io.flush && commit.io.xret
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csr.io.xretIsMret := commit.io.xretIsMret
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val commitCsr0 = commit.io.commitReady(0) && rename.io.commitValid(0) && rename.io.commitEntry(0).csrValid
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val commitCsr1 = commit.io.commitReady(1) && rename.io.commitValid(1) && rename.io.commitEntry(1).csrValid
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val commitCsrEntry = Mux(commitCsr0, rename.io.commitEntry(0), rename.io.commitEntry(1))
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@@ -221,6 +307,7 @@ class OoOBackend(p: CoreParams = CoreParams()) extends Module {
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when(commit.io.flush) {
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loadPending := false.B
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forwardPending := false.B
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storeCheckPending := false.B
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}.elsewhen(forwardLoad) {
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forwardPending := true.B
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forwardPendingRob := issue.io.out(memSlot).robIdx
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@@ -237,6 +324,14 @@ class OoOBackend(p: CoreParams = CoreParams()) extends Module {
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}.elsewhen(loadRespValid) {
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loadPending := false.B
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}
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when(!commit.io.flush) {
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when(storeCheckRespPending) {
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storeCheckPending := false.B
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}.elsewhen(lsuStoreCheckReq && !storeCheckRespNow) {
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storeCheckPending := true.B
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storeCheckPendingRob := issue.io.out(memSlot).robIdx
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}
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}
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for (i <- 0 until p.issueWidth) {
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prf.io.raddr(2 * i) := issue.io.out(i).prs1
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@@ -245,8 +340,12 @@ class OoOBackend(p: CoreParams = CoreParams()) extends Module {
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for (i <- 0 until p.issueWidth) {
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val decoded = issue.io.out(i).decoded
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val src1 = prf.io.rdata(2 * i)
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val rs2Val = prf.io.rdata(2 * i + 1)
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val src1Raw = prf.io.rdata(2 * i)
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val rs2Raw = prf.io.rdata(2 * i + 1)
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val src1 = MuxCase(src1Raw, (0 until p.issueWidth).map(w =>
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(wakeupReg(w).valid && wakeupReg(w).phys =/= 0.U && wakeupReg(w).phys === issue.io.out(i).prs1) -> wakeupReg(w).data))
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val rs2Val = MuxCase(rs2Raw, (0 until p.issueWidth).map(w =>
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(wakeupReg(w).valid && wakeupReg(w).phys =/= 0.U && wakeupReg(w).phys === issue.io.out(i).prs2) -> wakeupReg(w).data))
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val src2 = Mux(decoded.isOpImm || decoded.isLoad || decoded.isJalr, decoded.immI, rs2Val)
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exec(i).io.inValid := issueFire(i)
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@@ -254,8 +353,40 @@ class OoOBackend(p: CoreParams = CoreParams()) extends Module {
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exec(i).io.src1 := src1
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exec(i).io.src2 := src2
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val isLoadRespSlot = i.U === 0.U && loadRespValid
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val useExecWb = exec(i).io.outValid && decoded.writesRd && !decoded.isLoad
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val branchTarget = decoded.pc + decoded.immB
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val jalTarget = decoded.pc + decoded.immJ
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val jalrTarget = (src1 + decoded.immI) & (~1.U(p.xlen.W))
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val controlTarget = Mux(decoded.isJal, jalTarget,
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Mux(decoded.isJalr, jalrTarget, branchTarget))
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val controlTargetMisaligned = issueFire(i) &&
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(decoded.isJal || decoded.isJalr || (decoded.isBranch && exec(i).io.branchTaken)) &&
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controlTarget(1, 0) =/= 0.U
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dontTouch(controlTargetMisaligned)
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val branchRedirect = Mux(decoded.isJal, jalTarget,
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Mux(decoded.isJalr, jalrTarget,
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Mux(decoded.isBranch && exec(i).io.branchTaken, branchTarget, decoded.pc + 4.U)))
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val isEcall = decoded.isEcall
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val isEbreak = decoded.isEbreak
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val isMret = decoded.isMret
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val illegalPriv = (decoded.isMret && io.currentPriv =/= Privileged.PRV_M) ||
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(decoded.isSret && io.currentPriv === Privileged.PRV_U) ||
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(decoded.isSfenceVma && io.currentPriv === Privileged.PRV_U)
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val csrReadIllegal = csrReadFire(i) && csr.io.readIllegal
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val csrWrites = decoded.isSystem && decoded.funct3 =/= 0.U &&
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!(decoded.funct3(1) && decoded.rs1 === 0.U)
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val csrWriteIllegal = csrWrites && !CSRPermission.writeAllowed(decoded.inst(31, 20), io.currentPriv)
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val illegalInst = !decoded.fetchException && (decoded.illegal || illegalPriv || csrReadIllegal || csrWriteIllegal)
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val dataAddr = src1 + Mux(decoded.isStore, decoded.immS, decoded.immI)
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val dataMisaligned = (dataAddr(2, 0) & (accessBytes(decoded.memWidth) - 1.U)) =/= 0.U
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val storeMisaligned = issueFire(i) && decoded.isStore && dataMisaligned
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val loadFaultNow = lsuLoadReq && lsu.io.respValid && (lsu.io.misaligned || lsu.io.pageFault || lsu.io.accessFault)
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val issueRaisesException = issueFire(i) &&
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(decoded.fetchException || illegalInst || isEcall || isEbreak || lq.io.violation || storeMisaligned ||
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controlTargetMisaligned)
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val loadRespHasFault = loadRespFault || loadFaultNow
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val isLoadRespSlot = i.U === 0.U && loadRespValid && !loadRespHasFault
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val useExecWb = exec(i).io.outValid && decoded.writesRd && !decoded.isLoad && !issueRaisesException
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wb(i).io.valid := useExecWb || isLoadRespSlot
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wb(i).io.physDest := Mux(isLoadRespSlot, Mux(forwardPending, forwardPendingPhys, loadPendingPhys), issue.io.out(i).prd)
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wb(i).io.data := Mux(isLoadRespSlot, loadRespData, Mux(decoded.isLui, decoded.immU,
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@@ -271,36 +402,47 @@ class OoOBackend(p: CoreParams = CoreParams()) extends Module {
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wakeup(i).phys := wb(i).io.waddr
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wakeup(i).data := wb(i).io.wdata
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val branchTarget = decoded.pc + decoded.immB
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val jalTarget = decoded.pc + decoded.immJ
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val jalrTarget = (src1 + decoded.immI) & (~1.U(p.xlen.W))
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val branchRedirect = Mux(decoded.isJal, jalTarget,
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||||
Mux(decoded.isJalr, jalrTarget,
|
||||
Mux(decoded.isBranch && exec(i).io.branchTaken, branchTarget, decoded.pc + 4.U)))
|
||||
val isEcall = decoded.inst === "h00000073".U
|
||||
val isEbreak = decoded.inst === "h00100073".U
|
||||
val isMret = decoded.inst === "h30200073".U
|
||||
|
||||
val completeLoadResp = i.U === 0.U && loadRespValid
|
||||
completeValid(i) := (issueFire(i) && !decoded.isLoad) || completeLoadResp
|
||||
completeIdx(i) := Mux(completeLoadResp, Mux(forwardPending, forwardPendingRob, loadPendingRob), issue.io.out(i).robIdx)
|
||||
completeException(i) := (issueFire(i) && (decoded.illegal || isEcall || isEbreak || lq.io.violation)) ||
|
||||
(completeLoadResp && loadRespPageFault)
|
||||
completeCause(i) := Mux(completeLoadResp && loadRespPageFault, 13.U,
|
||||
Mux(issueFire(i) && isEbreak, 3.U,
|
||||
Mux(issueFire(i) && isEcall, 11.U,
|
||||
Mux(issueFire(i) && decoded.illegal, 2.U, 0.U))))
|
||||
completeBadAddr(i) := decoded.pc
|
||||
val completeLoadResp = i.U === 0.U && (loadRespValid || loadFaultNow)
|
||||
val completeStoreResp = (i.U === 0.U && storeCheckRespPending) ||
|
||||
(storeCheckRespNow && issueFire(i) && decoded.isStore)
|
||||
completeValid(i) := (issueFire(i) && !decoded.isLoad && !decoded.isStore) || completeLoadResp || completeStoreResp
|
||||
val storeCompleteIdx = Mux(storeCheckRespPending, storeCheckPendingRob, issue.io.out(i).robIdx)
|
||||
completeIdx(i) := Mux(completeStoreResp, storeCompleteIdx,
|
||||
Mux(completeLoadResp, Mux(loadFaultNow, issue.io.out(memSlot).robIdx, Mux(forwardPending, forwardPendingRob, loadPendingRob)),
|
||||
issue.io.out(i).robIdx))
|
||||
val issueException = issueRaisesException
|
||||
val thisStoreCheckFault = completeStoreResp && storeCheckFault
|
||||
completeException(i) := issueException || (completeLoadResp && (loadRespFault || loadFaultNow)) || thisStoreCheckFault
|
||||
completeCause(i) := Mux(thisStoreCheckFault || (completeLoadResp && (loadRespFault || loadFaultNow)), lsu.io.faultCause,
|
||||
Mux(issueFire(i) && decoded.fetchException, decoded.fetchExceptionCause,
|
||||
Mux(issueFire(i) && isEbreak, Privileged.CAUSE_BREAKPOINT,
|
||||
Mux(issueFire(i) && isEcall, ExceptionSource.ecallCause(io.currentPriv),
|
||||
Mux(storeMisaligned, Privileged.CAUSE_STORE_ADDR_MISALIGNED,
|
||||
Mux(controlTargetMisaligned, Privileged.CAUSE_INSTR_ADDR_MISALIGNED,
|
||||
Mux(issueFire(i) && illegalInst, Privileged.CAUSE_ILLEGAL_INSTRUCTION, 0.U)))))))
|
||||
completeBadAddr(i) := Mux(thisStoreCheckFault || (completeLoadResp && (loadRespFault || loadFaultNow)), lsu.io.faultAddr,
|
||||
Mux(storeMisaligned, dataAddr,
|
||||
Mux(issueFire(i) && decoded.fetchException, decoded.fetchExceptionTval,
|
||||
Mux(controlTargetMisaligned, controlTarget,
|
||||
Mux(issueFire(i) && illegalInst, decoded.inst.pad(p.xlen), 0.U)))))
|
||||
completeMispredict(i) := issueFire(i) &&
|
||||
(decoded.isJal || decoded.isJalr || isMret || decoded.isFenceI ||
|
||||
(decoded.isJal || decoded.isJalr || decoded.isXret || decoded.isFenceI || decoded.isSfenceVma || decoded.isWfi ||
|
||||
(decoded.isBranch && exec(i).io.branchTaken))
|
||||
completeRedirectPc(i) := Mux(isEcall || isEbreak, csr.io.mtvec, Mux(isMret, csr.io.mepc, branchRedirect))
|
||||
completeRedirectPc(i) := Mux(isEcall || isEbreak,
|
||||
csr.io.trapVector,
|
||||
Mux(decoded.isXret,
|
||||
PrivilegeTransitions.xretTargetPc(decoded.isMret, csr.io.mepc, csr.io.sepc),
|
||||
Mux(decoded.isWfi, decoded.pc + 4.U, branchRedirect)))
|
||||
completeCsrValid(i) := issueFire(i) && decoded.isSystem && decoded.funct3 =/= 0.U &&
|
||||
!(decoded.funct3(1) && decoded.rs1 === 0.U)
|
||||
!(decoded.funct3(1) && decoded.rs1 === 0.U) && !illegalInst
|
||||
completeCsrAddr(i) := decoded.inst(31, 20)
|
||||
completeCsrCmd(i) := decoded.funct3
|
||||
completeCsrRs1(i) := src1
|
||||
completeCsrZimm(i) := decoded.rs1
|
||||
completeFenceI(i) := issueFire(i) && decoded.isFenceI
|
||||
completeSfenceVma(i) := issueFire(i) && decoded.isSfenceVma
|
||||
completeXret(i) := issueFire(i) && decoded.isXret
|
||||
completeXretIsMret(i) := issueFire(i) && decoded.isMret
|
||||
}
|
||||
wakeupReg := wakeup
|
||||
|
||||
@@ -310,8 +452,16 @@ class OoOBackend(p: CoreParams = CoreParams()) extends Module {
|
||||
io.commitValid := VecInit((0 until p.issueWidth).map(i => rename.io.commitValid(i) && commit.io.commitReady(i)))
|
||||
io.commitEntry := rename.io.commitEntry
|
||||
io.flush := commit.io.flush
|
||||
io.redirectPc := Mux(commit.io.exception, csr.io.mtvec, commit.io.redirectPc)
|
||||
val xretRedirectPc = PrivilegeTransitions.xretTargetPc(commit.io.xretIsMret, csr.io.mepc, csr.io.sepc)
|
||||
dontTouch(xretRedirectPc)
|
||||
io.redirectPc := Mux(commit.io.exception, csr.io.trapVector,
|
||||
Mux(commit.io.xret, xretRedirectPc, commit.io.redirectPc))
|
||||
io.invalidateICache := commit.io.fenceI
|
||||
io.sfenceVma := commit.io.sfenceVma
|
||||
io.setPriv := commit.io.setPriv
|
||||
io.targetPriv := Mux(commit.io.exception,
|
||||
trapTargetPriv,
|
||||
Mux(commit.io.xret, PrivilegeTransitions.xretNextPriv(commit.io.xretIsMret, csr.io.mstatus), io.currentPriv))
|
||||
}
|
||||
|
||||
object OoOBackend extends App {
|
||||
|
||||
Reference in New Issue
Block a user