feat: implement privileged mode support

sim/tests/exception/MisalignedTest.scala

@@ -0,0 +1,3 @@
+// Verilator scenario checklist:
+// 1. Instruction fetch with pc[1:0] != 0 raises instruction address misaligned.
+// 2. Load/store addresses not aligned to access size raise load/store address misaligned.

sim/tests/exception/PageFaultTest.scala

@@ -0,0 +1,4 @@
+// Verilator scenario checklist:
+// 1. Unmapped instruction fetch raises instruction page fault.
+// 2. Unmapped load/store raises load/store page fault.
+// 3. U/S permission violations raise page fault instead of access fault.