feat: implement privileged mode support

sim/tests/EcallDelegationTest.scala

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+// Verilator scenario checklist:
+// 1. Set medeleg bit 8 and execute ecall from U-mode.
+// 2. Expect delegation to S-mode handler when S support is enabled.
+// 3. Clear delegation and verify ecall from U-mode traps to M-mode.

sim/tests/InterruptEnableTest.scala

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+// Verilator scenario checklist:
+// 1. Toggle MSI, MTI, and MEI pending sources.
+// 2. Verify enable bits gate interrupt injection.
+// 3. Verify MEI > MTI > MSI priority and S-mode delegation bits.

sim/tests/PrivilegeTransitionTest.scala

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+// Verilator scenario checklist:
+// 1. Start in M-mode after reset.
+// 2. Configure mstatus.MPP=S and mepc to an S-mode entry point.
+// 3. Execute mret and verify the redirected PC equals mepc.
+// 4. Execute an S-mode ecall path and verify trap state is recoverable.

sim/tests/SfenceTest.scala

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+// Verilator scenario checklist:
+// 1. sfence.vma in U-mode raises illegal instruction.
+// 2. sfence.vma in S/M-mode flushes DTLB state.
+// 3. fence.i invalidates ICache and flushes younger instructions.

sim/tests/XretFlushTest.scala

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+// Verilator scenario checklist:
+// 1. Execute mret and sret with younger instructions in flight.
+// 2. Verify commit emits flush and redirect.
+// 3. Verify younger side effects are squashed.

sim/tests/exception/MisalignedTest.scala

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+// Verilator scenario checklist:
+// 1. Instruction fetch with pc[1:0] != 0 raises instruction address misaligned.
+// 2. Load/store addresses not aligned to access size raise load/store address misaligned.

sim/tests/exception/PageFaultTest.scala

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+// Verilator scenario checklist:
+// 1. Unmapped instruction fetch raises instruction page fault.
+// 2. Unmapped load/store raises load/store page fault.
+// 3. U/S permission violations raise page fault instead of access fault.