feat: implement privileged mode support
This commit is contained in:
abnerhexu
93
sim/results/privileged_test_results.txt
Normal file
93
sim/results/privileged_test_results.txt
Normal file
@@ -0,0 +1,93 @@
|
||||
Running privileged RISC-V tests...
|
||||
=================================
|
||||
rv64mi-p-breakpoint: exit=0 PASS
|
||||
rv64mi-p-csr: exit=0 PASS
|
||||
rv64mi-p-illegal: exit=0 PASS
|
||||
rv64mi-p-instret_overflow: exit=1 FAIL
|
||||
[5] FLUSH exception=0 mtvec=0x0 mepc=0x0 mcause=0x0 frontend_pc=0x80000008
|
||||
[65] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x0
|
||||
[66] CSR commit slot0=1 slot1=0 addr=0x744 cmd=5 next=0x800000e8 mtvec=0x800000e8
|
||||
[71] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x800000e8
|
||||
[72] CSR commit slot0=1 slot1=0 addr=0x180 cmd=5 next=0x800000f8 mtvec=0x800000f8
|
||||
[77] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x800000f8
|
||||
[83] CSR commit slot0=1 slot1=0 addr=0x3b0 cmd=1 next=0x0 mtvec=0x8000011c
|
||||
[86] CSR commit slot0=1 slot1=0 addr=0x3a0 cmd=1 next=0x0 mtvec=0x8000011c
|
||||
[87] CSR commit slot0=1 slot1=0 addr=0x304 cmd=5 next=0x1f mtvec=0x8000011c
|
||||
[92] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x8000011c
|
||||
[93] CSR commit slot0=1 slot1=0 addr=0x302 cmd=5 next=0x80000134 mtvec=0x80000134
|
||||
[95] CSR commit slot0=1 slot1=0 addr=0x303 cmd=5 next=0x0 mtvec=0x80000134
|
||||
[101] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x80000134
|
||||
[105] FLUSH exception=0 mtvec=0x80000004 mepc=0x0 mcause=0x0 frontend_pc=0x80000158
|
||||
[114] FLUSH exception=0 mtvec=0x80000004 mepc=0x0 mcause=0x0 frontend_pc=0x80000170
|
||||
[120] CSR commit slot0=1 slot1=0 addr=0x300 cmd=5 next=0x0 mtvec=0x80000004
|
||||
[126] CSR commit slot0=1 slot1=0 addr=0x300 cmd=2 next=0x0 mtvec=0x80000004
|
||||
[130] CSR commit slot0=1 slot1=0 addr=0x341 cmd=1 next=0x0 mtvec=0x80000004
|
||||
[133] FLUSH exception=0 mtvec=0x80000004 mepc=0x800001a0 mcause=0x0 frontend_pc=0x800001a8
|
||||
[141] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x80000004
|
||||
[142] FLUSH exception=1 mtvec=0x800001b0 mepc=0x800001a0 mcause=0x0 frontend_pc=0x800001b8
|
||||
[147] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x800001b0
|
||||
[150] FLUSH exception=1 mtvec=0x80000004 mepc=0x800001ac mcause=0x2 frontend_pc=0x800001c0
|
||||
[171] FLUSH exception=0 mtvec=0x80000004 mepc=0x800001b8 mcause=0x2 frontend_pc=0x80000038
|
||||
[177] FLUSH exception=0 mtvec=0x80000004 mepc=0x800001b8 mcause=0x2 frontend_pc=0x80000200
|
||||
[193] FLUSH exception=1 mtvec=0x80000004 mepc=0x800001b8 mcause=0x2 frontend_pc=0x800001f0
|
||||
[205] FLUSH exception=0 mtvec=0x80000004 mepc=0x800001e4 mcause=0xb frontend_pc=0x80000028
|
||||
[213] STORE addr=0x80001000 data=0x5 size=2
|
||||
Loaded segment: paddr=0x80000000 size=576
|
||||
Loaded segment: paddr=0x80001000 size=72
|
||||
ELF loaded: entry=0x80000000
|
||||
[213] TEST FAILED: error code 2
|
||||
rv64mi-p-ld-misaligned: exit=0 PASS
|
||||
rv64mi-p-lh-misaligned: exit=0 PASS
|
||||
rv64mi-p-lw-misaligned: exit=0 PASS
|
||||
rv64mi-p-ma_addr: exit=0 PASS
|
||||
rv64mi-p-ma_fetch: exit=0 PASS
|
||||
rv64mi-p-mcsr: exit=1 FAIL
|
||||
[5] FLUSH exception=0 mtvec=0x0 mepc=0x0 mcause=0x0 frontend_pc=0x80000008
|
||||
[63] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x0
|
||||
[65] CSR commit slot0=1 slot1=0 addr=0x744 cmd=5 next=0x0 mtvec=0x800000e4
|
||||
[69] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x800000e4
|
||||
[71] CSR commit slot0=1 slot1=0 addr=0x180 cmd=5 next=0x0 mtvec=0x800000f4
|
||||
[75] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x800000f4
|
||||
[81] CSR commit slot0=1 slot1=0 addr=0x3b0 cmd=1 next=0x0 mtvec=0x80000118
|
||||
[84] CSR commit slot0=1 slot1=0 addr=0x3a0 cmd=1 next=0x0 mtvec=0x80000118
|
||||
[86] CSR commit slot0=1 slot1=0 addr=0x304 cmd=5 next=0x0 mtvec=0x80000118
|
||||
[90] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x80000118
|
||||
[92] CSR commit slot0=1 slot1=0 addr=0x302 cmd=5 next=0x0 mtvec=0x80000130
|
||||
[93] CSR commit slot0=1 slot1=0 addr=0x303 cmd=5 next=0x0 mtvec=0x80000130
|
||||
[99] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x80000130
|
||||
[104] FLUSH exception=0 mtvec=0x80000004 mepc=0x0 mcause=0x0 frontend_pc=0x80000150
|
||||
[111] FLUSH exception=0 mtvec=0x80000004 mepc=0x0 mcause=0x0 frontend_pc=0x80000170
|
||||
[117] CSR commit slot0=1 slot1=0 addr=0x300 cmd=5 next=0x0 mtvec=0x80000004
|
||||
[121] CSR commit slot0=1 slot1=0 addr=0x300 cmd=2 next=0x0 mtvec=0x80000004
|
||||
[126] CSR commit slot0=1 slot1=0 addr=0x341 cmd=1 next=0x0 mtvec=0x80000004
|
||||
[129] FLUSH exception=0 mtvec=0x80000004 mepc=0x8000019c mcause=0x0 frontend_pc=0x800001a0
|
||||
[149] FLUSH exception=1 mtvec=0x80000004 mepc=0x8000019c mcause=0x0 frontend_pc=0x800001c8
|
||||
[167] FLUSH exception=0 mtvec=0x80000004 mepc=0x800001c0 mcause=0x2 frontend_pc=0x80000030
|
||||
[175] FLUSH exception=0 mtvec=0x80000004 mepc=0x800001c0 mcause=0x2 frontend_pc=0x80000038
|
||||
[185] STORE addr=0x80001000 data=0x53b size=2
|
||||
Loaded segment: paddr=0x80000000 size=572
|
||||
Loaded segment: paddr=0x80001000 size=72
|
||||
ELF loaded: entry=0x80000000
|
||||
[185] TEST FAILED: error code 669
|
||||
rv64mi-p-pmpaddr: exit=0 PASS
|
||||
rv64mi-p-sbreak: exit=0 PASS
|
||||
rv64mi-p-scall: exit=0 PASS
|
||||
rv64mi-p-sd-misaligned: exit=0 PASS
|
||||
rv64mi-p-sh-misaligned: exit=0 PASS
|
||||
rv64mi-p-sw-misaligned: exit=0 PASS
|
||||
rv64mi-p-zicntr: exit=0 PASS
|
||||
rv64si-p-csr: exit=0 PASS
|
||||
rv64si-p-dirty: exit=124 TIMEOUT
|
||||
rv64si-p-icache-alias: exit=124 TIMEOUT
|
||||
rv64si-p-ma_fetch: exit=0 PASS
|
||||
rv64si-p-sbreak: exit=0 PASS
|
||||
rv64si-p-scall: exit=0 PASS
|
||||
rv64si-p-wfi: exit=0 PASS
|
||||
rv64ui-p-fence_i: exit=0 PASS
|
||||
|
||||
=================================
|
||||
Summary:
|
||||
PASS: 21
|
||||
FAIL: 2
|
||||
TIMEOUT: 2
|
||||
TOTAL: 25
|
||||
95
sim/results/test_results.txt
Normal file
95
sim/results/test_results.txt
Normal file
@@ -0,0 +1,95 @@
|
||||
Running RISC-V tests...
|
||||
====================
|
||||
rv64ui-p-add: PASS
|
||||
rv64ui-p-addi: PASS
|
||||
rv64ui-p-addiw: PASS
|
||||
rv64ui-p-addw: PASS
|
||||
rv64ui-p-and: PASS
|
||||
rv64ui-p-andi: PASS
|
||||
rv64ui-p-auipc: PASS
|
||||
rv64ui-p-beq: PASS
|
||||
rv64ui-p-bge: PASS
|
||||
rv64ui-p-bgeu: PASS
|
||||
rv64ui-p-blt: PASS
|
||||
rv64ui-p-bltu: PASS
|
||||
rv64ui-p-bne: PASS
|
||||
rv64ui-p-fence_i: PASS
|
||||
rv64ui-p-jal: PASS
|
||||
rv64ui-p-jalr: PASS
|
||||
rv64ui-p-lb: PASS
|
||||
rv64ui-p-lbu: PASS
|
||||
rv64ui-p-ld: PASS
|
||||
rv64ui-p-ld_st: PASS
|
||||
rv64ui-p-lh: PASS
|
||||
rv64ui-p-lhu: PASS
|
||||
rv64ui-p-lui: PASS
|
||||
rv64ui-p-lw: PASS
|
||||
rv64ui-p-lwu: PASS
|
||||
rv64ui-p-ma_data: FAIL
|
||||
rv64ui-p-or: PASS
|
||||
rv64ui-p-ori: PASS
|
||||
rv64ui-p-sb: PASS
|
||||
rv64ui-p-sd: PASS
|
||||
rv64ui-p-sh: PASS
|
||||
rv64ui-p-simple: PASS
|
||||
rv64ui-p-sll: PASS
|
||||
rv64ui-p-slli: PASS
|
||||
rv64ui-p-slliw: PASS
|
||||
rv64ui-p-sllw: PASS
|
||||
rv64ui-p-slt: PASS
|
||||
rv64ui-p-slti: PASS
|
||||
rv64ui-p-sltiu: PASS
|
||||
rv64ui-p-sltu: PASS
|
||||
rv64ui-p-sra: PASS
|
||||
rv64ui-p-srai: PASS
|
||||
rv64ui-p-sraiw: PASS
|
||||
rv64ui-p-sraw: PASS
|
||||
rv64ui-p-srl: PASS
|
||||
rv64ui-p-srli: PASS
|
||||
rv64ui-p-srliw: PASS
|
||||
rv64ui-p-srlw: PASS
|
||||
rv64ui-p-st_ld: PASS
|
||||
rv64ui-p-sub: PASS
|
||||
rv64ui-p-subw: PASS
|
||||
rv64ui-p-sw: PASS
|
||||
rv64ui-p-xor: PASS
|
||||
rv64ui-p-xori: PASS
|
||||
rv64um-p-div: PASS
|
||||
rv64um-p-divu: PASS
|
||||
rv64um-p-divuw: PASS
|
||||
rv64um-p-divw: PASS
|
||||
rv64um-p-mul: PASS
|
||||
rv64um-p-mulh: PASS
|
||||
rv64um-p-mulhsu: PASS
|
||||
rv64um-p-mulhu: PASS
|
||||
rv64um-p-mulw: PASS
|
||||
rv64um-p-rem: PASS
|
||||
rv64um-p-remu: PASS
|
||||
rv64um-p-remuw: PASS
|
||||
rv64um-p-remw: PASS
|
||||
rv64ua-p-amoadd_d: PASS
|
||||
rv64ua-p-amoadd_w: PASS
|
||||
rv64ua-p-amoand_d: PASS
|
||||
rv64ua-p-amoand_w: PASS
|
||||
rv64ua-p-amomax_d: PASS
|
||||
rv64ua-p-amomaxu_d: PASS
|
||||
rv64ua-p-amomaxu_w: PASS
|
||||
rv64ua-p-amomax_w: PASS
|
||||
rv64ua-p-amomin_d: PASS
|
||||
rv64ua-p-amominu_d: PASS
|
||||
rv64ua-p-amominu_w: PASS
|
||||
rv64ua-p-amomin_w: PASS
|
||||
rv64ua-p-amoor_d: PASS
|
||||
rv64ua-p-amoor_w: PASS
|
||||
rv64ua-p-amoswap_d: PASS
|
||||
rv64ua-p-amoswap_w: PASS
|
||||
rv64ua-p-amoxor_d: PASS
|
||||
rv64ua-p-amoxor_w: PASS
|
||||
rv64ua-p-lrsc: PASS
|
||||
|
||||
====================
|
||||
Summary:
|
||||
PASS: 85
|
||||
FAIL: 1
|
||||
TIMEOUT: 0
|
||||
TOTAL: 86
|
||||
Reference in New Issue
Block a user