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feat: implement privileged mode support

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This commit is contained in:
abnerhexu
2026-06-29 07:00:55 +00:00
parent a32db39c80
commit b6afa61e66
89 changed files with 49571 additions and 43647 deletions
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106
generated-ooo/RenameStage.sv
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@@ -30,11 +30,21 @@ module RenameStage(
io_in_0_isWord,
io_in_0_isSystem,
io_in_0_isFenceI,
io_in_0_isEcall,
io_in_0_isEbreak,
io_in_0_isMret,
io_in_0_isSret,
io_in_0_isSfenceVma,
io_in_0_isXret,
io_in_0_isWfi,
io_in_0_isAmo,
input [4:0] io_in_0_amoOp,
input io_in_0_writesRd,
io_in_0_illegal,
input [63:0] io_in_1_pc,
io_in_0_fetchException,
input [63:0] io_in_0_fetchExceptionCause,
io_in_0_fetchExceptionTval,
io_in_1_pc,
input [31:0] io_in_1_inst,
input [4:0] io_in_1_rs1,
io_in_1_rs2,
@@ -60,10 +70,20 @@ module RenameStage(
io_in_1_isWord,
io_in_1_isSystem,
io_in_1_isFenceI,
io_in_1_isEcall,
io_in_1_isEbreak,
io_in_1_isMret,
io_in_1_isSret,
io_in_1_isSfenceVma,
io_in_1_isXret,
io_in_1_isWfi,
io_in_1_isAmo,
input [4:0] io_in_1_amoOp,
input io_in_1_writesRd,
io_in_1_illegal,
io_in_1_fetchException,
input [63:0] io_in_1_fetchExceptionCause,
io_in_1_fetchExceptionTval,
output io_outValid_0,
io_outValid_1,
output [63:0] io_out_0_decoded_pc,
@@ -90,10 +110,20 @@ module RenameStage(
io_out_0_decoded_isWord,
io_out_0_decoded_isSystem,
io_out_0_decoded_isFenceI,
io_out_0_decoded_isEcall,
io_out_0_decoded_isEbreak,
io_out_0_decoded_isMret,
io_out_0_decoded_isSret,
io_out_0_decoded_isSfenceVma,
io_out_0_decoded_isXret,
io_out_0_decoded_isWfi,
io_out_0_decoded_isAmo,
output [4:0] io_out_0_decoded_amoOp,
output io_out_0_decoded_writesRd,
io_out_0_decoded_illegal,
io_out_0_decoded_fetchException,
output [63:0] io_out_0_decoded_fetchExceptionCause,
io_out_0_decoded_fetchExceptionTval,
output [5:0] io_out_0_prs1,
io_out_0_prs2,
output io_out_0_src1Ready,
@@ -124,10 +154,20 @@ module RenameStage(
io_out_1_decoded_isWord,
io_out_1_decoded_isSystem,
io_out_1_decoded_isFenceI,
io_out_1_decoded_isEcall,
io_out_1_decoded_isEbreak,
io_out_1_decoded_isMret,
io_out_1_decoded_isSret,
io_out_1_decoded_isSfenceVma,
io_out_1_decoded_isXret,
io_out_1_decoded_isWfi,
io_out_1_decoded_isAmo,
output [4:0] io_out_1_decoded_amoOp,
output io_out_1_decoded_writesRd,
io_out_1_decoded_illegal,
io_out_1_decoded_fetchException,
output [63:0] io_out_1_decoded_fetchExceptionCause,
io_out_1_decoded_fetchExceptionTval,
output [5:0] io_out_1_prs1,
io_out_1_prs2,
output io_out_1_src1Ready,
@@ -163,11 +203,21 @@ module RenameStage(
io_completeCsrRs1_1,
input [4:0] io_completeCsrZimm_0,
io_completeCsrZimm_1,
input io_commitReady_0,
input io_completeFenceI_0,
io_completeFenceI_1,
io_completeSfenceVma_0,
io_completeSfenceVma_1,
io_completeXret_0,
io_completeXret_1,
io_completeXretIsMret_0,
io_completeXretIsMret_1,
io_commitReady_0,
io_commitReady_1,
output io_commitValid_0,
io_commitValid_1,
io_commitEntry_0_valid,
output [5:0] io_commitEntry_0_robIdx,
output [63:0] io_commitEntry_0_pc,
output [4:0] io_commitEntry_0_archDest,
output io_commitEntry_0_writesDest,
output [3:0] io_commitEntry_0_opClass,
@@ -184,7 +234,11 @@ module RenameStage(
output [63:0] io_commitEntry_0_csrRs1,
output [4:0] io_commitEntry_0_csrZimm,
output io_commitEntry_0_fenceI,
io_commitEntry_0_sfenceVma,
io_commitEntry_0_xret,
io_commitEntry_0_xretIsMret,
output [5:0] io_commitEntry_1_robIdx,
output [63:0] io_commitEntry_1_pc,
output [4:0] io_commitEntry_1_archDest,
output io_commitEntry_1_writesDest,
output [3:0] io_commitEntry_1_opClass,
@@ -201,6 +255,9 @@ module RenameStage(
output [63:0] io_commitEntry_1_csrRs1,
output [4:0] io_commitEntry_1_csrZimm,
output io_commitEntry_1_fenceI,
io_commitEntry_1_sfenceVma,
io_commitEntry_1_xret,
io_commitEntry_1_xretIsMret,
input io_commitMapValid_0,
io_commitMapValid_1,
input [4:0] io_commitArch_0,
@@ -893,18 +950,26 @@ module RenameStage(
.reset (reset),
.io_allocateValid_0 (e_valid),
.io_allocateValid_1 (e_1_valid),
.io_allocateEntry_0_pc (io_in_0_pc),
.io_allocateEntry_0_archDest (io_in_0_rd),
.io_allocateEntry_0_writesDest (io_in_0_writesRd),
.io_allocateEntry_0_opClass (io_in_0_opClass),
.io_allocateEntry_0_dest (e_dest),
.io_allocateEntry_0_oldDest (_table_io_oldPrd_0),
.io_allocateEntry_0_fenceI (io_in_0_isFenceI),
.io_allocateEntry_0_sfenceVma (io_in_0_isSfenceVma),
.io_allocateEntry_0_xret (io_in_0_isXret),
.io_allocateEntry_0_xretIsMret (io_in_0_isMret),
.io_allocateEntry_1_pc (io_in_1_pc),
.io_allocateEntry_1_archDest (io_in_1_rd),
.io_allocateEntry_1_writesDest (io_in_1_writesRd),
.io_allocateEntry_1_opClass (io_in_1_opClass),
.io_allocateEntry_1_dest (e_1_dest),
.io_allocateEntry_1_oldDest (_table_io_oldPrd_1),
.io_allocateEntry_1_fenceI (io_in_1_isFenceI),
.io_allocateEntry_1_sfenceVma (io_in_1_isSfenceVma),
.io_allocateEntry_1_xret (io_in_1_isXret),
.io_allocateEntry_1_xretIsMret (io_in_1_isMret),
.io_allocateIdx_0 (io_out_0_robIdx),
.io_allocateIdx_1 (io_out_1_robIdx),
.io_canAllocate (_rob_io_canAllocate),
@@ -932,9 +997,19 @@ module RenameStage(
.io_completeCsrRs1_1 (io_completeCsrRs1_1),
.io_completeCsrZimm_0 (io_completeCsrZimm_0),
.io_completeCsrZimm_1 (io_completeCsrZimm_1),
.io_completeFenceI_0 (io_completeFenceI_0),
.io_completeFenceI_1 (io_completeFenceI_1),
.io_completeSfenceVma_0 (io_completeSfenceVma_0),
.io_completeSfenceVma_1 (io_completeSfenceVma_1),
.io_completeXret_0 (io_completeXret_0),
.io_completeXret_1 (io_completeXret_1),
.io_completeXretIsMret_0 (io_completeXretIsMret_0),
.io_completeXretIsMret_1 (io_completeXretIsMret_1),
.io_commitValid_0 (io_commitValid_0),
.io_commitValid_1 (io_commitValid_1),
.io_commit_0_valid (io_commitEntry_0_valid),
.io_commit_0_robIdx (io_commitEntry_0_robIdx),
.io_commit_0_pc (io_commitEntry_0_pc),
.io_commit_0_archDest (io_commitEntry_0_archDest),
.io_commit_0_writesDest (io_commitEntry_0_writesDest),
.io_commit_0_opClass (io_commitEntry_0_opClass),
@@ -951,7 +1026,11 @@ module RenameStage(
.io_commit_0_csrRs1 (io_commitEntry_0_csrRs1),
.io_commit_0_csrZimm (io_commitEntry_0_csrZimm),
.io_commit_0_fenceI (io_commitEntry_0_fenceI),
.io_commit_0_sfenceVma (io_commitEntry_0_sfenceVma),
.io_commit_0_xret (io_commitEntry_0_xret),
.io_commit_0_xretIsMret (io_commitEntry_0_xretIsMret),
.io_commit_1_robIdx (io_commitEntry_1_robIdx),
.io_commit_1_pc (io_commitEntry_1_pc),
.io_commit_1_archDest (io_commitEntry_1_archDest),
.io_commit_1_writesDest (io_commitEntry_1_writesDest),
.io_commit_1_opClass (io_commitEntry_1_opClass),
@@ -968,6 +1047,9 @@ module RenameStage(
.io_commit_1_csrRs1 (io_commitEntry_1_csrRs1),
.io_commit_1_csrZimm (io_commitEntry_1_csrZimm),
.io_commit_1_fenceI (io_commitEntry_1_fenceI),
.io_commit_1_sfenceVma (io_commitEntry_1_sfenceVma),
.io_commit_1_xret (io_commitEntry_1_xret),
.io_commit_1_xretIsMret (io_commitEntry_1_xretIsMret),
.io_commitReady_0 (io_commitReady_0),
.io_commitReady_1 (io_commitReady_1),
.io_flush (io_flush)
@@ -998,10 +1080,20 @@ module RenameStage(
assign io_out_0_decoded_isWord = io_in_0_isWord;
assign io_out_0_decoded_isSystem = io_in_0_isSystem;
assign io_out_0_decoded_isFenceI = io_in_0_isFenceI;
assign io_out_0_decoded_isEcall = io_in_0_isEcall;
assign io_out_0_decoded_isEbreak = io_in_0_isEbreak;
assign io_out_0_decoded_isMret = io_in_0_isMret;
assign io_out_0_decoded_isSret = io_in_0_isSret;
assign io_out_0_decoded_isSfenceVma = io_in_0_isSfenceVma;
assign io_out_0_decoded_isXret = io_in_0_isXret;
assign io_out_0_decoded_isWfi = io_in_0_isWfi;
assign io_out_0_decoded_isAmo = io_in_0_isAmo;
assign io_out_0_decoded_amoOp = io_in_0_amoOp;
assign io_out_0_decoded_writesRd = io_in_0_writesRd;
assign io_out_0_decoded_illegal = io_in_0_illegal;
assign io_out_0_decoded_fetchException = io_in_0_fetchException;
assign io_out_0_decoded_fetchExceptionCause = io_in_0_fetchExceptionCause;
assign io_out_0_decoded_fetchExceptionTval = io_in_0_fetchExceptionTval;
assign io_out_0_prs1 = _table_io_prs1_0;
assign io_out_0_prs2 = _table_io_prs2_0;
assign io_out_0_src1Ready =
@@ -1039,10 +1131,20 @@ module RenameStage(
assign io_out_1_decoded_isWord = io_in_1_isWord;
assign io_out_1_decoded_isSystem = io_in_1_isSystem;
assign io_out_1_decoded_isFenceI = io_in_1_isFenceI;
assign io_out_1_decoded_isEcall = io_in_1_isEcall;
assign io_out_1_decoded_isEbreak = io_in_1_isEbreak;
assign io_out_1_decoded_isMret = io_in_1_isMret;
assign io_out_1_decoded_isSret = io_in_1_isSret;
assign io_out_1_decoded_isSfenceVma = io_in_1_isSfenceVma;
assign io_out_1_decoded_isXret = io_in_1_isXret;
assign io_out_1_decoded_isWfi = io_in_1_isWfi;
assign io_out_1_decoded_isAmo = io_in_1_isAmo;
assign io_out_1_decoded_amoOp = io_in_1_amoOp;
assign io_out_1_decoded_writesRd = io_in_1_writesRd;
assign io_out_1_decoded_illegal = io_in_1_illegal;
assign io_out_1_decoded_fetchException = io_in_1_fetchException;
assign io_out_1_decoded_fetchExceptionCause = io_in_1_fetchExceptionCause;
assign io_out_1_decoded_fetchExceptionTval = io_in_1_fetchExceptionTval;
assign io_out_1_prs1 = _table_io_prs1_1;
assign io_out_1_prs2 = _table_io_prs2_1;
assign io_out_1_src1Ready =