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feat: implement privileged mode support

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This commit is contained in:
abnerhexu
2026-06-29 07:00:55 +00:00
parent a32db39c80
commit b6afa61e66
89 changed files with 49571 additions and 43647 deletions
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26
generated-ooo/ICache.sv
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@@ -2,6 +2,7 @@
module ICache(
input clock,
reset,
io_reqValid,
input [63:0] io_reqAddr,
io_reqPc,
input io_flush,
@@ -17,7 +18,10 @@ module ICache(
output [31:0] io_resp_inst_0,
io_resp_inst_1,
output io_resp_laneValid_0,
io_resp_laneValid_1
io_resp_laneValid_1,
io_resp_exception,
output [63:0] io_resp_exceptionCause,
io_resp_exceptionTval
);
wire [31:0] dataWrite_3_1;
@@ -9295,8 +9299,9 @@ module ICache(
reg [31:0] respReg_inst_1;
reg respReg_laneValid_0;
reg respReg_laneValid_1;
reg respReg_exception;
wire _readFire_T = state == 2'h0;
wire readFire = _readFire_T & ~io_flush;
wire readFire = _readFire_T & io_reqValid & ~io_flush;
wire tagHitVec_0 =
(|{lookupValidRow_0_1, lookupValidRow_0_0})
& _tags_ext_R0_data[50:0] == lookupAddr[63:13];
@@ -38132,7 +38137,7 @@ module ICache(
{{_GEN_18 ? _GEN_2082 : state},
{io_respReady ? 2'h0 : state},
{(|_hitWay_T) ? _GEN_2082 : 2'h3},
{2'h1}};
{io_reqValid ? 2'h1 : state}};
state <= _GEN_2083[state];
end
missReqSent <=
@@ -38143,7 +38148,7 @@ module ICache(
? (|_hitWay_T) & missReqSent
: ~_io_resp_T & (&state) & ~missReqSent | missReqSent);
end
if (_GEN_16 | ~_readFire_T) begin
if (_GEN_16 | ~(_readFire_T & io_reqValid)) begin
end
else begin
automatic logic [1023:0] _GEN_2084 =
@@ -47420,8 +47425,12 @@ module ICache(
missValidRow_3_1 <= lookupValidRow_3_1;
end
if (~_GEN_17) begin
automatic logic _GEN_2093;
automatic logic _GEN_2094;
_GEN_2093 = ~(|_hitWay_T) | io_respReady;
_GEN_2094 = _io_resp_T | ~_GEN_18 | io_respReady;
if (_io_miss_T) begin
if (~(|_hitWay_T) | io_respReady) begin
if (_GEN_2093) begin
end
else begin
respReg_pc <= lookupPc;
@@ -47430,7 +47439,7 @@ module ICache(
respReg_laneValid_1 <= lookupLane1Valid;
end
end
else if (_io_resp_T | ~_GEN_18 | io_respReady) begin
else if (_GEN_2094) begin
end
else begin
respReg_pc <= missPc;
@@ -47442,6 +47451,8 @@ module ICache(
_io_miss_T
? (|_hitWay_T) & ~io_respReady | respReg_laneValid_0
: ~_io_resp_T & _GEN_18 & ~io_respReady | respReg_laneValid_0;
respReg_exception <=
_io_miss_T ? _GEN_2093 & respReg_exception : _GEN_2094 & respReg_exception;
end
end // always @(posedge)
tags_1024x204 tags_ext (
@@ -47487,5 +47498,8 @@ module ICache(
assign io_resp_laneValid_0 = ~_io_resp_T | respReg_laneValid_0;
assign io_resp_laneValid_1 =
_io_resp_T ? respReg_laneValid_1 : _io_resp_T_2 ? ~missInst : lookupLane1Valid;
assign io_resp_exception = _io_resp_T & respReg_exception;
assign io_resp_exceptionCause = 64'h0;
assign io_resp_exceptionTval = 64'h0;
endmodule