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feat: implement privileged mode support

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This commit is contained in:
abnerhexu
2026-06-29 07:00:55 +00:00
parent a32db39c80
commit b6afa61e66
89 changed files with 49571 additions and 43647 deletions
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56
generated-ooo/CommitStage.sv
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@@ -2,6 +2,7 @@
module CommitStage(
input io_robValid_0,
io_robValid_1,
input [63:0] io_robEntry_0_pc,
input [4:0] io_robEntry_0_archDest,
input io_robEntry_0_writesDest,
input [3:0] io_robEntry_0_opClass,
@@ -14,6 +15,10 @@ module CommitStage(
input [63:0] io_robEntry_0_redirectPc,
input io_robEntry_0_csrValid,
io_robEntry_0_fenceI,
io_robEntry_0_sfenceVma,
io_robEntry_0_xret,
io_robEntry_0_xretIsMret,
input [63:0] io_robEntry_1_pc,
input [4:0] io_robEntry_1_archDest,
input io_robEntry_1_writesDest,
input [5:0] io_robEntry_1_dest,
@@ -25,6 +30,9 @@ module CommitStage(
input [63:0] io_robEntry_1_redirectPc,
input io_robEntry_1_csrValid,
io_robEntry_1_fenceI,
io_robEntry_1_sfenceVma,
io_robEntry_1_xret,
io_robEntry_1_xretIsMret,
output io_commitReady_0,
io_commitReady_1,
io_freeOldPhys_0,
@@ -42,38 +50,53 @@ module CommitStage(
output io_exception,
output [63:0] io_exceptionCause,
io_badAddr,
output io_fenceI
io_trapPc,
output io_fenceI,
io_sfenceVma,
io_xret,
io_xretIsMret,
io_setPriv
);
wire firstTrap =
io_robValid_0 & (io_robEntry_0_exception | io_robEntry_0_branchMispredict);
io_robValid_0
& (io_robEntry_0_exception | io_robEntry_0_branchMispredict | io_robEntry_0_xret
| io_robEntry_0_sfenceVma | io_robEntry_0_fenceI);
wire secondTrap =
io_robValid_1 & (io_robEntry_1_exception | io_robEntry_1_branchMispredict);
io_robValid_1
& (io_robEntry_1_exception | io_robEntry_1_branchMispredict | io_robEntry_1_xret
| io_robEntry_1_sfenceVma | io_robEntry_1_fenceI);
wire io_commitReady_1_0 =
io_robValid_1 & ~firstTrap & ~secondTrap
& ~(io_robValid_0 & io_robValid_1 & io_robEntry_0_csrValid & io_robEntry_1_csrValid)
& ~(io_robValid_0 & io_robEntry_0_opClass == 4'h4);
wire _io_commitMapValid_0_T = io_robValid_0 & io_robEntry_0_writesDest;
wire _io_commitMapValid_1_T = io_commitReady_1_0 & io_robEntry_1_writesDest;
wire commitWritesDest =
io_robValid_0 & ~io_robEntry_0_exception & io_robEntry_0_writesDest;
wire commitWritesDest_1 =
io_commitReady_1_0 & ~io_robEntry_1_exception & io_robEntry_1_writesDest;
wire secondTrapSelected = ~io_robValid_0 & secondTrap;
wire selectedTrap = firstTrap | secondTrapSelected;
wire io_exception_0 =
firstTrap ? io_robEntry_0_exception : secondTrapSelected & io_robEntry_1_exception;
wire io_xret_0 =
io_robValid_0 & io_robEntry_0_xret | io_commitReady_1_0 & io_robEntry_1_xret;
assign io_commitReady_0 = io_robValid_0;
assign io_commitReady_1 = io_commitReady_1_0;
assign io_freeOldPhys_0 =
_io_commitMapValid_0_T & io_robEntry_0_oldDest != io_robEntry_0_dest;
commitWritesDest & io_robEntry_0_oldDest != io_robEntry_0_dest;
assign io_freeOldPhys_1 =
_io_commitMapValid_1_T & io_robEntry_1_oldDest != io_robEntry_1_dest;
commitWritesDest_1 & io_robEntry_1_oldDest != io_robEntry_1_dest;
assign io_oldPhys_0 = io_robEntry_0_oldDest;
assign io_oldPhys_1 = io_robEntry_1_oldDest;
assign io_commitMapValid_0 = _io_commitMapValid_0_T & (|io_robEntry_0_archDest);
assign io_commitMapValid_1 = _io_commitMapValid_1_T & (|io_robEntry_1_archDest);
assign io_commitMapValid_0 = commitWritesDest & (|io_robEntry_0_archDest);
assign io_commitMapValid_1 = commitWritesDest_1 & (|io_robEntry_1_archDest);
assign io_commitArch_0 = io_robEntry_0_archDest;
assign io_commitArch_1 = io_robEntry_1_archDest;
assign io_commitPhys_0 = io_robEntry_0_dest;
assign io_commitPhys_1 = io_robEntry_1_dest;
assign io_flush = firstTrap | secondTrapSelected;
assign io_flush = selectedTrap;
assign io_redirectPc = firstTrap ? io_robEntry_0_redirectPc : io_robEntry_1_redirectPc;
assign io_exception =
firstTrap ? io_robEntry_0_exception : secondTrapSelected & io_robEntry_1_exception;
assign io_exception = io_exception_0;
assign io_exceptionCause =
firstTrap
? io_robEntry_0_exceptionCause
@@ -82,7 +105,16 @@ module CommitStage(
firstTrap
? io_robEntry_0_badAddr
: secondTrapSelected ? io_robEntry_1_badAddr : 64'h0;
assign io_trapPc =
firstTrap ? io_robEntry_0_pc : secondTrapSelected ? io_robEntry_1_pc : 64'h0;
assign io_fenceI =
io_robValid_0 & io_robEntry_0_fenceI | io_commitReady_1_0 & io_robEntry_1_fenceI;
assign io_sfenceVma =
io_robValid_0 & io_robEntry_0_sfenceVma | io_commitReady_1_0
& io_robEntry_1_sfenceVma;
assign io_xret = io_xret_0;
assign io_xretIsMret =
firstTrap ? io_robEntry_0_xretIsMret : ~secondTrapSelected | io_robEntry_1_xretIsMret;
assign io_setPriv = selectedTrap & (io_exception_0 | io_xret_0);
endmodule