feat: implement privileged mode support
This commit is contained in:
abnerhexu
@@ -8,37 +8,203 @@ module CSRFile(
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input [63:0] io_cmd_rs1,
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input [4:0] io_cmd_zimm,
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input [11:0] io_readAddr,
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input [1:0] io_currentPriv,
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output [63:0] io_rdata,
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output io_readIllegal,
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input io_trap,
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input [63:0] io_trapPc,
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io_trapCause,
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io_trapTval,
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input [1:0] io_trapTargetPriv,
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output [63:0] io_trapVector,
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input io_xret,
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io_xretIsMret,
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output [63:0] io_satp,
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io_mtvec,
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io_mepc
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io_mepc,
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io_sepc,
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io_medeleg,
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io_mstatus
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);
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reg [63:0] cycle;
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reg [63:0] mstatus;
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reg [63:0] mtvecReg;
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reg [63:0] mepcReg;
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reg [63:0] mcause;
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reg [63:0] mtval;
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reg [63:0] medeleg;
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reg [63:0] mideleg;
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reg [63:0] mie;
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reg [63:0] mip;
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reg [63:0] sstatus;
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reg [63:0] stvec;
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reg [63:0] sepc;
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reg [63:0] scause;
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reg [63:0] stval;
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reg [63:0] sscratch;
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reg [63:0] satpReg;
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reg [63:0] cycle;
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reg [63:0] instret;
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reg [63:0] mcountinhibit;
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reg suppressInstretAfterWrite;
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reg [63:0] mstatus;
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reg [63:0] mtvecReg;
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reg [63:0] mscratch;
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reg [63:0] mepcReg;
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reg [63:0] mcause;
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reg [63:0] mtval;
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reg [63:0] medeleg;
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reg [63:0] mideleg;
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reg [63:0] mie;
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reg [63:0] mip;
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reg [63:0] mcounteren;
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reg [63:0] pmpcfg0;
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reg [63:0] pmpaddr0;
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reg [63:0] tdata1;
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reg [63:0] tdata2;
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reg [63:0] tcontrol;
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reg [63:0] mnstatus;
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reg [63:0] scounteren;
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reg [63:0] stvec;
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reg [63:0] sepc;
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reg [63:0] scause;
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reg [63:0] stval;
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reg [63:0] sscratch;
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reg [63:0] satpReg;
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wire _readAllowed_T_75 = io_readAddr == 12'h300;
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wire _readAllowed_T_76 = io_readAddr == 12'h301;
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wire _readAllowed_T_78 = io_readAddr == 12'h302;
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wire _readAllowed_T_80 = io_readAddr == 12'h303;
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wire _readAllowed_T_82 = io_readAddr == 12'h304;
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wire _readAllowed_T_84 = io_readAddr == 12'h305;
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wire _readAllowed_T_86 = io_readAddr == 12'h306;
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wire _readAllowed_T_88 = io_readAddr == 12'h340;
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wire _readAllowed_T_90 = io_readAddr == 12'h341;
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wire _readAllowed_T_92 = io_readAddr == 12'h342;
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wire _readAllowed_T_94 = io_readAddr == 12'h343;
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wire _readAllowed_T_96 = io_readAddr == 12'h344;
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wire _readAllowed_T_98 = io_readAddr == 12'h3A0;
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wire _readAllowed_T_100 = io_readAddr == 12'h3B0;
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wire _readAllowed_T_102 = io_readAddr == 12'h7A0;
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wire _readAllowed_T_104 = io_readAddr == 12'h7A1;
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wire _readAllowed_T_106 = io_readAddr == 12'h7A2;
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wire _readAllowed_T_108 = io_readAddr == 12'h7A5;
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wire _readAllowed_T_110 = io_readAddr == 12'h744;
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wire _readAllowed_T_112 = io_readAddr == 12'h320;
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wire _readAllowed_T_114 = io_readAddr == 12'hB02;
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wire _readAllowed_T_116 = io_readAddr == 12'hF11;
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wire _readAllowed_T_118 = io_readAddr == 12'hF12;
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wire _readAllowed_T_120 = io_readAddr == 12'hF13;
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wire _readAllowed_T_122 = io_readAddr == 12'hF14;
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wire _readAllowed_T_125 = io_readAddr == 12'h100;
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wire _readAllowed_T_126 = io_readAddr == 12'h104;
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wire _readAllowed_T_128 = io_readAddr == 12'h105;
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wire _readAllowed_T_130 = io_readAddr == 12'h140;
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wire _readAllowed_T_132 = io_readAddr == 12'h106;
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wire _readAllowed_T_134 = io_readAddr == 12'h141;
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wire _readAllowed_T_136 = io_readAddr == 12'h142;
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wire _readAllowed_T_138 = io_readAddr == 12'h143;
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wire _readAllowed_T_140 = io_readAddr == 12'h144;
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wire _readAllowed_T_142 = io_readAddr == 12'h180;
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wire _readAllowed_T_69 = io_readAddr == 12'hC00;
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wire _readAllowed_T_70 = io_readAddr == 12'hC01;
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wire _readAllowed_T_72 = io_readAddr == 12'hC02;
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wire readAllowed =
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(_readAllowed_T_75 | _readAllowed_T_76 | _readAllowed_T_78 | _readAllowed_T_80
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| _readAllowed_T_82 | _readAllowed_T_84 | _readAllowed_T_86 | _readAllowed_T_88
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| _readAllowed_T_90 | _readAllowed_T_92 | _readAllowed_T_94 | _readAllowed_T_96
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| _readAllowed_T_98 | _readAllowed_T_100 | _readAllowed_T_102 | _readAllowed_T_104
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| _readAllowed_T_106 | _readAllowed_T_108 | _readAllowed_T_110 | _readAllowed_T_112
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| _readAllowed_T_114 | _readAllowed_T_116 | _readAllowed_T_118 | _readAllowed_T_120
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| _readAllowed_T_122 | _readAllowed_T_125 | _readAllowed_T_126 | _readAllowed_T_128
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| _readAllowed_T_130 | _readAllowed_T_132 | _readAllowed_T_134 | _readAllowed_T_136
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| _readAllowed_T_138 | _readAllowed_T_140 | _readAllowed_T_142 | _readAllowed_T_69
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| _readAllowed_T_70 | _readAllowed_T_72)
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& (_readAllowed_T_75 | _readAllowed_T_76 | _readAllowed_T_78 | _readAllowed_T_80
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| _readAllowed_T_82 | _readAllowed_T_84 | _readAllowed_T_86 | _readAllowed_T_88
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| _readAllowed_T_90 | _readAllowed_T_92 | _readAllowed_T_94 | _readAllowed_T_96
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| _readAllowed_T_98 | _readAllowed_T_100 | _readAllowed_T_102 | _readAllowed_T_104
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| _readAllowed_T_106 | _readAllowed_T_108 | _readAllowed_T_110 | _readAllowed_T_112
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| _readAllowed_T_114 | _readAllowed_T_116 | _readAllowed_T_118 | _readAllowed_T_120
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| _readAllowed_T_122
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? (&io_currentPriv)
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: ~(_readAllowed_T_125 | _readAllowed_T_126 | _readAllowed_T_128
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| _readAllowed_T_130 | _readAllowed_T_132 | _readAllowed_T_134
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| _readAllowed_T_136 | _readAllowed_T_138 | _readAllowed_T_140
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| _readAllowed_T_142) | (|io_currentPriv));
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wire _writeAllowed_T_75 = io_cmd_addr == 12'h300;
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wire _writeAllowed_T_76 = io_cmd_addr == 12'h301;
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wire _writeAllowed_T_78 = io_cmd_addr == 12'h302;
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wire _writeAllowed_T_80 = io_cmd_addr == 12'h303;
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wire _writeAllowed_T_82 = io_cmd_addr == 12'h304;
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wire _writeAllowed_T_84 = io_cmd_addr == 12'h305;
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wire _writeAllowed_T_86 = io_cmd_addr == 12'h306;
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wire _writeAllowed_T_88 = io_cmd_addr == 12'h340;
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wire _writeAllowed_T_90 = io_cmd_addr == 12'h341;
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wire _writeAllowed_T_92 = io_cmd_addr == 12'h342;
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wire _writeAllowed_T_94 = io_cmd_addr == 12'h343;
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wire _writeAllowed_T_96 = io_cmd_addr == 12'h344;
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wire _writeAllowed_T_98 = io_cmd_addr == 12'h3A0;
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wire _writeAllowed_T_100 = io_cmd_addr == 12'h3B0;
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wire _writeAllowed_T_102 = io_cmd_addr == 12'h7A0;
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wire _writeAllowed_T_104 = io_cmd_addr == 12'h7A1;
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wire _writeAllowed_T_106 = io_cmd_addr == 12'h7A2;
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wire _writeAllowed_T_108 = io_cmd_addr == 12'h7A5;
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wire _writeAllowed_T_110 = io_cmd_addr == 12'h744;
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wire _writeAllowed_T_112 = io_cmd_addr == 12'h320;
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wire _writeAllowed_T_114 = io_cmd_addr == 12'hB02;
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wire _writeAllowed_T_148 = io_cmd_addr == 12'hF11;
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wire _writeAllowed_T_149 = io_cmd_addr == 12'hF12;
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wire _writeAllowed_T_151 = io_cmd_addr == 12'hF13;
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wire _writeAllowed_T_153 = io_cmd_addr == 12'hF14;
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wire _writeAllowed_T_125 = io_cmd_addr == 12'h100;
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wire _writeAllowed_T_126 = io_cmd_addr == 12'h104;
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wire _writeAllowed_T_128 = io_cmd_addr == 12'h105;
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wire _writeAllowed_T_130 = io_cmd_addr == 12'h140;
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wire _writeAllowed_T_132 = io_cmd_addr == 12'h106;
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wire _writeAllowed_T_134 = io_cmd_addr == 12'h141;
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wire _writeAllowed_T_136 = io_cmd_addr == 12'h142;
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wire _writeAllowed_T_138 = io_cmd_addr == 12'h143;
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wire _writeAllowed_T_140 = io_cmd_addr == 12'h144;
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wire _writeAllowed_T_142 = io_cmd_addr == 12'h180;
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wire _writeAllowed_T_155 = io_cmd_addr == 12'hC00;
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wire _writeAllowed_T_156 = io_cmd_addr == 12'hC01;
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wire _writeAllowed_T_158 = io_cmd_addr == 12'hC02;
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wire [63:0] mstatusView = mstatus & 64'hFFFFFFF0FFFFFFFF | 64'hA00000000;
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wire [63:0] sstatusView = {30'h0, mstatusView[33:1] & 33'h10006F0B1, 1'h0};
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wire _GEN =
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io_cmd_valid & (|io_cmd_cmd)
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& (_writeAllowed_T_75 | _writeAllowed_T_76 | _writeAllowed_T_78 | _writeAllowed_T_80
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| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_88
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| _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
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| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_102
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| _writeAllowed_T_104 | _writeAllowed_T_106 | _writeAllowed_T_108
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| _writeAllowed_T_110 | _writeAllowed_T_112 | _writeAllowed_T_114
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| _writeAllowed_T_148 | _writeAllowed_T_149 | _writeAllowed_T_151
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| _writeAllowed_T_153 | _writeAllowed_T_125 | _writeAllowed_T_126
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| _writeAllowed_T_128 | _writeAllowed_T_130 | _writeAllowed_T_132
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| _writeAllowed_T_134 | _writeAllowed_T_136 | _writeAllowed_T_138
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| _writeAllowed_T_140 | _writeAllowed_T_142 | _writeAllowed_T_155
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| _writeAllowed_T_156 | _writeAllowed_T_158)
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& (_writeAllowed_T_75 | _writeAllowed_T_76 | _writeAllowed_T_78 | _writeAllowed_T_80
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| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_88
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| _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
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| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_102
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| _writeAllowed_T_104 | _writeAllowed_T_106 | _writeAllowed_T_108
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| _writeAllowed_T_110 | _writeAllowed_T_112 | _writeAllowed_T_114
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| _writeAllowed_T_148 | _writeAllowed_T_149 | _writeAllowed_T_151
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| _writeAllowed_T_153
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? (&io_currentPriv)
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: ~(_writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128
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| _writeAllowed_T_130 | _writeAllowed_T_132 | _writeAllowed_T_134
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| _writeAllowed_T_136 | _writeAllowed_T_138 | _writeAllowed_T_140
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| _writeAllowed_T_142) | (|io_currentPriv))
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& ~(_writeAllowed_T_148 | _writeAllowed_T_149 | _writeAllowed_T_151
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| _writeAllowed_T_153 | _writeAllowed_T_155 | _writeAllowed_T_156
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| _writeAllowed_T_158);
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wire _GEN_0 =
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_writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82
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| _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | _writeAllowed_T_88
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| _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
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| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104 | _writeAllowed_T_106
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| _writeAllowed_T_108 | _writeAllowed_T_110 | _writeAllowed_T_125
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| _writeAllowed_T_126 | _writeAllowed_T_128 | _writeAllowed_T_132
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| _writeAllowed_T_130 | _writeAllowed_T_134 | _writeAllowed_T_136
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| _writeAllowed_T_138 | _writeAllowed_T_140 | _writeAllowed_T_142;
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wire suppressInstretIncrement = _GEN & ~_GEN_0 & _writeAllowed_T_114;
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wire trapToS = io_trapTargetPriv == 2'h1;
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always @(posedge clock) begin
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if (reset) begin
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cycle <= 64'h0;
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instret <= 64'h0;
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mcountinhibit <= 64'h0;
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suppressInstretAfterWrite <= 1'h0;
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mstatus <= 64'h0;
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mtvecReg <= 64'h0;
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mscratch <= 64'h0;
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mepcReg <= 64'h0;
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mcause <= 64'h0;
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mtval <= 64'h0;
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@@ -46,7 +212,14 @@ module CSRFile(
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mideleg <= 64'h0;
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mie <= 64'h0;
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mip <= 64'h0;
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sstatus <= 64'h0;
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mcounteren <= 64'h0;
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pmpcfg0 <= 64'h0;
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pmpaddr0 <= 64'h0;
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tdata1 <= 64'h0;
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tdata2 <= 64'h0;
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tcontrol <= 64'h0;
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mnstatus <= 64'h0;
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scounteren <= 64'h0;
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stvec <= 64'h0;
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sepc <= 64'h0;
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scause <= 64'h0;
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@@ -55,206 +228,466 @@ module CSRFile(
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satpReg <= 64'h0;
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end
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else begin
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automatic logic _GEN;
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automatic logic _GEN_0;
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automatic logic _GEN_1;
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automatic logic _GEN_2;
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automatic logic _GEN_3;
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automatic logic _GEN_4;
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automatic logic _GEN_5;
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automatic logic _GEN_6 = io_cmd_addr == 12'h343;
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automatic logic _GEN_7 = io_cmd_addr == 12'h344;
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automatic logic _GEN_8 = io_cmd_addr == 12'h100;
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automatic logic _GEN_9 = io_cmd_addr == 12'h105;
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automatic logic _GEN_10 = io_cmd_addr == 12'h140;
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automatic logic _GEN_11 = io_cmd_addr == 12'h141;
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automatic logic _GEN_12 = io_cmd_addr == 12'h142;
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automatic logic _GEN_13 = io_cmd_addr == 12'h143;
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automatic logic _GEN_14 = io_cmd_addr == 12'h180;
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automatic logic [63:0] _GEN_15;
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automatic logic [63:0] writeOld;
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automatic logic [63:0] writeOld =
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_writeAllowed_T_75
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? mstatusView
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: _writeAllowed_T_76
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? 64'h8000000000141101
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: _writeAllowed_T_78
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? medeleg
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: _writeAllowed_T_80
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? mideleg
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: _writeAllowed_T_82
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? mie
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: _writeAllowed_T_84
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? mtvecReg
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: _writeAllowed_T_86
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? mcounteren
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: _writeAllowed_T_112
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? mcountinhibit
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: _writeAllowed_T_88
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? mscratch
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: _writeAllowed_T_90
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? mepcReg
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: _writeAllowed_T_92
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? mcause
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: _writeAllowed_T_94
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? mtval
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: _writeAllowed_T_96
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? mip
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: _writeAllowed_T_98
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? pmpcfg0
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: _writeAllowed_T_100
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? pmpaddr0
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: _writeAllowed_T_102
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? 64'h1
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: _writeAllowed_T_104
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? tdata1
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: _writeAllowed_T_106
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? tdata2
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: _writeAllowed_T_108
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? tcontrol
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: _writeAllowed_T_110
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? mnstatus
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: _writeAllowed_T_125
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? sstatusView
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: _writeAllowed_T_126
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? mie
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& mideleg
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: _writeAllowed_T_128
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? stvec
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: _writeAllowed_T_132
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? scounteren
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: _writeAllowed_T_130
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? sscratch
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: _writeAllowed_T_134
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? sepc
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: _writeAllowed_T_136
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? scause
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: _writeAllowed_T_138
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? stval
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: _writeAllowed_T_140
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? mip
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& mideleg
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: _writeAllowed_T_142
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? satpReg
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: _writeAllowed_T_148
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| _writeAllowed_T_149
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| _writeAllowed_T_151
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| _writeAllowed_T_153
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? 64'h0
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: _writeAllowed_T_114
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? instret
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: _writeAllowed_T_155
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| _writeAllowed_T_156
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? cycle
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: _writeAllowed_T_158
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? instret
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: 64'h0;
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automatic logic [63:0] operand;
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automatic logic [63:0] _next_T_1;
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automatic logic [63:0] _next_T_3;
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automatic logic [3:0][63:0] _GEN_16;
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automatic logic [3:0][63:0] _GEN_1;
|
||||
automatic logic [63:0] next;
|
||||
automatic logic _GEN_17;
|
||||
_GEN = io_cmd_addr == 12'h300;
|
||||
_GEN_0 = io_cmd_addr == 12'h302;
|
||||
_GEN_1 = io_cmd_addr == 12'h303;
|
||||
_GEN_2 = io_cmd_addr == 12'h304;
|
||||
_GEN_3 = io_cmd_addr == 12'h305;
|
||||
_GEN_4 = io_cmd_addr == 12'h341;
|
||||
_GEN_5 = io_cmd_addr == 12'h342;
|
||||
_GEN_15 =
|
||||
io_cmd_addr == 12'h301
|
||||
? 64'h800000000014112D
|
||||
: _GEN_0
|
||||
? medeleg
|
||||
: _GEN_1
|
||||
? mideleg
|
||||
: _GEN_2
|
||||
? mie
|
||||
: _GEN_3
|
||||
? mtvecReg
|
||||
: _GEN_4
|
||||
? mepcReg
|
||||
: _GEN_5
|
||||
? mcause
|
||||
: _GEN_6
|
||||
? mtval
|
||||
: _GEN_7
|
||||
? mip
|
||||
: _GEN_8
|
||||
? sstatus
|
||||
: _GEN_9
|
||||
? stvec
|
||||
: _GEN_10
|
||||
? sscratch
|
||||
: _GEN_11
|
||||
? sepc
|
||||
: _GEN_12
|
||||
? scause
|
||||
: _GEN_13
|
||||
? stval
|
||||
: _GEN_14
|
||||
? satpReg
|
||||
: io_cmd_addr == 12'hF14
|
||||
| io_cmd_addr != 12'hC00
|
||||
? 64'h0
|
||||
: cycle;
|
||||
writeOld = _GEN ? mstatus : _GEN_15;
|
||||
operand = io_cmd_cmd[2] ? {59'h0, io_cmd_zimm} : io_cmd_rs1;
|
||||
_next_T_1 = writeOld | operand;
|
||||
_next_T_3 = writeOld & ~operand;
|
||||
_GEN_16 = {{_next_T_3}, {_next_T_1}, {operand}, {writeOld}};
|
||||
next = _GEN_16[io_cmd_cmd[1:0]];
|
||||
_GEN_17 = io_cmd_valid & (|io_cmd_cmd);
|
||||
_GEN_1 = {{_next_T_3}, {_next_T_1}, {operand}, {writeOld}};
|
||||
next = _GEN_1[io_cmd_cmd[1:0]];
|
||||
cycle <= cycle + 64'h1;
|
||||
if (_GEN_17 & _GEN)
|
||||
mstatus <= next;
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | ~_GEN_3) begin
|
||||
if (~_GEN | _GEN_0 | ~_writeAllowed_T_114) begin
|
||||
if (mcountinhibit[2] | suppressInstretIncrement | suppressInstretAfterWrite) begin
|
||||
end
|
||||
else
|
||||
instret <= instret + 64'h1;
|
||||
end
|
||||
else
|
||||
instret <= next;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| ~_writeAllowed_T_112) begin
|
||||
end
|
||||
else
|
||||
mcountinhibit <= {61'h0, next[2], 2'h0};
|
||||
suppressInstretAfterWrite <=
|
||||
~suppressInstretAfterWrite
|
||||
& (suppressInstretIncrement | suppressInstretAfterWrite);
|
||||
if (io_trap) begin
|
||||
automatic logic [63:0] _GEN_2 =
|
||||
mstatus[1] ? mstatus | 64'h20 : mstatus & 64'hFFFFFFFFFFFFFFDF;
|
||||
mstatus <=
|
||||
trapToS
|
||||
? (io_currentPriv == 2'h1
|
||||
? _GEN_2 & 64'hFFFFFFFFFFFFFFFD | 64'h100
|
||||
: _GEN_2 & 64'hFFFFFFFFFFFFFEFD)
|
||||
: (mstatus[3] ? mstatus | 64'h80 : mstatus & 64'hFFFFFFFFFFFFFF7F)
|
||||
& 64'hFFFFFFFFFFFFE7F7 | {51'h0, io_currentPriv, 11'h0};
|
||||
end
|
||||
else if (io_xret)
|
||||
mstatus <=
|
||||
io_xretIsMret
|
||||
? ((mstatus[7] ? mstatus | 64'h8 : mstatus & 64'hFFFFFFFFFFFFFFF7) | 64'h80)
|
||||
& 64'hFFFFFFFFFFFFE7FF
|
||||
: ((mstatus[5] ? mstatus | 64'h2 : mstatus & 64'hFFFFFFFFFFFFFFFD) | 64'h20)
|
||||
& 64'hFFFFFFFFFFFFFEFF;
|
||||
else if (_GEN) begin
|
||||
if (_writeAllowed_T_75) begin
|
||||
automatic logic [3:0][63:0] _GEN_3;
|
||||
_GEN_3 = {{_next_T_3}, {_next_T_1}, {operand}, {mstatusView}};
|
||||
mstatus <= _GEN_3[io_cmd_cmd[1:0]];
|
||||
end
|
||||
else if (_writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82
|
||||
| _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112
|
||||
| _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92
|
||||
| _writeAllowed_T_94 | _writeAllowed_T_96 | _writeAllowed_T_98
|
||||
| _writeAllowed_T_100 | _writeAllowed_T_104 | _writeAllowed_T_106
|
||||
| _writeAllowed_T_108 | _writeAllowed_T_110 | ~_writeAllowed_T_125) begin
|
||||
end
|
||||
else
|
||||
mstatus <=
|
||||
mstatus & 64'hFFFFFFFDFFF21E9D | {30'h0, next[33:1] & 33'h10006F0B1, 1'h0};
|
||||
end
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | ~_writeAllowed_T_84) begin
|
||||
end
|
||||
else
|
||||
mtvecReg <= next;
|
||||
if (io_trap) begin
|
||||
mepcReg <= io_trapPc;
|
||||
mcause <= io_trapCause;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | ~_writeAllowed_T_88) begin
|
||||
end
|
||||
else begin
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | ~_GEN_4) begin
|
||||
else
|
||||
mscratch <= next;
|
||||
if (~io_trap | trapToS) begin
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | ~_writeAllowed_T_90) begin
|
||||
end
|
||||
else
|
||||
mepcReg <= next;
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | ~_GEN_5) begin
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| ~_writeAllowed_T_92) begin
|
||||
end
|
||||
else
|
||||
mcause <= next;
|
||||
end
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5
|
||||
| ~_GEN_6) begin
|
||||
end
|
||||
else
|
||||
mtval <= next;
|
||||
if (~_GEN_17 | _GEN | ~_GEN_0) begin
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | ~_writeAllowed_T_94) begin
|
||||
end
|
||||
else
|
||||
mtval <= next;
|
||||
end
|
||||
else begin
|
||||
automatic logic [3:0][63:0] _GEN_18;
|
||||
_GEN_18 = {{_next_T_3}, {_next_T_1}, {operand}, {_GEN_15}};
|
||||
medeleg <= _GEN_18[io_cmd_cmd[1:0]];
|
||||
mepcReg <= io_trapPc;
|
||||
mcause <= io_trapCause;
|
||||
mtval <= io_trapTval;
|
||||
end
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | ~_GEN_1) begin
|
||||
if (~_GEN | _writeAllowed_T_75 | ~_writeAllowed_T_78) begin
|
||||
end
|
||||
else
|
||||
mideleg <= next;
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | ~_GEN_2) begin
|
||||
else begin
|
||||
automatic logic [3:0][63:0] _GEN_4;
|
||||
_GEN_4 =
|
||||
{{_next_T_3},
|
||||
{_next_T_1},
|
||||
{operand},
|
||||
{_writeAllowed_T_76 ? 64'h8000000000141101 : medeleg}};
|
||||
medeleg <= _GEN_4[io_cmd_cmd[1:0]];
|
||||
end
|
||||
else
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | ~_writeAllowed_T_80) begin
|
||||
end
|
||||
else begin
|
||||
automatic logic [3:0][63:0] _GEN_5;
|
||||
_GEN_5 =
|
||||
{{_next_T_3},
|
||||
{_next_T_1},
|
||||
{operand},
|
||||
{_writeAllowed_T_75
|
||||
? mstatusView
|
||||
: _writeAllowed_T_76
|
||||
? 64'h8000000000141101
|
||||
: _writeAllowed_T_78 ? medeleg : mideleg}};
|
||||
mideleg <= _GEN_5[io_cmd_cmd[1:0]];
|
||||
end
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80) begin
|
||||
end
|
||||
else if (_writeAllowed_T_82)
|
||||
mie <= next;
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
|
||||
| ~_GEN_7) begin
|
||||
else if (_writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112
|
||||
| _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92
|
||||
| _writeAllowed_T_94 | _writeAllowed_T_96 | _writeAllowed_T_98
|
||||
| _writeAllowed_T_100 | _writeAllowed_T_104 | _writeAllowed_T_106
|
||||
| _writeAllowed_T_108 | _writeAllowed_T_110 | _writeAllowed_T_125
|
||||
| ~_writeAllowed_T_126) begin
|
||||
end
|
||||
else
|
||||
mie <= mie & ~mideleg | next & mideleg;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94) begin
|
||||
end
|
||||
else if (_writeAllowed_T_96)
|
||||
mip <= next;
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
|
||||
| _GEN_7 | ~_GEN_8) begin
|
||||
else if (_writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104
|
||||
| _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110
|
||||
| _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128
|
||||
| _writeAllowed_T_132 | _writeAllowed_T_130 | _writeAllowed_T_134
|
||||
| _writeAllowed_T_136 | _writeAllowed_T_138 | ~_writeAllowed_T_140) begin
|
||||
end
|
||||
else
|
||||
sstatus <= next;
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
|
||||
| _GEN_7 | _GEN_8 | ~_GEN_9) begin
|
||||
mip <= mip & ~mideleg | next & mideleg;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | ~_writeAllowed_T_86) begin
|
||||
end
|
||||
else
|
||||
mcounteren <= next;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| ~_writeAllowed_T_98) begin
|
||||
end
|
||||
else
|
||||
pmpcfg0 <= next;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | ~_writeAllowed_T_100) begin
|
||||
end
|
||||
else
|
||||
pmpaddr0 <= next;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | _writeAllowed_T_100 | ~_writeAllowed_T_104) begin
|
||||
end
|
||||
else
|
||||
tdata1 <= next;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104
|
||||
| ~_writeAllowed_T_106) begin
|
||||
end
|
||||
else
|
||||
tdata2 <= next;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104
|
||||
| _writeAllowed_T_106 | ~_writeAllowed_T_108) begin
|
||||
end
|
||||
else
|
||||
tcontrol <= next;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104
|
||||
| _writeAllowed_T_106 | _writeAllowed_T_108 | ~_writeAllowed_T_110) begin
|
||||
end
|
||||
else
|
||||
mnstatus <= next;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104
|
||||
| _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110
|
||||
| _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128
|
||||
| ~_writeAllowed_T_132) begin
|
||||
end
|
||||
else
|
||||
scounteren <= next;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104
|
||||
| _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110
|
||||
| _writeAllowed_T_125 | _writeAllowed_T_126 | ~_writeAllowed_T_128) begin
|
||||
end
|
||||
else
|
||||
stvec <= next;
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
|
||||
| _GEN_7 | _GEN_8 | _GEN_9 | _GEN_10 | ~_GEN_11) begin
|
||||
if (io_trap & trapToS) begin
|
||||
sepc <= io_trapPc;
|
||||
scause <= io_trapCause;
|
||||
stval <= io_trapTval;
|
||||
end
|
||||
else
|
||||
sepc <= next;
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
|
||||
| _GEN_7 | _GEN_8 | _GEN_9 | _GEN_10 | _GEN_11 | ~_GEN_12) begin
|
||||
else begin
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104
|
||||
| _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110
|
||||
| _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128
|
||||
| _writeAllowed_T_132 | _writeAllowed_T_130 | ~_writeAllowed_T_134) begin
|
||||
end
|
||||
else
|
||||
sepc <= next;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104
|
||||
| _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110
|
||||
| _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128
|
||||
| _writeAllowed_T_132 | _writeAllowed_T_130 | _writeAllowed_T_134
|
||||
| ~_writeAllowed_T_136) begin
|
||||
end
|
||||
else
|
||||
scause <= next;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104
|
||||
| _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110
|
||||
| _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128
|
||||
| _writeAllowed_T_132 | _writeAllowed_T_130 | _writeAllowed_T_134
|
||||
| _writeAllowed_T_136 | ~_writeAllowed_T_138) begin
|
||||
end
|
||||
else
|
||||
stval <= next;
|
||||
end
|
||||
else
|
||||
scause <= next;
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
|
||||
| _GEN_7 | _GEN_8 | _GEN_9 | _GEN_10 | _GEN_11 | _GEN_12 | ~_GEN_13) begin
|
||||
end
|
||||
else
|
||||
stval <= next;
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
|
||||
| _GEN_7 | _GEN_8 | _GEN_9 | ~_GEN_10) begin
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104
|
||||
| _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110
|
||||
| _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128
|
||||
| _writeAllowed_T_132 | ~_writeAllowed_T_130) begin
|
||||
end
|
||||
else
|
||||
sscratch <= next;
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
|
||||
| _GEN_7 | _GEN_8 | _GEN_9 | _GEN_10 | _GEN_11 | _GEN_12 | _GEN_13
|
||||
| ~_GEN_14) begin
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104
|
||||
| _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110
|
||||
| _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128
|
||||
| _writeAllowed_T_132 | _writeAllowed_T_130 | _writeAllowed_T_134
|
||||
| _writeAllowed_T_136 | _writeAllowed_T_138 | _writeAllowed_T_140
|
||||
| ~_writeAllowed_T_142) begin
|
||||
end
|
||||
else
|
||||
satpReg <= next;
|
||||
end
|
||||
end // always @(posedge)
|
||||
assign io_rdata =
|
||||
io_readAddr == 12'h300
|
||||
? mstatus
|
||||
: io_readAddr == 12'h301
|
||||
? 64'h800000000014112D
|
||||
: io_readAddr == 12'h302
|
||||
? medeleg
|
||||
: io_readAddr == 12'h303
|
||||
? mideleg
|
||||
: io_readAddr == 12'h304
|
||||
? mie
|
||||
: io_readAddr == 12'h305
|
||||
? mtvecReg
|
||||
: io_readAddr == 12'h341
|
||||
? mepcReg
|
||||
: io_readAddr == 12'h342
|
||||
? mcause
|
||||
: io_readAddr == 12'h343
|
||||
? mtval
|
||||
: io_readAddr == 12'h344
|
||||
? mip
|
||||
: io_readAddr == 12'h100
|
||||
? sstatus
|
||||
: io_readAddr == 12'h105
|
||||
? stvec
|
||||
: io_readAddr == 12'h140
|
||||
? sscratch
|
||||
: io_readAddr == 12'h141
|
||||
? sepc
|
||||
: io_readAddr == 12'h142
|
||||
? scause
|
||||
: io_readAddr == 12'h143
|
||||
? stval
|
||||
: io_readAddr == 12'h180
|
||||
? satpReg
|
||||
: io_readAddr == 12'hF14
|
||||
| io_readAddr != 12'hC00
|
||||
? 64'h0
|
||||
: cycle;
|
||||
readAllowed
|
||||
? (_readAllowed_T_75
|
||||
? mstatusView
|
||||
: _readAllowed_T_76
|
||||
? 64'h8000000000141101
|
||||
: _readAllowed_T_78
|
||||
? medeleg
|
||||
: _readAllowed_T_80
|
||||
? mideleg
|
||||
: _readAllowed_T_82
|
||||
? mie
|
||||
: _readAllowed_T_84
|
||||
? mtvecReg
|
||||
: _readAllowed_T_86
|
||||
? mcounteren
|
||||
: _readAllowed_T_112
|
||||
? mcountinhibit
|
||||
: _readAllowed_T_88
|
||||
? mscratch
|
||||
: _readAllowed_T_90
|
||||
? mepcReg
|
||||
: _readAllowed_T_92
|
||||
? mcause
|
||||
: _readAllowed_T_94
|
||||
? mtval
|
||||
: _readAllowed_T_96
|
||||
? mip
|
||||
: _readAllowed_T_98
|
||||
? pmpcfg0
|
||||
: _readAllowed_T_100
|
||||
? pmpaddr0
|
||||
: _readAllowed_T_102
|
||||
? 64'h1
|
||||
: _readAllowed_T_104
|
||||
? tdata1
|
||||
: _readAllowed_T_106
|
||||
? tdata2
|
||||
: _readAllowed_T_108
|
||||
? tcontrol
|
||||
: _readAllowed_T_110
|
||||
? mnstatus
|
||||
: _readAllowed_T_125
|
||||
? sstatusView
|
||||
: _readAllowed_T_126
|
||||
? mie
|
||||
& mideleg
|
||||
: _readAllowed_T_128
|
||||
? stvec
|
||||
: _readAllowed_T_132
|
||||
? scounteren
|
||||
: _readAllowed_T_130
|
||||
? sscratch
|
||||
: _readAllowed_T_134
|
||||
? sepc
|
||||
: _readAllowed_T_136
|
||||
? scause
|
||||
: _readAllowed_T_138
|
||||
? stval
|
||||
: _readAllowed_T_140
|
||||
? mip
|
||||
& mideleg
|
||||
: _readAllowed_T_142
|
||||
? satpReg
|
||||
: _readAllowed_T_116
|
||||
| _readAllowed_T_118
|
||||
| _readAllowed_T_120
|
||||
| _readAllowed_T_122
|
||||
? 64'h0
|
||||
: _readAllowed_T_114
|
||||
? instret
|
||||
: _readAllowed_T_69
|
||||
| _readAllowed_T_70
|
||||
? cycle
|
||||
: _readAllowed_T_72
|
||||
? instret
|
||||
: 64'h0)
|
||||
: 64'h0;
|
||||
assign io_readIllegal = ~readAllowed;
|
||||
assign io_trapVector = trapToS ? stvec : mtvecReg;
|
||||
assign io_satp = satpReg;
|
||||
assign io_mtvec = mtvecReg;
|
||||
assign io_mepc = mepcReg;
|
||||
assign io_sepc = sepc;
|
||||
assign io_medeleg = medeleg;
|
||||
assign io_mstatus = mstatus;
|
||||
endmodule
|
||||
|
||||
|
||||
Reference in New Issue
Block a user