feat: implement privileged mode support
This commit is contained in:
abnerhexu
@@ -8,37 +8,203 @@ module CSRFile(
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input [63:0] io_cmd_rs1,
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input [4:0] io_cmd_zimm,
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input [11:0] io_readAddr,
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input [1:0] io_currentPriv,
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output [63:0] io_rdata,
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output io_readIllegal,
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input io_trap,
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input [63:0] io_trapPc,
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io_trapCause,
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io_trapTval,
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input [1:0] io_trapTargetPriv,
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output [63:0] io_trapVector,
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input io_xret,
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io_xretIsMret,
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output [63:0] io_satp,
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io_mtvec,
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io_mepc
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io_mepc,
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io_sepc,
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io_medeleg,
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io_mstatus
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);
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reg [63:0] cycle;
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reg [63:0] mstatus;
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reg [63:0] mtvecReg;
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reg [63:0] mepcReg;
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reg [63:0] mcause;
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reg [63:0] mtval;
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reg [63:0] medeleg;
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reg [63:0] mideleg;
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reg [63:0] mie;
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reg [63:0] mip;
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reg [63:0] sstatus;
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reg [63:0] stvec;
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reg [63:0] sepc;
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reg [63:0] scause;
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reg [63:0] stval;
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reg [63:0] sscratch;
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reg [63:0] satpReg;
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reg [63:0] cycle;
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reg [63:0] instret;
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reg [63:0] mcountinhibit;
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reg suppressInstretAfterWrite;
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reg [63:0] mstatus;
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reg [63:0] mtvecReg;
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reg [63:0] mscratch;
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reg [63:0] mepcReg;
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reg [63:0] mcause;
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reg [63:0] mtval;
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reg [63:0] medeleg;
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reg [63:0] mideleg;
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reg [63:0] mie;
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reg [63:0] mip;
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reg [63:0] mcounteren;
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reg [63:0] pmpcfg0;
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reg [63:0] pmpaddr0;
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reg [63:0] tdata1;
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reg [63:0] tdata2;
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reg [63:0] tcontrol;
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reg [63:0] mnstatus;
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reg [63:0] scounteren;
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reg [63:0] stvec;
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reg [63:0] sepc;
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reg [63:0] scause;
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reg [63:0] stval;
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reg [63:0] sscratch;
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reg [63:0] satpReg;
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wire _readAllowed_T_75 = io_readAddr == 12'h300;
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wire _readAllowed_T_76 = io_readAddr == 12'h301;
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wire _readAllowed_T_78 = io_readAddr == 12'h302;
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wire _readAllowed_T_80 = io_readAddr == 12'h303;
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wire _readAllowed_T_82 = io_readAddr == 12'h304;
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wire _readAllowed_T_84 = io_readAddr == 12'h305;
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wire _readAllowed_T_86 = io_readAddr == 12'h306;
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wire _readAllowed_T_88 = io_readAddr == 12'h340;
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wire _readAllowed_T_90 = io_readAddr == 12'h341;
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wire _readAllowed_T_92 = io_readAddr == 12'h342;
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wire _readAllowed_T_94 = io_readAddr == 12'h343;
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wire _readAllowed_T_96 = io_readAddr == 12'h344;
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wire _readAllowed_T_98 = io_readAddr == 12'h3A0;
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wire _readAllowed_T_100 = io_readAddr == 12'h3B0;
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wire _readAllowed_T_102 = io_readAddr == 12'h7A0;
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wire _readAllowed_T_104 = io_readAddr == 12'h7A1;
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wire _readAllowed_T_106 = io_readAddr == 12'h7A2;
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wire _readAllowed_T_108 = io_readAddr == 12'h7A5;
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wire _readAllowed_T_110 = io_readAddr == 12'h744;
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wire _readAllowed_T_112 = io_readAddr == 12'h320;
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wire _readAllowed_T_114 = io_readAddr == 12'hB02;
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wire _readAllowed_T_116 = io_readAddr == 12'hF11;
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wire _readAllowed_T_118 = io_readAddr == 12'hF12;
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wire _readAllowed_T_120 = io_readAddr == 12'hF13;
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wire _readAllowed_T_122 = io_readAddr == 12'hF14;
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wire _readAllowed_T_125 = io_readAddr == 12'h100;
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wire _readAllowed_T_126 = io_readAddr == 12'h104;
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wire _readAllowed_T_128 = io_readAddr == 12'h105;
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wire _readAllowed_T_130 = io_readAddr == 12'h140;
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wire _readAllowed_T_132 = io_readAddr == 12'h106;
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wire _readAllowed_T_134 = io_readAddr == 12'h141;
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wire _readAllowed_T_136 = io_readAddr == 12'h142;
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wire _readAllowed_T_138 = io_readAddr == 12'h143;
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wire _readAllowed_T_140 = io_readAddr == 12'h144;
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wire _readAllowed_T_142 = io_readAddr == 12'h180;
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wire _readAllowed_T_69 = io_readAddr == 12'hC00;
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wire _readAllowed_T_70 = io_readAddr == 12'hC01;
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wire _readAllowed_T_72 = io_readAddr == 12'hC02;
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wire readAllowed =
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(_readAllowed_T_75 | _readAllowed_T_76 | _readAllowed_T_78 | _readAllowed_T_80
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| _readAllowed_T_82 | _readAllowed_T_84 | _readAllowed_T_86 | _readAllowed_T_88
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| _readAllowed_T_90 | _readAllowed_T_92 | _readAllowed_T_94 | _readAllowed_T_96
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| _readAllowed_T_98 | _readAllowed_T_100 | _readAllowed_T_102 | _readAllowed_T_104
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| _readAllowed_T_106 | _readAllowed_T_108 | _readAllowed_T_110 | _readAllowed_T_112
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| _readAllowed_T_114 | _readAllowed_T_116 | _readAllowed_T_118 | _readAllowed_T_120
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| _readAllowed_T_122 | _readAllowed_T_125 | _readAllowed_T_126 | _readAllowed_T_128
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| _readAllowed_T_130 | _readAllowed_T_132 | _readAllowed_T_134 | _readAllowed_T_136
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| _readAllowed_T_138 | _readAllowed_T_140 | _readAllowed_T_142 | _readAllowed_T_69
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| _readAllowed_T_70 | _readAllowed_T_72)
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& (_readAllowed_T_75 | _readAllowed_T_76 | _readAllowed_T_78 | _readAllowed_T_80
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| _readAllowed_T_82 | _readAllowed_T_84 | _readAllowed_T_86 | _readAllowed_T_88
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| _readAllowed_T_90 | _readAllowed_T_92 | _readAllowed_T_94 | _readAllowed_T_96
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| _readAllowed_T_98 | _readAllowed_T_100 | _readAllowed_T_102 | _readAllowed_T_104
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| _readAllowed_T_106 | _readAllowed_T_108 | _readAllowed_T_110 | _readAllowed_T_112
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| _readAllowed_T_114 | _readAllowed_T_116 | _readAllowed_T_118 | _readAllowed_T_120
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| _readAllowed_T_122
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? (&io_currentPriv)
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: ~(_readAllowed_T_125 | _readAllowed_T_126 | _readAllowed_T_128
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| _readAllowed_T_130 | _readAllowed_T_132 | _readAllowed_T_134
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| _readAllowed_T_136 | _readAllowed_T_138 | _readAllowed_T_140
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| _readAllowed_T_142) | (|io_currentPriv));
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wire _writeAllowed_T_75 = io_cmd_addr == 12'h300;
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wire _writeAllowed_T_76 = io_cmd_addr == 12'h301;
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wire _writeAllowed_T_78 = io_cmd_addr == 12'h302;
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wire _writeAllowed_T_80 = io_cmd_addr == 12'h303;
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wire _writeAllowed_T_82 = io_cmd_addr == 12'h304;
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wire _writeAllowed_T_84 = io_cmd_addr == 12'h305;
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wire _writeAllowed_T_86 = io_cmd_addr == 12'h306;
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wire _writeAllowed_T_88 = io_cmd_addr == 12'h340;
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wire _writeAllowed_T_90 = io_cmd_addr == 12'h341;
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wire _writeAllowed_T_92 = io_cmd_addr == 12'h342;
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wire _writeAllowed_T_94 = io_cmd_addr == 12'h343;
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wire _writeAllowed_T_96 = io_cmd_addr == 12'h344;
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wire _writeAllowed_T_98 = io_cmd_addr == 12'h3A0;
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wire _writeAllowed_T_100 = io_cmd_addr == 12'h3B0;
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wire _writeAllowed_T_102 = io_cmd_addr == 12'h7A0;
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wire _writeAllowed_T_104 = io_cmd_addr == 12'h7A1;
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wire _writeAllowed_T_106 = io_cmd_addr == 12'h7A2;
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wire _writeAllowed_T_108 = io_cmd_addr == 12'h7A5;
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wire _writeAllowed_T_110 = io_cmd_addr == 12'h744;
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wire _writeAllowed_T_112 = io_cmd_addr == 12'h320;
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wire _writeAllowed_T_114 = io_cmd_addr == 12'hB02;
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wire _writeAllowed_T_148 = io_cmd_addr == 12'hF11;
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wire _writeAllowed_T_149 = io_cmd_addr == 12'hF12;
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wire _writeAllowed_T_151 = io_cmd_addr == 12'hF13;
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wire _writeAllowed_T_153 = io_cmd_addr == 12'hF14;
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wire _writeAllowed_T_125 = io_cmd_addr == 12'h100;
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wire _writeAllowed_T_126 = io_cmd_addr == 12'h104;
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wire _writeAllowed_T_128 = io_cmd_addr == 12'h105;
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wire _writeAllowed_T_130 = io_cmd_addr == 12'h140;
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wire _writeAllowed_T_132 = io_cmd_addr == 12'h106;
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wire _writeAllowed_T_134 = io_cmd_addr == 12'h141;
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wire _writeAllowed_T_136 = io_cmd_addr == 12'h142;
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wire _writeAllowed_T_138 = io_cmd_addr == 12'h143;
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wire _writeAllowed_T_140 = io_cmd_addr == 12'h144;
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wire _writeAllowed_T_142 = io_cmd_addr == 12'h180;
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wire _writeAllowed_T_155 = io_cmd_addr == 12'hC00;
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wire _writeAllowed_T_156 = io_cmd_addr == 12'hC01;
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wire _writeAllowed_T_158 = io_cmd_addr == 12'hC02;
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wire [63:0] mstatusView = mstatus & 64'hFFFFFFF0FFFFFFFF | 64'hA00000000;
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wire [63:0] sstatusView = {30'h0, mstatusView[33:1] & 33'h10006F0B1, 1'h0};
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wire _GEN =
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io_cmd_valid & (|io_cmd_cmd)
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& (_writeAllowed_T_75 | _writeAllowed_T_76 | _writeAllowed_T_78 | _writeAllowed_T_80
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| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_88
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| _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
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| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_102
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| _writeAllowed_T_104 | _writeAllowed_T_106 | _writeAllowed_T_108
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| _writeAllowed_T_110 | _writeAllowed_T_112 | _writeAllowed_T_114
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| _writeAllowed_T_148 | _writeAllowed_T_149 | _writeAllowed_T_151
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| _writeAllowed_T_153 | _writeAllowed_T_125 | _writeAllowed_T_126
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| _writeAllowed_T_128 | _writeAllowed_T_130 | _writeAllowed_T_132
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| _writeAllowed_T_134 | _writeAllowed_T_136 | _writeAllowed_T_138
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| _writeAllowed_T_140 | _writeAllowed_T_142 | _writeAllowed_T_155
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| _writeAllowed_T_156 | _writeAllowed_T_158)
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& (_writeAllowed_T_75 | _writeAllowed_T_76 | _writeAllowed_T_78 | _writeAllowed_T_80
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| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_88
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| _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
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| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_102
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| _writeAllowed_T_104 | _writeAllowed_T_106 | _writeAllowed_T_108
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| _writeAllowed_T_110 | _writeAllowed_T_112 | _writeAllowed_T_114
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| _writeAllowed_T_148 | _writeAllowed_T_149 | _writeAllowed_T_151
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| _writeAllowed_T_153
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? (&io_currentPriv)
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: ~(_writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128
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| _writeAllowed_T_130 | _writeAllowed_T_132 | _writeAllowed_T_134
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| _writeAllowed_T_136 | _writeAllowed_T_138 | _writeAllowed_T_140
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| _writeAllowed_T_142) | (|io_currentPriv))
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& ~(_writeAllowed_T_148 | _writeAllowed_T_149 | _writeAllowed_T_151
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| _writeAllowed_T_153 | _writeAllowed_T_155 | _writeAllowed_T_156
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| _writeAllowed_T_158);
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wire _GEN_0 =
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_writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82
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| _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112 | _writeAllowed_T_88
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| _writeAllowed_T_90 | _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
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| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104 | _writeAllowed_T_106
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| _writeAllowed_T_108 | _writeAllowed_T_110 | _writeAllowed_T_125
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| _writeAllowed_T_126 | _writeAllowed_T_128 | _writeAllowed_T_132
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| _writeAllowed_T_130 | _writeAllowed_T_134 | _writeAllowed_T_136
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| _writeAllowed_T_138 | _writeAllowed_T_140 | _writeAllowed_T_142;
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wire suppressInstretIncrement = _GEN & ~_GEN_0 & _writeAllowed_T_114;
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wire trapToS = io_trapTargetPriv == 2'h1;
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always @(posedge clock) begin
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if (reset) begin
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cycle <= 64'h0;
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instret <= 64'h0;
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mcountinhibit <= 64'h0;
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suppressInstretAfterWrite <= 1'h0;
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mstatus <= 64'h0;
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mtvecReg <= 64'h0;
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mscratch <= 64'h0;
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mepcReg <= 64'h0;
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mcause <= 64'h0;
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mtval <= 64'h0;
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@@ -46,7 +212,14 @@ module CSRFile(
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mideleg <= 64'h0;
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mie <= 64'h0;
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mip <= 64'h0;
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sstatus <= 64'h0;
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mcounteren <= 64'h0;
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pmpcfg0 <= 64'h0;
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pmpaddr0 <= 64'h0;
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tdata1 <= 64'h0;
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tdata2 <= 64'h0;
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tcontrol <= 64'h0;
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mnstatus <= 64'h0;
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scounteren <= 64'h0;
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stvec <= 64'h0;
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sepc <= 64'h0;
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scause <= 64'h0;
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@@ -55,206 +228,466 @@ module CSRFile(
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satpReg <= 64'h0;
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end
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else begin
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automatic logic _GEN;
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automatic logic _GEN_0;
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automatic logic _GEN_1;
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automatic logic _GEN_2;
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automatic logic _GEN_3;
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automatic logic _GEN_4;
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automatic logic _GEN_5;
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automatic logic _GEN_6 = io_cmd_addr == 12'h343;
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automatic logic _GEN_7 = io_cmd_addr == 12'h344;
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automatic logic _GEN_8 = io_cmd_addr == 12'h100;
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automatic logic _GEN_9 = io_cmd_addr == 12'h105;
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automatic logic _GEN_10 = io_cmd_addr == 12'h140;
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automatic logic _GEN_11 = io_cmd_addr == 12'h141;
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automatic logic _GEN_12 = io_cmd_addr == 12'h142;
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automatic logic _GEN_13 = io_cmd_addr == 12'h143;
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automatic logic _GEN_14 = io_cmd_addr == 12'h180;
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automatic logic [63:0] _GEN_15;
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automatic logic [63:0] writeOld;
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automatic logic [63:0] writeOld =
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_writeAllowed_T_75
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? mstatusView
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: _writeAllowed_T_76
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? 64'h8000000000141101
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: _writeAllowed_T_78
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? medeleg
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: _writeAllowed_T_80
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? mideleg
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: _writeAllowed_T_82
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? mie
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: _writeAllowed_T_84
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? mtvecReg
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: _writeAllowed_T_86
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? mcounteren
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: _writeAllowed_T_112
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? mcountinhibit
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: _writeAllowed_T_88
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? mscratch
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: _writeAllowed_T_90
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? mepcReg
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: _writeAllowed_T_92
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? mcause
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: _writeAllowed_T_94
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? mtval
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: _writeAllowed_T_96
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? mip
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: _writeAllowed_T_98
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? pmpcfg0
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: _writeAllowed_T_100
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? pmpaddr0
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: _writeAllowed_T_102
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? 64'h1
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: _writeAllowed_T_104
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? tdata1
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: _writeAllowed_T_106
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? tdata2
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: _writeAllowed_T_108
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? tcontrol
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: _writeAllowed_T_110
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? mnstatus
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: _writeAllowed_T_125
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? sstatusView
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: _writeAllowed_T_126
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? mie
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& mideleg
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: _writeAllowed_T_128
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? stvec
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: _writeAllowed_T_132
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? scounteren
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: _writeAllowed_T_130
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? sscratch
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: _writeAllowed_T_134
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? sepc
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: _writeAllowed_T_136
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? scause
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: _writeAllowed_T_138
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? stval
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: _writeAllowed_T_140
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? mip
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& mideleg
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: _writeAllowed_T_142
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? satpReg
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: _writeAllowed_T_148
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| _writeAllowed_T_149
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| _writeAllowed_T_151
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| _writeAllowed_T_153
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? 64'h0
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: _writeAllowed_T_114
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? instret
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: _writeAllowed_T_155
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| _writeAllowed_T_156
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? cycle
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: _writeAllowed_T_158
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? instret
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: 64'h0;
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automatic logic [63:0] operand;
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automatic logic [63:0] _next_T_1;
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automatic logic [63:0] _next_T_3;
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automatic logic [3:0][63:0] _GEN_16;
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automatic logic [3:0][63:0] _GEN_1;
|
||||
automatic logic [63:0] next;
|
||||
automatic logic _GEN_17;
|
||||
_GEN = io_cmd_addr == 12'h300;
|
||||
_GEN_0 = io_cmd_addr == 12'h302;
|
||||
_GEN_1 = io_cmd_addr == 12'h303;
|
||||
_GEN_2 = io_cmd_addr == 12'h304;
|
||||
_GEN_3 = io_cmd_addr == 12'h305;
|
||||
_GEN_4 = io_cmd_addr == 12'h341;
|
||||
_GEN_5 = io_cmd_addr == 12'h342;
|
||||
_GEN_15 =
|
||||
io_cmd_addr == 12'h301
|
||||
? 64'h800000000014112D
|
||||
: _GEN_0
|
||||
? medeleg
|
||||
: _GEN_1
|
||||
? mideleg
|
||||
: _GEN_2
|
||||
? mie
|
||||
: _GEN_3
|
||||
? mtvecReg
|
||||
: _GEN_4
|
||||
? mepcReg
|
||||
: _GEN_5
|
||||
? mcause
|
||||
: _GEN_6
|
||||
? mtval
|
||||
: _GEN_7
|
||||
? mip
|
||||
: _GEN_8
|
||||
? sstatus
|
||||
: _GEN_9
|
||||
? stvec
|
||||
: _GEN_10
|
||||
? sscratch
|
||||
: _GEN_11
|
||||
? sepc
|
||||
: _GEN_12
|
||||
? scause
|
||||
: _GEN_13
|
||||
? stval
|
||||
: _GEN_14
|
||||
? satpReg
|
||||
: io_cmd_addr == 12'hF14
|
||||
| io_cmd_addr != 12'hC00
|
||||
? 64'h0
|
||||
: cycle;
|
||||
writeOld = _GEN ? mstatus : _GEN_15;
|
||||
operand = io_cmd_cmd[2] ? {59'h0, io_cmd_zimm} : io_cmd_rs1;
|
||||
_next_T_1 = writeOld | operand;
|
||||
_next_T_3 = writeOld & ~operand;
|
||||
_GEN_16 = {{_next_T_3}, {_next_T_1}, {operand}, {writeOld}};
|
||||
next = _GEN_16[io_cmd_cmd[1:0]];
|
||||
_GEN_17 = io_cmd_valid & (|io_cmd_cmd);
|
||||
_GEN_1 = {{_next_T_3}, {_next_T_1}, {operand}, {writeOld}};
|
||||
next = _GEN_1[io_cmd_cmd[1:0]];
|
||||
cycle <= cycle + 64'h1;
|
||||
if (_GEN_17 & _GEN)
|
||||
mstatus <= next;
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | ~_GEN_3) begin
|
||||
if (~_GEN | _GEN_0 | ~_writeAllowed_T_114) begin
|
||||
if (mcountinhibit[2] | suppressInstretIncrement | suppressInstretAfterWrite) begin
|
||||
end
|
||||
else
|
||||
instret <= instret + 64'h1;
|
||||
end
|
||||
else
|
||||
instret <= next;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| ~_writeAllowed_T_112) begin
|
||||
end
|
||||
else
|
||||
mcountinhibit <= {61'h0, next[2], 2'h0};
|
||||
suppressInstretAfterWrite <=
|
||||
~suppressInstretAfterWrite
|
||||
& (suppressInstretIncrement | suppressInstretAfterWrite);
|
||||
if (io_trap) begin
|
||||
automatic logic [63:0] _GEN_2 =
|
||||
mstatus[1] ? mstatus | 64'h20 : mstatus & 64'hFFFFFFFFFFFFFFDF;
|
||||
mstatus <=
|
||||
trapToS
|
||||
? (io_currentPriv == 2'h1
|
||||
? _GEN_2 & 64'hFFFFFFFFFFFFFFFD | 64'h100
|
||||
: _GEN_2 & 64'hFFFFFFFFFFFFFEFD)
|
||||
: (mstatus[3] ? mstatus | 64'h80 : mstatus & 64'hFFFFFFFFFFFFFF7F)
|
||||
& 64'hFFFFFFFFFFFFE7F7 | {51'h0, io_currentPriv, 11'h0};
|
||||
end
|
||||
else if (io_xret)
|
||||
mstatus <=
|
||||
io_xretIsMret
|
||||
? ((mstatus[7] ? mstatus | 64'h8 : mstatus & 64'hFFFFFFFFFFFFFFF7) | 64'h80)
|
||||
& 64'hFFFFFFFFFFFFE7FF
|
||||
: ((mstatus[5] ? mstatus | 64'h2 : mstatus & 64'hFFFFFFFFFFFFFFFD) | 64'h20)
|
||||
& 64'hFFFFFFFFFFFFFEFF;
|
||||
else if (_GEN) begin
|
||||
if (_writeAllowed_T_75) begin
|
||||
automatic logic [3:0][63:0] _GEN_3;
|
||||
_GEN_3 = {{_next_T_3}, {_next_T_1}, {operand}, {mstatusView}};
|
||||
mstatus <= _GEN_3[io_cmd_cmd[1:0]];
|
||||
end
|
||||
else if (_writeAllowed_T_78 | _writeAllowed_T_80 | _writeAllowed_T_82
|
||||
| _writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112
|
||||
| _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92
|
||||
| _writeAllowed_T_94 | _writeAllowed_T_96 | _writeAllowed_T_98
|
||||
| _writeAllowed_T_100 | _writeAllowed_T_104 | _writeAllowed_T_106
|
||||
| _writeAllowed_T_108 | _writeAllowed_T_110 | ~_writeAllowed_T_125) begin
|
||||
end
|
||||
else
|
||||
mstatus <=
|
||||
mstatus & 64'hFFFFFFFDFFF21E9D | {30'h0, next[33:1] & 33'h10006F0B1, 1'h0};
|
||||
end
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | ~_writeAllowed_T_84) begin
|
||||
end
|
||||
else
|
||||
mtvecReg <= next;
|
||||
if (io_trap) begin
|
||||
mepcReg <= io_trapPc;
|
||||
mcause <= io_trapCause;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | ~_writeAllowed_T_88) begin
|
||||
end
|
||||
else begin
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | ~_GEN_4) begin
|
||||
else
|
||||
mscratch <= next;
|
||||
if (~io_trap | trapToS) begin
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | ~_writeAllowed_T_90) begin
|
||||
end
|
||||
else
|
||||
mepcReg <= next;
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | ~_GEN_5) begin
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| ~_writeAllowed_T_92) begin
|
||||
end
|
||||
else
|
||||
mcause <= next;
|
||||
end
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5
|
||||
| ~_GEN_6) begin
|
||||
end
|
||||
else
|
||||
mtval <= next;
|
||||
if (~_GEN_17 | _GEN | ~_GEN_0) begin
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | ~_writeAllowed_T_94) begin
|
||||
end
|
||||
else
|
||||
mtval <= next;
|
||||
end
|
||||
else begin
|
||||
automatic logic [3:0][63:0] _GEN_18;
|
||||
_GEN_18 = {{_next_T_3}, {_next_T_1}, {operand}, {_GEN_15}};
|
||||
medeleg <= _GEN_18[io_cmd_cmd[1:0]];
|
||||
mepcReg <= io_trapPc;
|
||||
mcause <= io_trapCause;
|
||||
mtval <= io_trapTval;
|
||||
end
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | ~_GEN_1) begin
|
||||
if (~_GEN | _writeAllowed_T_75 | ~_writeAllowed_T_78) begin
|
||||
end
|
||||
else
|
||||
mideleg <= next;
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | ~_GEN_2) begin
|
||||
else begin
|
||||
automatic logic [3:0][63:0] _GEN_4;
|
||||
_GEN_4 =
|
||||
{{_next_T_3},
|
||||
{_next_T_1},
|
||||
{operand},
|
||||
{_writeAllowed_T_76 ? 64'h8000000000141101 : medeleg}};
|
||||
medeleg <= _GEN_4[io_cmd_cmd[1:0]];
|
||||
end
|
||||
else
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | ~_writeAllowed_T_80) begin
|
||||
end
|
||||
else begin
|
||||
automatic logic [3:0][63:0] _GEN_5;
|
||||
_GEN_5 =
|
||||
{{_next_T_3},
|
||||
{_next_T_1},
|
||||
{operand},
|
||||
{_writeAllowed_T_75
|
||||
? mstatusView
|
||||
: _writeAllowed_T_76
|
||||
? 64'h8000000000141101
|
||||
: _writeAllowed_T_78 ? medeleg : mideleg}};
|
||||
mideleg <= _GEN_5[io_cmd_cmd[1:0]];
|
||||
end
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80) begin
|
||||
end
|
||||
else if (_writeAllowed_T_82)
|
||||
mie <= next;
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
|
||||
| ~_GEN_7) begin
|
||||
else if (_writeAllowed_T_84 | _writeAllowed_T_86 | _writeAllowed_T_112
|
||||
| _writeAllowed_T_88 | _writeAllowed_T_90 | _writeAllowed_T_92
|
||||
| _writeAllowed_T_94 | _writeAllowed_T_96 | _writeAllowed_T_98
|
||||
| _writeAllowed_T_100 | _writeAllowed_T_104 | _writeAllowed_T_106
|
||||
| _writeAllowed_T_108 | _writeAllowed_T_110 | _writeAllowed_T_125
|
||||
| ~_writeAllowed_T_126) begin
|
||||
end
|
||||
else
|
||||
mie <= mie & ~mideleg | next & mideleg;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94) begin
|
||||
end
|
||||
else if (_writeAllowed_T_96)
|
||||
mip <= next;
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
|
||||
| _GEN_7 | ~_GEN_8) begin
|
||||
else if (_writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104
|
||||
| _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110
|
||||
| _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128
|
||||
| _writeAllowed_T_132 | _writeAllowed_T_130 | _writeAllowed_T_134
|
||||
| _writeAllowed_T_136 | _writeAllowed_T_138 | ~_writeAllowed_T_140) begin
|
||||
end
|
||||
else
|
||||
sstatus <= next;
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
|
||||
| _GEN_7 | _GEN_8 | ~_GEN_9) begin
|
||||
mip <= mip & ~mideleg | next & mideleg;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | ~_writeAllowed_T_86) begin
|
||||
end
|
||||
else
|
||||
mcounteren <= next;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| ~_writeAllowed_T_98) begin
|
||||
end
|
||||
else
|
||||
pmpcfg0 <= next;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | ~_writeAllowed_T_100) begin
|
||||
end
|
||||
else
|
||||
pmpaddr0 <= next;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | _writeAllowed_T_100 | ~_writeAllowed_T_104) begin
|
||||
end
|
||||
else
|
||||
tdata1 <= next;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104
|
||||
| ~_writeAllowed_T_106) begin
|
||||
end
|
||||
else
|
||||
tdata2 <= next;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104
|
||||
| _writeAllowed_T_106 | ~_writeAllowed_T_108) begin
|
||||
end
|
||||
else
|
||||
tcontrol <= next;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104
|
||||
| _writeAllowed_T_106 | _writeAllowed_T_108 | ~_writeAllowed_T_110) begin
|
||||
end
|
||||
else
|
||||
mnstatus <= next;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104
|
||||
| _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110
|
||||
| _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128
|
||||
| ~_writeAllowed_T_132) begin
|
||||
end
|
||||
else
|
||||
scounteren <= next;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104
|
||||
| _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110
|
||||
| _writeAllowed_T_125 | _writeAllowed_T_126 | ~_writeAllowed_T_128) begin
|
||||
end
|
||||
else
|
||||
stvec <= next;
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
|
||||
| _GEN_7 | _GEN_8 | _GEN_9 | _GEN_10 | ~_GEN_11) begin
|
||||
if (io_trap & trapToS) begin
|
||||
sepc <= io_trapPc;
|
||||
scause <= io_trapCause;
|
||||
stval <= io_trapTval;
|
||||
end
|
||||
else
|
||||
sepc <= next;
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
|
||||
| _GEN_7 | _GEN_8 | _GEN_9 | _GEN_10 | _GEN_11 | ~_GEN_12) begin
|
||||
else begin
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104
|
||||
| _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110
|
||||
| _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128
|
||||
| _writeAllowed_T_132 | _writeAllowed_T_130 | ~_writeAllowed_T_134) begin
|
||||
end
|
||||
else
|
||||
sepc <= next;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104
|
||||
| _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110
|
||||
| _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128
|
||||
| _writeAllowed_T_132 | _writeAllowed_T_130 | _writeAllowed_T_134
|
||||
| ~_writeAllowed_T_136) begin
|
||||
end
|
||||
else
|
||||
scause <= next;
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104
|
||||
| _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110
|
||||
| _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128
|
||||
| _writeAllowed_T_132 | _writeAllowed_T_130 | _writeAllowed_T_134
|
||||
| _writeAllowed_T_136 | ~_writeAllowed_T_138) begin
|
||||
end
|
||||
else
|
||||
stval <= next;
|
||||
end
|
||||
else
|
||||
scause <= next;
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
|
||||
| _GEN_7 | _GEN_8 | _GEN_9 | _GEN_10 | _GEN_11 | _GEN_12 | ~_GEN_13) begin
|
||||
end
|
||||
else
|
||||
stval <= next;
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
|
||||
| _GEN_7 | _GEN_8 | _GEN_9 | ~_GEN_10) begin
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104
|
||||
| _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110
|
||||
| _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128
|
||||
| _writeAllowed_T_132 | ~_writeAllowed_T_130) begin
|
||||
end
|
||||
else
|
||||
sscratch <= next;
|
||||
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
|
||||
| _GEN_7 | _GEN_8 | _GEN_9 | _GEN_10 | _GEN_11 | _GEN_12 | _GEN_13
|
||||
| ~_GEN_14) begin
|
||||
if (~_GEN | _writeAllowed_T_75 | _writeAllowed_T_78 | _writeAllowed_T_80
|
||||
| _writeAllowed_T_82 | _writeAllowed_T_84 | _writeAllowed_T_86
|
||||
| _writeAllowed_T_112 | _writeAllowed_T_88 | _writeAllowed_T_90
|
||||
| _writeAllowed_T_92 | _writeAllowed_T_94 | _writeAllowed_T_96
|
||||
| _writeAllowed_T_98 | _writeAllowed_T_100 | _writeAllowed_T_104
|
||||
| _writeAllowed_T_106 | _writeAllowed_T_108 | _writeAllowed_T_110
|
||||
| _writeAllowed_T_125 | _writeAllowed_T_126 | _writeAllowed_T_128
|
||||
| _writeAllowed_T_132 | _writeAllowed_T_130 | _writeAllowed_T_134
|
||||
| _writeAllowed_T_136 | _writeAllowed_T_138 | _writeAllowed_T_140
|
||||
| ~_writeAllowed_T_142) begin
|
||||
end
|
||||
else
|
||||
satpReg <= next;
|
||||
end
|
||||
end // always @(posedge)
|
||||
assign io_rdata =
|
||||
io_readAddr == 12'h300
|
||||
? mstatus
|
||||
: io_readAddr == 12'h301
|
||||
? 64'h800000000014112D
|
||||
: io_readAddr == 12'h302
|
||||
? medeleg
|
||||
: io_readAddr == 12'h303
|
||||
? mideleg
|
||||
: io_readAddr == 12'h304
|
||||
? mie
|
||||
: io_readAddr == 12'h305
|
||||
? mtvecReg
|
||||
: io_readAddr == 12'h341
|
||||
? mepcReg
|
||||
: io_readAddr == 12'h342
|
||||
? mcause
|
||||
: io_readAddr == 12'h343
|
||||
? mtval
|
||||
: io_readAddr == 12'h344
|
||||
? mip
|
||||
: io_readAddr == 12'h100
|
||||
? sstatus
|
||||
: io_readAddr == 12'h105
|
||||
? stvec
|
||||
: io_readAddr == 12'h140
|
||||
? sscratch
|
||||
: io_readAddr == 12'h141
|
||||
? sepc
|
||||
: io_readAddr == 12'h142
|
||||
? scause
|
||||
: io_readAddr == 12'h143
|
||||
? stval
|
||||
: io_readAddr == 12'h180
|
||||
? satpReg
|
||||
: io_readAddr == 12'hF14
|
||||
| io_readAddr != 12'hC00
|
||||
? 64'h0
|
||||
: cycle;
|
||||
readAllowed
|
||||
? (_readAllowed_T_75
|
||||
? mstatusView
|
||||
: _readAllowed_T_76
|
||||
? 64'h8000000000141101
|
||||
: _readAllowed_T_78
|
||||
? medeleg
|
||||
: _readAllowed_T_80
|
||||
? mideleg
|
||||
: _readAllowed_T_82
|
||||
? mie
|
||||
: _readAllowed_T_84
|
||||
? mtvecReg
|
||||
: _readAllowed_T_86
|
||||
? mcounteren
|
||||
: _readAllowed_T_112
|
||||
? mcountinhibit
|
||||
: _readAllowed_T_88
|
||||
? mscratch
|
||||
: _readAllowed_T_90
|
||||
? mepcReg
|
||||
: _readAllowed_T_92
|
||||
? mcause
|
||||
: _readAllowed_T_94
|
||||
? mtval
|
||||
: _readAllowed_T_96
|
||||
? mip
|
||||
: _readAllowed_T_98
|
||||
? pmpcfg0
|
||||
: _readAllowed_T_100
|
||||
? pmpaddr0
|
||||
: _readAllowed_T_102
|
||||
? 64'h1
|
||||
: _readAllowed_T_104
|
||||
? tdata1
|
||||
: _readAllowed_T_106
|
||||
? tdata2
|
||||
: _readAllowed_T_108
|
||||
? tcontrol
|
||||
: _readAllowed_T_110
|
||||
? mnstatus
|
||||
: _readAllowed_T_125
|
||||
? sstatusView
|
||||
: _readAllowed_T_126
|
||||
? mie
|
||||
& mideleg
|
||||
: _readAllowed_T_128
|
||||
? stvec
|
||||
: _readAllowed_T_132
|
||||
? scounteren
|
||||
: _readAllowed_T_130
|
||||
? sscratch
|
||||
: _readAllowed_T_134
|
||||
? sepc
|
||||
: _readAllowed_T_136
|
||||
? scause
|
||||
: _readAllowed_T_138
|
||||
? stval
|
||||
: _readAllowed_T_140
|
||||
? mip
|
||||
& mideleg
|
||||
: _readAllowed_T_142
|
||||
? satpReg
|
||||
: _readAllowed_T_116
|
||||
| _readAllowed_T_118
|
||||
| _readAllowed_T_120
|
||||
| _readAllowed_T_122
|
||||
? 64'h0
|
||||
: _readAllowed_T_114
|
||||
? instret
|
||||
: _readAllowed_T_69
|
||||
| _readAllowed_T_70
|
||||
? cycle
|
||||
: _readAllowed_T_72
|
||||
? instret
|
||||
: 64'h0)
|
||||
: 64'h0;
|
||||
assign io_readIllegal = ~readAllowed;
|
||||
assign io_trapVector = trapToS ? stvec : mtvecReg;
|
||||
assign io_satp = satpReg;
|
||||
assign io_mtvec = mtvecReg;
|
||||
assign io_mepc = mepcReg;
|
||||
assign io_sepc = sepc;
|
||||
assign io_medeleg = medeleg;
|
||||
assign io_mstatus = mstatus;
|
||||
endmodule
|
||||
|
||||
|
||||
@@ -2,6 +2,7 @@
|
||||
module CommitStage(
|
||||
input io_robValid_0,
|
||||
io_robValid_1,
|
||||
input [63:0] io_robEntry_0_pc,
|
||||
input [4:0] io_robEntry_0_archDest,
|
||||
input io_robEntry_0_writesDest,
|
||||
input [3:0] io_robEntry_0_opClass,
|
||||
@@ -14,6 +15,10 @@ module CommitStage(
|
||||
input [63:0] io_robEntry_0_redirectPc,
|
||||
input io_robEntry_0_csrValid,
|
||||
io_robEntry_0_fenceI,
|
||||
io_robEntry_0_sfenceVma,
|
||||
io_robEntry_0_xret,
|
||||
io_robEntry_0_xretIsMret,
|
||||
input [63:0] io_robEntry_1_pc,
|
||||
input [4:0] io_robEntry_1_archDest,
|
||||
input io_robEntry_1_writesDest,
|
||||
input [5:0] io_robEntry_1_dest,
|
||||
@@ -25,6 +30,9 @@ module CommitStage(
|
||||
input [63:0] io_robEntry_1_redirectPc,
|
||||
input io_robEntry_1_csrValid,
|
||||
io_robEntry_1_fenceI,
|
||||
io_robEntry_1_sfenceVma,
|
||||
io_robEntry_1_xret,
|
||||
io_robEntry_1_xretIsMret,
|
||||
output io_commitReady_0,
|
||||
io_commitReady_1,
|
||||
io_freeOldPhys_0,
|
||||
@@ -42,38 +50,53 @@ module CommitStage(
|
||||
output io_exception,
|
||||
output [63:0] io_exceptionCause,
|
||||
io_badAddr,
|
||||
output io_fenceI
|
||||
io_trapPc,
|
||||
output io_fenceI,
|
||||
io_sfenceVma,
|
||||
io_xret,
|
||||
io_xretIsMret,
|
||||
io_setPriv
|
||||
);
|
||||
|
||||
wire firstTrap =
|
||||
io_robValid_0 & (io_robEntry_0_exception | io_robEntry_0_branchMispredict);
|
||||
io_robValid_0
|
||||
& (io_robEntry_0_exception | io_robEntry_0_branchMispredict | io_robEntry_0_xret
|
||||
| io_robEntry_0_sfenceVma | io_robEntry_0_fenceI);
|
||||
wire secondTrap =
|
||||
io_robValid_1 & (io_robEntry_1_exception | io_robEntry_1_branchMispredict);
|
||||
io_robValid_1
|
||||
& (io_robEntry_1_exception | io_robEntry_1_branchMispredict | io_robEntry_1_xret
|
||||
| io_robEntry_1_sfenceVma | io_robEntry_1_fenceI);
|
||||
wire io_commitReady_1_0 =
|
||||
io_robValid_1 & ~firstTrap & ~secondTrap
|
||||
& ~(io_robValid_0 & io_robValid_1 & io_robEntry_0_csrValid & io_robEntry_1_csrValid)
|
||||
& ~(io_robValid_0 & io_robEntry_0_opClass == 4'h4);
|
||||
wire _io_commitMapValid_0_T = io_robValid_0 & io_robEntry_0_writesDest;
|
||||
wire _io_commitMapValid_1_T = io_commitReady_1_0 & io_robEntry_1_writesDest;
|
||||
wire commitWritesDest =
|
||||
io_robValid_0 & ~io_robEntry_0_exception & io_robEntry_0_writesDest;
|
||||
wire commitWritesDest_1 =
|
||||
io_commitReady_1_0 & ~io_robEntry_1_exception & io_robEntry_1_writesDest;
|
||||
wire secondTrapSelected = ~io_robValid_0 & secondTrap;
|
||||
wire selectedTrap = firstTrap | secondTrapSelected;
|
||||
wire io_exception_0 =
|
||||
firstTrap ? io_robEntry_0_exception : secondTrapSelected & io_robEntry_1_exception;
|
||||
wire io_xret_0 =
|
||||
io_robValid_0 & io_robEntry_0_xret | io_commitReady_1_0 & io_robEntry_1_xret;
|
||||
assign io_commitReady_0 = io_robValid_0;
|
||||
assign io_commitReady_1 = io_commitReady_1_0;
|
||||
assign io_freeOldPhys_0 =
|
||||
_io_commitMapValid_0_T & io_robEntry_0_oldDest != io_robEntry_0_dest;
|
||||
commitWritesDest & io_robEntry_0_oldDest != io_robEntry_0_dest;
|
||||
assign io_freeOldPhys_1 =
|
||||
_io_commitMapValid_1_T & io_robEntry_1_oldDest != io_robEntry_1_dest;
|
||||
commitWritesDest_1 & io_robEntry_1_oldDest != io_robEntry_1_dest;
|
||||
assign io_oldPhys_0 = io_robEntry_0_oldDest;
|
||||
assign io_oldPhys_1 = io_robEntry_1_oldDest;
|
||||
assign io_commitMapValid_0 = _io_commitMapValid_0_T & (|io_robEntry_0_archDest);
|
||||
assign io_commitMapValid_1 = _io_commitMapValid_1_T & (|io_robEntry_1_archDest);
|
||||
assign io_commitMapValid_0 = commitWritesDest & (|io_robEntry_0_archDest);
|
||||
assign io_commitMapValid_1 = commitWritesDest_1 & (|io_robEntry_1_archDest);
|
||||
assign io_commitArch_0 = io_robEntry_0_archDest;
|
||||
assign io_commitArch_1 = io_robEntry_1_archDest;
|
||||
assign io_commitPhys_0 = io_robEntry_0_dest;
|
||||
assign io_commitPhys_1 = io_robEntry_1_dest;
|
||||
assign io_flush = firstTrap | secondTrapSelected;
|
||||
assign io_flush = selectedTrap;
|
||||
assign io_redirectPc = firstTrap ? io_robEntry_0_redirectPc : io_robEntry_1_redirectPc;
|
||||
assign io_exception =
|
||||
firstTrap ? io_robEntry_0_exception : secondTrapSelected & io_robEntry_1_exception;
|
||||
assign io_exception = io_exception_0;
|
||||
assign io_exceptionCause =
|
||||
firstTrap
|
||||
? io_robEntry_0_exceptionCause
|
||||
@@ -82,7 +105,16 @@ module CommitStage(
|
||||
firstTrap
|
||||
? io_robEntry_0_badAddr
|
||||
: secondTrapSelected ? io_robEntry_1_badAddr : 64'h0;
|
||||
assign io_trapPc =
|
||||
firstTrap ? io_robEntry_0_pc : secondTrapSelected ? io_robEntry_1_pc : 64'h0;
|
||||
assign io_fenceI =
|
||||
io_robValid_0 & io_robEntry_0_fenceI | io_commitReady_1_0 & io_robEntry_1_fenceI;
|
||||
assign io_sfenceVma =
|
||||
io_robValid_0 & io_robEntry_0_sfenceVma | io_commitReady_1_0
|
||||
& io_robEntry_1_sfenceVma;
|
||||
assign io_xret = io_xret_0;
|
||||
assign io_xretIsMret =
|
||||
firstTrap ? io_robEntry_0_xretIsMret : ~secondTrapSelected | io_robEntry_1_xretIsMret;
|
||||
assign io_setPriv = selectedTrap & (io_exception_0 | io_xret_0);
|
||||
endmodule
|
||||
|
||||
|
||||
@@ -16,10 +16,20 @@ module Core(
|
||||
input [63:0] io_dmem_resp_bits
|
||||
);
|
||||
|
||||
wire [1:0] _privCtrl_io_priv;
|
||||
wire _backend_io_decodeReady;
|
||||
wire _backend_io_flush;
|
||||
wire [63:0] _backend_io_redirectPc;
|
||||
wire _backend_io_invalidateICache;
|
||||
wire _backend_io_sfenceVma;
|
||||
wire _backend_io_setPriv;
|
||||
wire [1:0] _backend_io_targetPriv;
|
||||
wire _backend_io_dmemReqValid;
|
||||
wire [63:0] _backend_io_dmemReq_addr;
|
||||
wire [63:0] _backend_io_dmemReq_data;
|
||||
wire _backend_io_dmemReq_isStore;
|
||||
wire [2:0] _backend_io_dmemReq_size;
|
||||
wire [63:0] _backend_io_satpOut;
|
||||
wire _id_io_outValid_0;
|
||||
wire _id_io_outValid_1;
|
||||
wire [63:0] _id_io_out_0_pc;
|
||||
@@ -48,10 +58,20 @@ module Core(
|
||||
wire _id_io_out_0_isWord;
|
||||
wire _id_io_out_0_isSystem;
|
||||
wire _id_io_out_0_isFenceI;
|
||||
wire _id_io_out_0_isEcall;
|
||||
wire _id_io_out_0_isEbreak;
|
||||
wire _id_io_out_0_isMret;
|
||||
wire _id_io_out_0_isSret;
|
||||
wire _id_io_out_0_isSfenceVma;
|
||||
wire _id_io_out_0_isXret;
|
||||
wire _id_io_out_0_isWfi;
|
||||
wire _id_io_out_0_isAmo;
|
||||
wire [4:0] _id_io_out_0_amoOp;
|
||||
wire _id_io_out_0_writesRd;
|
||||
wire _id_io_out_0_illegal;
|
||||
wire _id_io_out_0_fetchException;
|
||||
wire [63:0] _id_io_out_0_fetchExceptionCause;
|
||||
wire [63:0] _id_io_out_0_fetchExceptionTval;
|
||||
wire [63:0] _id_io_out_1_pc;
|
||||
wire [31:0] _id_io_out_1_inst;
|
||||
wire [4:0] _id_io_out_1_rs1;
|
||||
@@ -78,29 +98,70 @@ module Core(
|
||||
wire _id_io_out_1_isWord;
|
||||
wire _id_io_out_1_isSystem;
|
||||
wire _id_io_out_1_isFenceI;
|
||||
wire _id_io_out_1_isEcall;
|
||||
wire _id_io_out_1_isEbreak;
|
||||
wire _id_io_out_1_isMret;
|
||||
wire _id_io_out_1_isSret;
|
||||
wire _id_io_out_1_isSfenceVma;
|
||||
wire _id_io_out_1_isXret;
|
||||
wire _id_io_out_1_isWfi;
|
||||
wire _id_io_out_1_isAmo;
|
||||
wire [4:0] _id_io_out_1_amoOp;
|
||||
wire _id_io_out_1_writesRd;
|
||||
wire _id_io_out_1_illegal;
|
||||
wire _id_io_out_1_fetchException;
|
||||
wire [63:0] _id_io_out_1_fetchExceptionCause;
|
||||
wire [63:0] _id_io_out_1_fetchExceptionTval;
|
||||
wire _frontend_io_ptwMemReqValid;
|
||||
wire [63:0] _frontend_io_ptwMemReqAddr;
|
||||
wire _frontend_io_outValid;
|
||||
wire [63:0] _frontend_io_out_pc;
|
||||
wire [31:0] _frontend_io_out_inst_0;
|
||||
wire [31:0] _frontend_io_out_inst_1;
|
||||
wire _frontend_io_out_laneValid_0;
|
||||
wire _frontend_io_out_laneValid_1;
|
||||
wire _frontend_io_out_exception;
|
||||
wire [63:0] _frontend_io_out_exceptionCause;
|
||||
wire [63:0] _frontend_io_out_exceptionTval;
|
||||
reg fetchValid;
|
||||
reg [63:0] fetchReg_pc;
|
||||
reg [31:0] fetchReg_inst_0;
|
||||
reg [31:0] fetchReg_inst_1;
|
||||
reg fetchReg_laneValid_0;
|
||||
reg fetchReg_laneValid_1;
|
||||
reg fetchReg_exception;
|
||||
reg [63:0] fetchReg_exceptionCause;
|
||||
reg [63:0] fetchReg_exceptionTval;
|
||||
wire fetchReady = ~fetchValid | _backend_io_decodeReady;
|
||||
reg frontendPtwOutstanding;
|
||||
reg backendReadOutstanding;
|
||||
wire frontendPtwCanIssue =
|
||||
_frontend_io_ptwMemReqValid & ~frontendPtwOutstanding & ~backendReadOutstanding
|
||||
& ~_backend_io_dmemReqValid;
|
||||
wire _io_dmem_req_bits_isStore_T =
|
||||
_backend_io_dmemReqValid & ~frontendPtwOutstanding;
|
||||
wire frontendPtwRespValid =
|
||||
io_dmem_resp_valid & (frontendPtwOutstanding | frontendPtwCanIssue);
|
||||
wire backendRespValid =
|
||||
io_dmem_resp_valid & ~frontendPtwOutstanding & ~frontendPtwCanIssue;
|
||||
always @(posedge clock) begin
|
||||
if (reset)
|
||||
if (reset) begin
|
||||
fetchValid <= 1'h0;
|
||||
else
|
||||
frontendPtwOutstanding <= 1'h0;
|
||||
backendReadOutstanding <= 1'h0;
|
||||
end
|
||||
else begin
|
||||
automatic logic backendReadIssue =
|
||||
_io_dmem_req_bits_isStore_T & ~_backend_io_dmemReq_isStore
|
||||
& ~backendReadOutstanding;
|
||||
fetchValid <=
|
||||
~_backend_io_flush & (fetchReady ? _frontend_io_outValid : fetchValid);
|
||||
frontendPtwOutstanding <=
|
||||
~frontendPtwRespValid & (frontendPtwCanIssue | frontendPtwOutstanding);
|
||||
backendReadOutstanding <=
|
||||
~(backendRespValid & (backendReadOutstanding | backendReadIssue))
|
||||
& (backendReadIssue & ~backendRespValid | backendReadOutstanding);
|
||||
end
|
||||
if (_backend_io_flush | ~fetchReady) begin
|
||||
end
|
||||
else begin
|
||||
@@ -109,173 +170,248 @@ module Core(
|
||||
fetchReg_inst_1 <= _frontend_io_out_inst_1;
|
||||
fetchReg_laneValid_0 <= _frontend_io_out_laneValid_0;
|
||||
fetchReg_laneValid_1 <= _frontend_io_out_laneValid_1;
|
||||
fetchReg_exception <= _frontend_io_out_exception;
|
||||
fetchReg_exceptionCause <= _frontend_io_out_exceptionCause;
|
||||
fetchReg_exceptionTval <= _frontend_io_out_exceptionTval;
|
||||
end
|
||||
end // always @(posedge)
|
||||
Frontend frontend (
|
||||
.clock (clock),
|
||||
.reset (reset),
|
||||
.io_redirectValid (_backend_io_flush),
|
||||
.io_redirectPc (_backend_io_redirectPc),
|
||||
.io_invalidateICache (_backend_io_invalidateICache),
|
||||
.io_imemReqValid (io_imem_req_valid),
|
||||
.io_imemReqAddr (io_imem_req_bits),
|
||||
.io_imemRespValid (io_imem_resp_valid),
|
||||
.io_imemRespBits_0 (io_imem_resp_bits_0),
|
||||
.io_imemRespBits_1 (io_imem_resp_bits_1),
|
||||
.io_outReady (fetchReady),
|
||||
.io_outValid (_frontend_io_outValid),
|
||||
.io_out_pc (_frontend_io_out_pc),
|
||||
.io_out_inst_0 (_frontend_io_out_inst_0),
|
||||
.io_out_inst_1 (_frontend_io_out_inst_1),
|
||||
.io_out_laneValid_0 (_frontend_io_out_laneValid_0),
|
||||
.io_out_laneValid_1 (_frontend_io_out_laneValid_1)
|
||||
);
|
||||
IDStage id (
|
||||
.io_inValid (fetchValid),
|
||||
.io_in_pc (fetchReg_pc),
|
||||
.io_in_inst_0 (fetchReg_inst_0),
|
||||
.io_in_inst_1 (fetchReg_inst_1),
|
||||
.io_in_laneValid_0 (fetchReg_laneValid_0),
|
||||
.io_in_laneValid_1 (fetchReg_laneValid_1),
|
||||
.io_outValid_0 (_id_io_outValid_0),
|
||||
.io_outValid_1 (_id_io_outValid_1),
|
||||
.io_out_0_pc (_id_io_out_0_pc),
|
||||
.io_out_0_inst (_id_io_out_0_inst),
|
||||
.io_out_0_rs1 (_id_io_out_0_rs1),
|
||||
.io_out_0_rs2 (_id_io_out_0_rs2),
|
||||
.io_out_0_rd (_id_io_out_0_rd),
|
||||
.io_out_0_funct3 (_id_io_out_0_funct3),
|
||||
.io_out_0_immI (_id_io_out_0_immI),
|
||||
.io_out_0_immS (_id_io_out_0_immS),
|
||||
.io_out_0_immB (_id_io_out_0_immB),
|
||||
.io_out_0_immU (_id_io_out_0_immU),
|
||||
.io_out_0_immJ (_id_io_out_0_immJ),
|
||||
.io_out_0_opClass (_id_io_out_0_opClass),
|
||||
.io_out_0_aluFn (_id_io_out_0_aluFn),
|
||||
.io_out_0_memWidth (_id_io_out_0_memWidth),
|
||||
.io_out_0_memSigned (_id_io_out_0_memSigned),
|
||||
.io_out_0_isLoad (_id_io_out_0_isLoad),
|
||||
.io_out_0_isStore (_id_io_out_0_isStore),
|
||||
.io_out_0_isBranch (_id_io_out_0_isBranch),
|
||||
.io_out_0_isJal (_id_io_out_0_isJal),
|
||||
.io_out_0_isJalr (_id_io_out_0_isJalr),
|
||||
.io_out_0_isLui (_id_io_out_0_isLui),
|
||||
.io_out_0_isAuipc (_id_io_out_0_isAuipc),
|
||||
.io_out_0_isOpImm (_id_io_out_0_isOpImm),
|
||||
.io_out_0_isWord (_id_io_out_0_isWord),
|
||||
.io_out_0_isSystem (_id_io_out_0_isSystem),
|
||||
.io_out_0_isFenceI (_id_io_out_0_isFenceI),
|
||||
.io_out_0_isAmo (_id_io_out_0_isAmo),
|
||||
.io_out_0_amoOp (_id_io_out_0_amoOp),
|
||||
.io_out_0_writesRd (_id_io_out_0_writesRd),
|
||||
.io_out_0_illegal (_id_io_out_0_illegal),
|
||||
.io_out_1_pc (_id_io_out_1_pc),
|
||||
.io_out_1_inst (_id_io_out_1_inst),
|
||||
.io_out_1_rs1 (_id_io_out_1_rs1),
|
||||
.io_out_1_rs2 (_id_io_out_1_rs2),
|
||||
.io_out_1_rd (_id_io_out_1_rd),
|
||||
.io_out_1_funct3 (_id_io_out_1_funct3),
|
||||
.io_out_1_immI (_id_io_out_1_immI),
|
||||
.io_out_1_immS (_id_io_out_1_immS),
|
||||
.io_out_1_immB (_id_io_out_1_immB),
|
||||
.io_out_1_immU (_id_io_out_1_immU),
|
||||
.io_out_1_immJ (_id_io_out_1_immJ),
|
||||
.io_out_1_opClass (_id_io_out_1_opClass),
|
||||
.io_out_1_aluFn (_id_io_out_1_aluFn),
|
||||
.io_out_1_memWidth (_id_io_out_1_memWidth),
|
||||
.io_out_1_memSigned (_id_io_out_1_memSigned),
|
||||
.io_out_1_isLoad (_id_io_out_1_isLoad),
|
||||
.io_out_1_isStore (_id_io_out_1_isStore),
|
||||
.io_out_1_isBranch (_id_io_out_1_isBranch),
|
||||
.io_out_1_isJal (_id_io_out_1_isJal),
|
||||
.io_out_1_isJalr (_id_io_out_1_isJalr),
|
||||
.io_out_1_isLui (_id_io_out_1_isLui),
|
||||
.io_out_1_isAuipc (_id_io_out_1_isAuipc),
|
||||
.io_out_1_isOpImm (_id_io_out_1_isOpImm),
|
||||
.io_out_1_isWord (_id_io_out_1_isWord),
|
||||
.io_out_1_isSystem (_id_io_out_1_isSystem),
|
||||
.io_out_1_isFenceI (_id_io_out_1_isFenceI),
|
||||
.io_out_1_isAmo (_id_io_out_1_isAmo),
|
||||
.io_out_1_amoOp (_id_io_out_1_amoOp),
|
||||
.io_out_1_writesRd (_id_io_out_1_writesRd),
|
||||
.io_out_1_illegal (_id_io_out_1_illegal)
|
||||
);
|
||||
OoOBackend backend (
|
||||
.clock (clock),
|
||||
.reset (reset),
|
||||
.io_decodeValid_0 (_id_io_outValid_0),
|
||||
.io_decodeValid_1 (_id_io_outValid_1),
|
||||
.io_decode_0_pc (_id_io_out_0_pc),
|
||||
.io_decode_0_inst (_id_io_out_0_inst),
|
||||
.io_decode_0_rs1 (_id_io_out_0_rs1),
|
||||
.io_decode_0_rs2 (_id_io_out_0_rs2),
|
||||
.io_decode_0_rd (_id_io_out_0_rd),
|
||||
.io_decode_0_funct3 (_id_io_out_0_funct3),
|
||||
.io_decode_0_immI (_id_io_out_0_immI),
|
||||
.io_decode_0_immS (_id_io_out_0_immS),
|
||||
.io_decode_0_immB (_id_io_out_0_immB),
|
||||
.io_decode_0_immU (_id_io_out_0_immU),
|
||||
.io_decode_0_immJ (_id_io_out_0_immJ),
|
||||
.io_decode_0_opClass (_id_io_out_0_opClass),
|
||||
.io_decode_0_aluFn (_id_io_out_0_aluFn),
|
||||
.io_decode_0_memWidth (_id_io_out_0_memWidth),
|
||||
.io_decode_0_memSigned (_id_io_out_0_memSigned),
|
||||
.io_decode_0_isLoad (_id_io_out_0_isLoad),
|
||||
.io_decode_0_isStore (_id_io_out_0_isStore),
|
||||
.io_decode_0_isBranch (_id_io_out_0_isBranch),
|
||||
.io_decode_0_isJal (_id_io_out_0_isJal),
|
||||
.io_decode_0_isJalr (_id_io_out_0_isJalr),
|
||||
.io_decode_0_isLui (_id_io_out_0_isLui),
|
||||
.io_decode_0_isAuipc (_id_io_out_0_isAuipc),
|
||||
.io_decode_0_isOpImm (_id_io_out_0_isOpImm),
|
||||
.io_decode_0_isWord (_id_io_out_0_isWord),
|
||||
.io_decode_0_isSystem (_id_io_out_0_isSystem),
|
||||
.io_decode_0_isFenceI (_id_io_out_0_isFenceI),
|
||||
.io_decode_0_isAmo (_id_io_out_0_isAmo),
|
||||
.io_decode_0_amoOp (_id_io_out_0_amoOp),
|
||||
.io_decode_0_writesRd (_id_io_out_0_writesRd),
|
||||
.io_decode_0_illegal (_id_io_out_0_illegal),
|
||||
.io_decode_1_pc (_id_io_out_1_pc),
|
||||
.io_decode_1_inst (_id_io_out_1_inst),
|
||||
.io_decode_1_rs1 (_id_io_out_1_rs1),
|
||||
.io_decode_1_rs2 (_id_io_out_1_rs2),
|
||||
.io_decode_1_rd (_id_io_out_1_rd),
|
||||
.io_decode_1_funct3 (_id_io_out_1_funct3),
|
||||
.io_decode_1_immI (_id_io_out_1_immI),
|
||||
.io_decode_1_immS (_id_io_out_1_immS),
|
||||
.io_decode_1_immB (_id_io_out_1_immB),
|
||||
.io_decode_1_immU (_id_io_out_1_immU),
|
||||
.io_decode_1_immJ (_id_io_out_1_immJ),
|
||||
.io_decode_1_opClass (_id_io_out_1_opClass),
|
||||
.io_decode_1_aluFn (_id_io_out_1_aluFn),
|
||||
.io_decode_1_memWidth (_id_io_out_1_memWidth),
|
||||
.io_decode_1_memSigned (_id_io_out_1_memSigned),
|
||||
.io_decode_1_isLoad (_id_io_out_1_isLoad),
|
||||
.io_decode_1_isStore (_id_io_out_1_isStore),
|
||||
.io_decode_1_isBranch (_id_io_out_1_isBranch),
|
||||
.io_decode_1_isJal (_id_io_out_1_isJal),
|
||||
.io_decode_1_isJalr (_id_io_out_1_isJalr),
|
||||
.io_decode_1_isLui (_id_io_out_1_isLui),
|
||||
.io_decode_1_isAuipc (_id_io_out_1_isAuipc),
|
||||
.io_decode_1_isOpImm (_id_io_out_1_isOpImm),
|
||||
.io_decode_1_isWord (_id_io_out_1_isWord),
|
||||
.io_decode_1_isSystem (_id_io_out_1_isSystem),
|
||||
.io_decode_1_isFenceI (_id_io_out_1_isFenceI),
|
||||
.io_decode_1_isAmo (_id_io_out_1_isAmo),
|
||||
.io_decode_1_amoOp (_id_io_out_1_amoOp),
|
||||
.io_decode_1_writesRd (_id_io_out_1_writesRd),
|
||||
.io_decode_1_illegal (_id_io_out_1_illegal),
|
||||
.io_decodeReady (_backend_io_decodeReady),
|
||||
.io_flush (_backend_io_flush),
|
||||
.io_redirectValid (_backend_io_flush),
|
||||
.io_redirectPc (_backend_io_redirectPc),
|
||||
.io_invalidateICache (_backend_io_invalidateICache),
|
||||
.io_dmemReqValid (io_dmem_req_valid),
|
||||
.io_dmemReq_addr (io_dmem_req_bits_addr),
|
||||
.io_dmemReq_data (io_dmem_req_bits_data),
|
||||
.io_dmemReq_isStore (io_dmem_req_bits_isStore),
|
||||
.io_dmemReq_size (io_dmem_req_bits_size),
|
||||
.io_dmemRespValid (io_dmem_resp_valid),
|
||||
.io_dmemRespData (io_dmem_resp_bits)
|
||||
.io_sfenceVma (_backend_io_sfenceVma),
|
||||
.io_satp (_backend_io_satpOut),
|
||||
.io_currentPriv (_privCtrl_io_priv),
|
||||
.io_imemReqValid (io_imem_req_valid),
|
||||
.io_imemReqAddr (io_imem_req_bits),
|
||||
.io_imemRespValid (io_imem_resp_valid),
|
||||
.io_imemRespBits_0 (io_imem_resp_bits_0),
|
||||
.io_imemRespBits_1 (io_imem_resp_bits_1),
|
||||
.io_ptwMemReqValid (_frontend_io_ptwMemReqValid),
|
||||
.io_ptwMemReqAddr (_frontend_io_ptwMemReqAddr),
|
||||
.io_ptwMemRespValid (frontendPtwRespValid),
|
||||
.io_ptwMemRespData (io_dmem_resp_bits),
|
||||
.io_outReady (fetchReady),
|
||||
.io_outValid (_frontend_io_outValid),
|
||||
.io_out_pc (_frontend_io_out_pc),
|
||||
.io_out_inst_0 (_frontend_io_out_inst_0),
|
||||
.io_out_inst_1 (_frontend_io_out_inst_1),
|
||||
.io_out_laneValid_0 (_frontend_io_out_laneValid_0),
|
||||
.io_out_laneValid_1 (_frontend_io_out_laneValid_1),
|
||||
.io_out_exception (_frontend_io_out_exception),
|
||||
.io_out_exceptionCause (_frontend_io_out_exceptionCause),
|
||||
.io_out_exceptionTval (_frontend_io_out_exceptionTval)
|
||||
);
|
||||
IDStage id (
|
||||
.io_inValid (fetchValid),
|
||||
.io_in_pc (fetchReg_pc),
|
||||
.io_in_inst_0 (fetchReg_inst_0),
|
||||
.io_in_inst_1 (fetchReg_inst_1),
|
||||
.io_in_laneValid_0 (fetchReg_laneValid_0),
|
||||
.io_in_laneValid_1 (fetchReg_laneValid_1),
|
||||
.io_in_exception (fetchReg_exception),
|
||||
.io_in_exceptionCause (fetchReg_exceptionCause),
|
||||
.io_in_exceptionTval (fetchReg_exceptionTval),
|
||||
.io_outValid_0 (_id_io_outValid_0),
|
||||
.io_outValid_1 (_id_io_outValid_1),
|
||||
.io_out_0_pc (_id_io_out_0_pc),
|
||||
.io_out_0_inst (_id_io_out_0_inst),
|
||||
.io_out_0_rs1 (_id_io_out_0_rs1),
|
||||
.io_out_0_rs2 (_id_io_out_0_rs2),
|
||||
.io_out_0_rd (_id_io_out_0_rd),
|
||||
.io_out_0_funct3 (_id_io_out_0_funct3),
|
||||
.io_out_0_immI (_id_io_out_0_immI),
|
||||
.io_out_0_immS (_id_io_out_0_immS),
|
||||
.io_out_0_immB (_id_io_out_0_immB),
|
||||
.io_out_0_immU (_id_io_out_0_immU),
|
||||
.io_out_0_immJ (_id_io_out_0_immJ),
|
||||
.io_out_0_opClass (_id_io_out_0_opClass),
|
||||
.io_out_0_aluFn (_id_io_out_0_aluFn),
|
||||
.io_out_0_memWidth (_id_io_out_0_memWidth),
|
||||
.io_out_0_memSigned (_id_io_out_0_memSigned),
|
||||
.io_out_0_isLoad (_id_io_out_0_isLoad),
|
||||
.io_out_0_isStore (_id_io_out_0_isStore),
|
||||
.io_out_0_isBranch (_id_io_out_0_isBranch),
|
||||
.io_out_0_isJal (_id_io_out_0_isJal),
|
||||
.io_out_0_isJalr (_id_io_out_0_isJalr),
|
||||
.io_out_0_isLui (_id_io_out_0_isLui),
|
||||
.io_out_0_isAuipc (_id_io_out_0_isAuipc),
|
||||
.io_out_0_isOpImm (_id_io_out_0_isOpImm),
|
||||
.io_out_0_isWord (_id_io_out_0_isWord),
|
||||
.io_out_0_isSystem (_id_io_out_0_isSystem),
|
||||
.io_out_0_isFenceI (_id_io_out_0_isFenceI),
|
||||
.io_out_0_isEcall (_id_io_out_0_isEcall),
|
||||
.io_out_0_isEbreak (_id_io_out_0_isEbreak),
|
||||
.io_out_0_isMret (_id_io_out_0_isMret),
|
||||
.io_out_0_isSret (_id_io_out_0_isSret),
|
||||
.io_out_0_isSfenceVma (_id_io_out_0_isSfenceVma),
|
||||
.io_out_0_isXret (_id_io_out_0_isXret),
|
||||
.io_out_0_isWfi (_id_io_out_0_isWfi),
|
||||
.io_out_0_isAmo (_id_io_out_0_isAmo),
|
||||
.io_out_0_amoOp (_id_io_out_0_amoOp),
|
||||
.io_out_0_writesRd (_id_io_out_0_writesRd),
|
||||
.io_out_0_illegal (_id_io_out_0_illegal),
|
||||
.io_out_0_fetchException (_id_io_out_0_fetchException),
|
||||
.io_out_0_fetchExceptionCause (_id_io_out_0_fetchExceptionCause),
|
||||
.io_out_0_fetchExceptionTval (_id_io_out_0_fetchExceptionTval),
|
||||
.io_out_1_pc (_id_io_out_1_pc),
|
||||
.io_out_1_inst (_id_io_out_1_inst),
|
||||
.io_out_1_rs1 (_id_io_out_1_rs1),
|
||||
.io_out_1_rs2 (_id_io_out_1_rs2),
|
||||
.io_out_1_rd (_id_io_out_1_rd),
|
||||
.io_out_1_funct3 (_id_io_out_1_funct3),
|
||||
.io_out_1_immI (_id_io_out_1_immI),
|
||||
.io_out_1_immS (_id_io_out_1_immS),
|
||||
.io_out_1_immB (_id_io_out_1_immB),
|
||||
.io_out_1_immU (_id_io_out_1_immU),
|
||||
.io_out_1_immJ (_id_io_out_1_immJ),
|
||||
.io_out_1_opClass (_id_io_out_1_opClass),
|
||||
.io_out_1_aluFn (_id_io_out_1_aluFn),
|
||||
.io_out_1_memWidth (_id_io_out_1_memWidth),
|
||||
.io_out_1_memSigned (_id_io_out_1_memSigned),
|
||||
.io_out_1_isLoad (_id_io_out_1_isLoad),
|
||||
.io_out_1_isStore (_id_io_out_1_isStore),
|
||||
.io_out_1_isBranch (_id_io_out_1_isBranch),
|
||||
.io_out_1_isJal (_id_io_out_1_isJal),
|
||||
.io_out_1_isJalr (_id_io_out_1_isJalr),
|
||||
.io_out_1_isLui (_id_io_out_1_isLui),
|
||||
.io_out_1_isAuipc (_id_io_out_1_isAuipc),
|
||||
.io_out_1_isOpImm (_id_io_out_1_isOpImm),
|
||||
.io_out_1_isWord (_id_io_out_1_isWord),
|
||||
.io_out_1_isSystem (_id_io_out_1_isSystem),
|
||||
.io_out_1_isFenceI (_id_io_out_1_isFenceI),
|
||||
.io_out_1_isEcall (_id_io_out_1_isEcall),
|
||||
.io_out_1_isEbreak (_id_io_out_1_isEbreak),
|
||||
.io_out_1_isMret (_id_io_out_1_isMret),
|
||||
.io_out_1_isSret (_id_io_out_1_isSret),
|
||||
.io_out_1_isSfenceVma (_id_io_out_1_isSfenceVma),
|
||||
.io_out_1_isXret (_id_io_out_1_isXret),
|
||||
.io_out_1_isWfi (_id_io_out_1_isWfi),
|
||||
.io_out_1_isAmo (_id_io_out_1_isAmo),
|
||||
.io_out_1_amoOp (_id_io_out_1_amoOp),
|
||||
.io_out_1_writesRd (_id_io_out_1_writesRd),
|
||||
.io_out_1_illegal (_id_io_out_1_illegal),
|
||||
.io_out_1_fetchException (_id_io_out_1_fetchException),
|
||||
.io_out_1_fetchExceptionCause (_id_io_out_1_fetchExceptionCause),
|
||||
.io_out_1_fetchExceptionTval (_id_io_out_1_fetchExceptionTval)
|
||||
);
|
||||
OoOBackend backend (
|
||||
.clock (clock),
|
||||
.reset (reset),
|
||||
.io_decodeValid_0 (_id_io_outValid_0),
|
||||
.io_decodeValid_1 (_id_io_outValid_1),
|
||||
.io_decode_0_pc (_id_io_out_0_pc),
|
||||
.io_decode_0_inst (_id_io_out_0_inst),
|
||||
.io_decode_0_rs1 (_id_io_out_0_rs1),
|
||||
.io_decode_0_rs2 (_id_io_out_0_rs2),
|
||||
.io_decode_0_rd (_id_io_out_0_rd),
|
||||
.io_decode_0_funct3 (_id_io_out_0_funct3),
|
||||
.io_decode_0_immI (_id_io_out_0_immI),
|
||||
.io_decode_0_immS (_id_io_out_0_immS),
|
||||
.io_decode_0_immB (_id_io_out_0_immB),
|
||||
.io_decode_0_immU (_id_io_out_0_immU),
|
||||
.io_decode_0_immJ (_id_io_out_0_immJ),
|
||||
.io_decode_0_opClass (_id_io_out_0_opClass),
|
||||
.io_decode_0_aluFn (_id_io_out_0_aluFn),
|
||||
.io_decode_0_memWidth (_id_io_out_0_memWidth),
|
||||
.io_decode_0_memSigned (_id_io_out_0_memSigned),
|
||||
.io_decode_0_isLoad (_id_io_out_0_isLoad),
|
||||
.io_decode_0_isStore (_id_io_out_0_isStore),
|
||||
.io_decode_0_isBranch (_id_io_out_0_isBranch),
|
||||
.io_decode_0_isJal (_id_io_out_0_isJal),
|
||||
.io_decode_0_isJalr (_id_io_out_0_isJalr),
|
||||
.io_decode_0_isLui (_id_io_out_0_isLui),
|
||||
.io_decode_0_isAuipc (_id_io_out_0_isAuipc),
|
||||
.io_decode_0_isOpImm (_id_io_out_0_isOpImm),
|
||||
.io_decode_0_isWord (_id_io_out_0_isWord),
|
||||
.io_decode_0_isSystem (_id_io_out_0_isSystem),
|
||||
.io_decode_0_isFenceI (_id_io_out_0_isFenceI),
|
||||
.io_decode_0_isEcall (_id_io_out_0_isEcall),
|
||||
.io_decode_0_isEbreak (_id_io_out_0_isEbreak),
|
||||
.io_decode_0_isMret (_id_io_out_0_isMret),
|
||||
.io_decode_0_isSret (_id_io_out_0_isSret),
|
||||
.io_decode_0_isSfenceVma (_id_io_out_0_isSfenceVma),
|
||||
.io_decode_0_isXret (_id_io_out_0_isXret),
|
||||
.io_decode_0_isWfi (_id_io_out_0_isWfi),
|
||||
.io_decode_0_isAmo (_id_io_out_0_isAmo),
|
||||
.io_decode_0_amoOp (_id_io_out_0_amoOp),
|
||||
.io_decode_0_writesRd (_id_io_out_0_writesRd),
|
||||
.io_decode_0_illegal (_id_io_out_0_illegal),
|
||||
.io_decode_0_fetchException (_id_io_out_0_fetchException),
|
||||
.io_decode_0_fetchExceptionCause (_id_io_out_0_fetchExceptionCause),
|
||||
.io_decode_0_fetchExceptionTval (_id_io_out_0_fetchExceptionTval),
|
||||
.io_decode_1_pc (_id_io_out_1_pc),
|
||||
.io_decode_1_inst (_id_io_out_1_inst),
|
||||
.io_decode_1_rs1 (_id_io_out_1_rs1),
|
||||
.io_decode_1_rs2 (_id_io_out_1_rs2),
|
||||
.io_decode_1_rd (_id_io_out_1_rd),
|
||||
.io_decode_1_funct3 (_id_io_out_1_funct3),
|
||||
.io_decode_1_immI (_id_io_out_1_immI),
|
||||
.io_decode_1_immS (_id_io_out_1_immS),
|
||||
.io_decode_1_immB (_id_io_out_1_immB),
|
||||
.io_decode_1_immU (_id_io_out_1_immU),
|
||||
.io_decode_1_immJ (_id_io_out_1_immJ),
|
||||
.io_decode_1_opClass (_id_io_out_1_opClass),
|
||||
.io_decode_1_aluFn (_id_io_out_1_aluFn),
|
||||
.io_decode_1_memWidth (_id_io_out_1_memWidth),
|
||||
.io_decode_1_memSigned (_id_io_out_1_memSigned),
|
||||
.io_decode_1_isLoad (_id_io_out_1_isLoad),
|
||||
.io_decode_1_isStore (_id_io_out_1_isStore),
|
||||
.io_decode_1_isBranch (_id_io_out_1_isBranch),
|
||||
.io_decode_1_isJal (_id_io_out_1_isJal),
|
||||
.io_decode_1_isJalr (_id_io_out_1_isJalr),
|
||||
.io_decode_1_isLui (_id_io_out_1_isLui),
|
||||
.io_decode_1_isAuipc (_id_io_out_1_isAuipc),
|
||||
.io_decode_1_isOpImm (_id_io_out_1_isOpImm),
|
||||
.io_decode_1_isWord (_id_io_out_1_isWord),
|
||||
.io_decode_1_isSystem (_id_io_out_1_isSystem),
|
||||
.io_decode_1_isFenceI (_id_io_out_1_isFenceI),
|
||||
.io_decode_1_isEcall (_id_io_out_1_isEcall),
|
||||
.io_decode_1_isEbreak (_id_io_out_1_isEbreak),
|
||||
.io_decode_1_isMret (_id_io_out_1_isMret),
|
||||
.io_decode_1_isSret (_id_io_out_1_isSret),
|
||||
.io_decode_1_isSfenceVma (_id_io_out_1_isSfenceVma),
|
||||
.io_decode_1_isXret (_id_io_out_1_isXret),
|
||||
.io_decode_1_isWfi (_id_io_out_1_isWfi),
|
||||
.io_decode_1_isAmo (_id_io_out_1_isAmo),
|
||||
.io_decode_1_amoOp (_id_io_out_1_amoOp),
|
||||
.io_decode_1_writesRd (_id_io_out_1_writesRd),
|
||||
.io_decode_1_illegal (_id_io_out_1_illegal),
|
||||
.io_decode_1_fetchException (_id_io_out_1_fetchException),
|
||||
.io_decode_1_fetchExceptionCause (_id_io_out_1_fetchExceptionCause),
|
||||
.io_decode_1_fetchExceptionTval (_id_io_out_1_fetchExceptionTval),
|
||||
.io_decodeReady (_backend_io_decodeReady),
|
||||
.io_flush (_backend_io_flush),
|
||||
.io_redirectPc (_backend_io_redirectPc),
|
||||
.io_invalidateICache (_backend_io_invalidateICache),
|
||||
.io_sfenceVma (_backend_io_sfenceVma),
|
||||
.io_setPriv (_backend_io_setPriv),
|
||||
.io_targetPriv (_backend_io_targetPriv),
|
||||
.io_dmemReqValid (_backend_io_dmemReqValid),
|
||||
.io_dmemReq_addr (_backend_io_dmemReq_addr),
|
||||
.io_dmemReq_data (_backend_io_dmemReq_data),
|
||||
.io_dmemReq_isStore (_backend_io_dmemReq_isStore),
|
||||
.io_dmemReq_size (_backend_io_dmemReq_size),
|
||||
.io_dmemRespValid (backendRespValid),
|
||||
.io_dmemRespData (io_dmem_resp_bits),
|
||||
.io_satpOut (_backend_io_satpOut),
|
||||
.io_currentPriv (_privCtrl_io_priv)
|
||||
);
|
||||
PrivilegeControl privCtrl (
|
||||
.clock (clock),
|
||||
.reset (reset),
|
||||
.io_nextPriv (_backend_io_targetPriv),
|
||||
.io_setPriv (_backend_io_setPriv),
|
||||
.io_priv (_privCtrl_io_priv)
|
||||
);
|
||||
assign io_dmem_req_valid = _io_dmem_req_bits_isStore_T | frontendPtwCanIssue;
|
||||
assign io_dmem_req_bits_addr =
|
||||
frontendPtwCanIssue ? _frontend_io_ptwMemReqAddr : _backend_io_dmemReq_addr;
|
||||
assign io_dmem_req_bits_data = frontendPtwCanIssue ? 64'h0 : _backend_io_dmemReq_data;
|
||||
assign io_dmem_req_bits_isStore =
|
||||
_io_dmem_req_bits_isStore_T & _backend_io_dmemReq_isStore;
|
||||
assign io_dmem_req_bits_size = frontendPtwCanIssue ? 3'h3 : _backend_io_dmemReq_size;
|
||||
endmodule
|
||||
|
||||
|
||||
74015
generated-ooo/DCache.sv
74015
generated-ooo/DCache.sv
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -28,6 +28,13 @@ module Decoder(
|
||||
io_out_isWord,
|
||||
io_out_isSystem,
|
||||
io_out_isFenceI,
|
||||
io_out_isEcall,
|
||||
io_out_isEbreak,
|
||||
io_out_isMret,
|
||||
io_out_isSret,
|
||||
io_out_isSfenceVma,
|
||||
io_out_isXret,
|
||||
io_out_isWfi,
|
||||
io_out_isAmo,
|
||||
output [4:0] io_out_amoOp,
|
||||
output io_out_writesRd,
|
||||
@@ -36,7 +43,16 @@ module Decoder(
|
||||
|
||||
wire [7:0][4:0] _GEN = '{5'hE, 5'hD, 5'hC, 5'hB, 5'h12, 5'h11, 5'h10, 5'hA};
|
||||
wire [7:0][1:0] _GEN_0 = '{2'h3, 2'h2, 2'h1, 2'h0, 2'h3, 2'h2, 2'h1, 2'h0};
|
||||
wire _isSfenceVma_T = io_inst[14:12] == 3'h0;
|
||||
wire _d_isFenceI_T = io_inst[14:12] == 3'h1;
|
||||
wire isSystemOpcode = io_inst[6:0] == 7'h73;
|
||||
wire isFenceOpcode = io_inst[6:0] == 7'hF;
|
||||
wire isEcall = io_inst == 32'h73;
|
||||
wire isEbreak = io_inst == 32'h100073;
|
||||
wire isMret = io_inst == 32'h30200073;
|
||||
wire isSret = io_inst == 32'h10200073;
|
||||
wire isWfi = io_inst == 32'h10500073;
|
||||
wire isSfenceVma = isSystemOpcode & _isSfenceVma_T & io_inst[31:25] == 7'h9;
|
||||
wire d_isLui = io_inst[6:0] == 7'h37;
|
||||
wire _GEN_1 = io_inst[6:0] == 7'h17;
|
||||
wire _GEN_2 = io_inst[6:0] == 7'h6F;
|
||||
@@ -70,15 +86,15 @@ module Decoder(
|
||||
{5'h3},
|
||||
{5'h2},
|
||||
{{4'h0, io_inst[30]}}};
|
||||
wire _GEN_14 = io_inst[6:0] == 7'hF;
|
||||
wire _GEN_15 = _GEN_8 | _GEN_12;
|
||||
wire _GEN_16 = io_inst[6:0] == 7'h73;
|
||||
wire _GEN_17 = io_inst[6:0] == 7'h2F;
|
||||
wire _GEN_18 = _GEN_14 | _GEN_16;
|
||||
wire _GEN_19 = _GEN_7 | _GEN_8 | _GEN_12 | _GEN_18;
|
||||
wire _GEN_20 = _GEN_2 | _GEN_4 | _GEN_5;
|
||||
wire _GEN_21 =
|
||||
d_isLui | _GEN_1 | _GEN_2 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_19;
|
||||
wire _GEN_14 = _GEN_8 | _GEN_12;
|
||||
wire _GEN_15 =
|
||||
d_isLui | _GEN_1 | _GEN_2 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_7 | _GEN_14;
|
||||
wire _GEN_16 = io_inst[6:0] == 7'h2F;
|
||||
wire _GEN_17 = isFenceOpcode | isSystemOpcode;
|
||||
wire _GEN_18 = _GEN_7 | _GEN_8 | _GEN_12 | _GEN_17;
|
||||
wire _GEN_19 = _GEN_2 | _GEN_4 | _GEN_5;
|
||||
wire _GEN_20 =
|
||||
d_isLui | _GEN_1 | _GEN_2 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_18;
|
||||
assign io_out_pc = io_pc;
|
||||
assign io_out_inst = io_inst;
|
||||
assign io_out_rs1 = io_inst[19:15];
|
||||
@@ -95,11 +111,11 @@ module Decoder(
|
||||
assign io_out_opClass =
|
||||
_GEN_3
|
||||
? 4'h1
|
||||
: _GEN_20
|
||||
: _GEN_19
|
||||
? 4'h2
|
||||
: _GEN_6
|
||||
? 4'h3
|
||||
: _GEN_7 ? 4'h4 : _GEN_15 ? 4'h1 : _GEN_18 ? 4'h5 : _GEN_17 ? 4'h3 : 4'h0;
|
||||
: _GEN_7 ? 4'h4 : _GEN_14 ? 4'h1 : _GEN_17 ? 4'h5 : _GEN_16 ? 4'h3 : 4'h0;
|
||||
assign io_out_aluFn =
|
||||
d_isLui
|
||||
? 5'hF
|
||||
@@ -113,9 +129,9 @@ module Decoder(
|
||||
: _GEN_13[io_inst[14:12]])
|
||||
: 5'h0;
|
||||
assign io_out_memWidth =
|
||||
_GEN_21 | ~_GEN_17 ? {1'h0, _GEN_0[io_inst[14:12]]} : {2'h1, io_inst[14:12] != 3'h2};
|
||||
_GEN_20 | ~_GEN_16 ? {1'h0, _GEN_0[io_inst[14:12]]} : {2'h1, io_inst[14:12] != 3'h2};
|
||||
assign io_out_memSigned = ~(io_inst[14]);
|
||||
assign io_out_isLoad = ~(d_isLui | _GEN_1 | _GEN_20) & (_GEN_6 | ~_GEN_19 & _GEN_17);
|
||||
assign io_out_isLoad = ~(d_isLui | _GEN_1 | _GEN_19) & (_GEN_6 | ~_GEN_18 & _GEN_16);
|
||||
assign io_out_isStore =
|
||||
~(d_isLui | _GEN_1 | _GEN_2 | _GEN_4 | _GEN_5 | _GEN_6) & _GEN_7;
|
||||
assign io_out_isBranch = ~(d_isLui | _GEN_1 | _GEN_2 | _GEN_4) & _GEN_5;
|
||||
@@ -127,11 +143,16 @@ module Decoder(
|
||||
assign io_out_isWord = ~_GEN_10 & (_GEN_8 ? _d_isWord_T : _GEN_12 & _d_isWord_T_1);
|
||||
assign io_out_isSystem =
|
||||
~(d_isLui | _GEN_1 | _GEN_2 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_7 | _GEN_8 | _GEN_12
|
||||
| _GEN_14) & _GEN_16;
|
||||
assign io_out_isFenceI =
|
||||
~(d_isLui | _GEN_1 | _GEN_2 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_7 | _GEN_15) & _GEN_14
|
||||
& _d_isFenceI_T;
|
||||
assign io_out_isAmo = ~_GEN_21 & _GEN_17;
|
||||
| isFenceOpcode) & isSystemOpcode;
|
||||
assign io_out_isFenceI = ~_GEN_15 & isFenceOpcode & _d_isFenceI_T;
|
||||
assign io_out_isEcall = isEcall;
|
||||
assign io_out_isEbreak = isEbreak;
|
||||
assign io_out_isMret = isMret;
|
||||
assign io_out_isSret = isSret;
|
||||
assign io_out_isSfenceVma = isSfenceVma;
|
||||
assign io_out_isXret = isMret | isSret;
|
||||
assign io_out_isWfi = isWfi;
|
||||
assign io_out_isAmo = ~_GEN_20 & _GEN_16;
|
||||
assign io_out_amoOp = io_inst[31:27];
|
||||
assign io_out_writesRd =
|
||||
d_isLui
|
||||
@@ -150,15 +171,20 @@ module Decoder(
|
||||
? (|(io_inst[11:7]))
|
||||
: _GEN_12
|
||||
? (|(io_inst[11:7]))
|
||||
: ~_GEN_14
|
||||
& (_GEN_16
|
||||
: ~isFenceOpcode
|
||||
& (isSystemOpcode
|
||||
? (|(io_inst[11:7])) & (|(io_inst[14:12]))
|
||||
: _GEN_17 & (|(io_inst[11:7])))));
|
||||
: _GEN_16 & (|(io_inst[11:7])))));
|
||||
assign io_out_illegal =
|
||||
io_inst[6:0] != 7'h37 & io_inst[6:0] != 7'h17 & io_inst[6:0] != 7'h6F
|
||||
& io_inst[6:0] != 7'h67 & io_inst[6:0] != 7'h63 & io_inst[6:0] != 7'h3
|
||||
& io_inst[6:0] != 7'h23 & io_inst[6:0] != 7'h13 & io_inst[6:0] != 7'h1B
|
||||
& io_inst[6:0] != 7'h33 & io_inst[6:0] != 7'h3B & io_inst[6:0] != 7'hF
|
||||
& io_inst[6:0] != 7'h73 & io_inst[6:0] != 7'h2F;
|
||||
isSystemOpcode & io_inst == 32'h200073 | io_inst[6:0] != 7'h37 & io_inst[6:0] != 7'h17
|
||||
& io_inst[6:0] != 7'h6F & io_inst[6:0] != 7'h67 & io_inst[6:0] != 7'h63
|
||||
& io_inst[6:0] != 7'h3 & io_inst[6:0] != 7'h23 & io_inst[6:0] != 7'h13
|
||||
& io_inst[6:0] != 7'h1B & io_inst[6:0] != 7'h33 & io_inst[6:0] != 7'h3B
|
||||
& io_inst[6:0] != 7'hF & io_inst[6:0] != 7'h73 & io_inst[6:0] != 7'h2F | ~_GEN_15
|
||||
& (isFenceOpcode
|
||||
? (|(io_inst[14:12])) & io_inst[14:12] != 3'h1
|
||||
: isSystemOpcode & _isSfenceVma_T
|
||||
& ~((isEcall | isEbreak | isMret | isSret | isSfenceVma | isWfi)
|
||||
& io_inst != 32'h200073));
|
||||
endmodule
|
||||
|
||||
|
||||
@@ -5,60 +5,163 @@ module Frontend(
|
||||
io_redirectValid,
|
||||
input [63:0] io_redirectPc,
|
||||
input io_invalidateICache,
|
||||
io_sfenceVma,
|
||||
input [63:0] io_satp,
|
||||
input [1:0] io_currentPriv,
|
||||
output io_imemReqValid,
|
||||
output [63:0] io_imemReqAddr,
|
||||
input io_imemRespValid,
|
||||
input [31:0] io_imemRespBits_0,
|
||||
io_imemRespBits_1,
|
||||
output io_ptwMemReqValid,
|
||||
output [63:0] io_ptwMemReqAddr,
|
||||
input io_ptwMemRespValid,
|
||||
input [63:0] io_ptwMemRespData,
|
||||
input io_outReady,
|
||||
output io_outValid,
|
||||
output [63:0] io_out_pc,
|
||||
output [31:0] io_out_inst_0,
|
||||
io_out_inst_1,
|
||||
output io_out_laneValid_0,
|
||||
io_out_laneValid_1
|
||||
io_out_laneValid_1,
|
||||
io_out_exception,
|
||||
output [63:0] io_out_exceptionCause,
|
||||
io_out_exceptionTval
|
||||
);
|
||||
|
||||
wire _icache_io_respValid;
|
||||
wire [63:0] _icache_io_resp_pc;
|
||||
wire [31:0] _icache_io_resp_inst_0;
|
||||
wire [31:0] _icache_io_resp_inst_1;
|
||||
wire _icache_io_resp_laneValid_0;
|
||||
wire _icache_io_resp_laneValid_1;
|
||||
wire _icache_io_resp_exception;
|
||||
wire [63:0] _icache_io_resp_exceptionCause;
|
||||
wire [63:0] _icache_io_resp_exceptionTval;
|
||||
wire _immu_io_resp_pageFault;
|
||||
wire _immu_io_refill_valid;
|
||||
wire [26:0] _immu_io_refill_vpn;
|
||||
wire [43:0] _immu_io_refill_ppn;
|
||||
wire [1:0] _immu_io_refill_level;
|
||||
wire [7:0] _immu_io_refill_flags;
|
||||
wire _itlb_io_resp_hit;
|
||||
wire _itlb_io_resp_miss;
|
||||
wire [63:0] _itlb_io_resp_paddr;
|
||||
wire _itlb_io_resp_pageFault;
|
||||
reg [63:0] pc;
|
||||
reg faultPending;
|
||||
reg [63:0] faultPc;
|
||||
reg [63:0] faultCause;
|
||||
wire fetchTranslate = (|(io_satp[63:60])) & io_currentPriv != 2'h3;
|
||||
wire itlbMiss = fetchTranslate & _itlb_io_resp_miss;
|
||||
wire instPageFault =
|
||||
fetchTranslate & (_itlb_io_resp_pageFault | _immu_io_resp_pageFault);
|
||||
wire fetchFault = (|(pc[1:0])) | instPageFault;
|
||||
wire translationReady = ~fetchTranslate | _itlb_io_resp_hit | instPageFault;
|
||||
wire [63:0] translatedFetchAddr = fetchTranslate ? _itlb_io_resp_paddr : pc;
|
||||
always @(posedge clock) begin
|
||||
if (reset)
|
||||
automatic logic _GEN;
|
||||
_GEN = fetchFault & ~faultPending;
|
||||
if (reset) begin
|
||||
pc <= 64'h80000000;
|
||||
else if (io_redirectValid)
|
||||
pc <= io_redirectPc;
|
||||
else if (_icache_io_respValid & io_outReady)
|
||||
pc <=
|
||||
_icache_io_resp_pc
|
||||
+ {60'h0,
|
||||
{1'h0, _icache_io_resp_laneValid_0} + {1'h0, _icache_io_resp_laneValid_1},
|
||||
2'h0};
|
||||
faultPending <= 1'h0;
|
||||
end
|
||||
else begin
|
||||
automatic logic _GEN_0;
|
||||
_GEN_0 = faultPending & io_outReady;
|
||||
if (io_redirectValid)
|
||||
pc <= io_redirectPc;
|
||||
else if (~_GEN) begin
|
||||
if (_GEN_0)
|
||||
pc <= pc + 64'h4;
|
||||
else if (_icache_io_respValid & io_outReady)
|
||||
pc <=
|
||||
_icache_io_resp_pc
|
||||
+ {60'h0,
|
||||
{1'h0, _icache_io_resp_laneValid_0} + {1'h0, _icache_io_resp_laneValid_1},
|
||||
2'h0};
|
||||
end
|
||||
faultPending <= ~io_redirectValid & (_GEN | ~_GEN_0 & faultPending);
|
||||
end
|
||||
if (io_redirectValid | ~_GEN) begin
|
||||
end
|
||||
else begin
|
||||
faultPc <= pc;
|
||||
faultCause <= {56'h0, (|(pc[1:0])) ? 8'h0 : 8'hC};
|
||||
end
|
||||
end // always @(posedge)
|
||||
ICache icache (
|
||||
ITLB itlb (
|
||||
.clock (clock),
|
||||
.reset (reset),
|
||||
.io_req_valid (fetchTranslate & ~faultPending),
|
||||
.io_req_vaddr (pc),
|
||||
.io_req_priv (io_currentPriv),
|
||||
.io_resp_hit (_itlb_io_resp_hit),
|
||||
.io_resp_miss (_itlb_io_resp_miss),
|
||||
.io_resp_paddr (_itlb_io_resp_paddr),
|
||||
.io_resp_pageFault (_itlb_io_resp_pageFault),
|
||||
.io_refill_valid (_immu_io_refill_valid),
|
||||
.io_refill_vpn (_immu_io_refill_vpn),
|
||||
.io_refill_ppn (_immu_io_refill_ppn),
|
||||
.io_refill_level (_immu_io_refill_level),
|
||||
.io_refill_flags (_immu_io_refill_flags),
|
||||
.io_flush (io_redirectValid | io_invalidateICache | io_sfenceVma)
|
||||
);
|
||||
MMU immu (
|
||||
.clock (clock),
|
||||
.reset (reset),
|
||||
.io_reqAddr (pc),
|
||||
.io_reqPc (pc),
|
||||
.io_flush (io_redirectValid),
|
||||
.io_invalidate (io_invalidateICache),
|
||||
.io_respReady (io_outReady),
|
||||
.io_memReqValid (io_imemReqValid),
|
||||
.io_memReqAddr (io_imemReqAddr),
|
||||
.io_memRespValid (io_imemRespValid),
|
||||
.io_memRespBits_0 (io_imemRespBits_0),
|
||||
.io_memRespBits_1 (io_imemRespBits_1),
|
||||
.io_respValid (_icache_io_respValid),
|
||||
.io_resp_pc (_icache_io_resp_pc),
|
||||
.io_resp_inst_0 (io_out_inst_0),
|
||||
.io_resp_inst_1 (io_out_inst_1),
|
||||
.io_resp_laneValid_0 (_icache_io_resp_laneValid_0),
|
||||
.io_resp_laneValid_1 (_icache_io_resp_laneValid_1)
|
||||
.io_satp (io_satp),
|
||||
.io_req_valid (itlbMiss),
|
||||
.io_req_vaddr (pc),
|
||||
.io_req_isStore (1'h0),
|
||||
.io_req_isFetch (1'h1),
|
||||
.io_req_priv (io_currentPriv),
|
||||
.io_req_sum (1'h0),
|
||||
.io_req_mxr (1'h0),
|
||||
.io_resp_pageFault (_immu_io_resp_pageFault),
|
||||
.io_ptwMemReq_valid (io_ptwMemReqValid),
|
||||
.io_ptwMemReq_addr (io_ptwMemReqAddr),
|
||||
.io_ptwMemResp_valid (io_ptwMemRespValid),
|
||||
.io_ptwMemResp_data (io_ptwMemRespData),
|
||||
.io_refill_valid (_immu_io_refill_valid),
|
||||
.io_refill_vpn (_immu_io_refill_vpn),
|
||||
.io_refill_ppn (_immu_io_refill_ppn),
|
||||
.io_refill_level (_immu_io_refill_level),
|
||||
.io_refill_flags (_immu_io_refill_flags)
|
||||
);
|
||||
assign io_outValid = _icache_io_respValid;
|
||||
assign io_out_pc = _icache_io_resp_pc;
|
||||
assign io_out_laneValid_0 = _icache_io_resp_laneValid_0;
|
||||
assign io_out_laneValid_1 = _icache_io_resp_laneValid_1;
|
||||
ICache icache (
|
||||
.clock (clock),
|
||||
.reset (reset),
|
||||
.io_reqValid (~fetchFault & ~faultPending & translationReady),
|
||||
.io_reqAddr (translatedFetchAddr),
|
||||
.io_reqPc (pc),
|
||||
.io_flush (io_redirectValid),
|
||||
.io_invalidate (io_invalidateICache),
|
||||
.io_respReady (io_outReady),
|
||||
.io_memReqValid (io_imemReqValid),
|
||||
.io_memReqAddr (io_imemReqAddr),
|
||||
.io_memRespValid (io_imemRespValid),
|
||||
.io_memRespBits_0 (io_imemRespBits_0),
|
||||
.io_memRespBits_1 (io_imemRespBits_1),
|
||||
.io_respValid (_icache_io_respValid),
|
||||
.io_resp_pc (_icache_io_resp_pc),
|
||||
.io_resp_inst_0 (_icache_io_resp_inst_0),
|
||||
.io_resp_inst_1 (_icache_io_resp_inst_1),
|
||||
.io_resp_laneValid_0 (_icache_io_resp_laneValid_0),
|
||||
.io_resp_laneValid_1 (_icache_io_resp_laneValid_1),
|
||||
.io_resp_exception (_icache_io_resp_exception),
|
||||
.io_resp_exceptionCause (_icache_io_resp_exceptionCause),
|
||||
.io_resp_exceptionTval (_icache_io_resp_exceptionTval)
|
||||
);
|
||||
assign io_outValid = faultPending | _icache_io_respValid;
|
||||
assign io_out_pc = faultPending ? faultPc : _icache_io_resp_pc;
|
||||
assign io_out_inst_0 = faultPending ? 32'h0 : _icache_io_resp_inst_0;
|
||||
assign io_out_inst_1 = faultPending ? 32'h0 : _icache_io_resp_inst_1;
|
||||
assign io_out_laneValid_0 = faultPending | _icache_io_resp_laneValid_0;
|
||||
assign io_out_laneValid_1 = ~faultPending & _icache_io_resp_laneValid_1;
|
||||
assign io_out_exception = faultPending | _icache_io_resp_exception;
|
||||
assign io_out_exceptionCause =
|
||||
faultPending ? faultCause : _icache_io_resp_exceptionCause;
|
||||
assign io_out_exceptionTval = faultPending ? faultPc : _icache_io_resp_exceptionTval;
|
||||
endmodule
|
||||
|
||||
|
||||
@@ -2,6 +2,7 @@
|
||||
module ICache(
|
||||
input clock,
|
||||
reset,
|
||||
io_reqValid,
|
||||
input [63:0] io_reqAddr,
|
||||
io_reqPc,
|
||||
input io_flush,
|
||||
@@ -17,7 +18,10 @@ module ICache(
|
||||
output [31:0] io_resp_inst_0,
|
||||
io_resp_inst_1,
|
||||
output io_resp_laneValid_0,
|
||||
io_resp_laneValid_1
|
||||
io_resp_laneValid_1,
|
||||
io_resp_exception,
|
||||
output [63:0] io_resp_exceptionCause,
|
||||
io_resp_exceptionTval
|
||||
);
|
||||
|
||||
wire [31:0] dataWrite_3_1;
|
||||
@@ -9295,8 +9299,9 @@ module ICache(
|
||||
reg [31:0] respReg_inst_1;
|
||||
reg respReg_laneValid_0;
|
||||
reg respReg_laneValid_1;
|
||||
reg respReg_exception;
|
||||
wire _readFire_T = state == 2'h0;
|
||||
wire readFire = _readFire_T & ~io_flush;
|
||||
wire readFire = _readFire_T & io_reqValid & ~io_flush;
|
||||
wire tagHitVec_0 =
|
||||
(|{lookupValidRow_0_1, lookupValidRow_0_0})
|
||||
& _tags_ext_R0_data[50:0] == lookupAddr[63:13];
|
||||
@@ -38132,7 +38137,7 @@ module ICache(
|
||||
{{_GEN_18 ? _GEN_2082 : state},
|
||||
{io_respReady ? 2'h0 : state},
|
||||
{(|_hitWay_T) ? _GEN_2082 : 2'h3},
|
||||
{2'h1}};
|
||||
{io_reqValid ? 2'h1 : state}};
|
||||
state <= _GEN_2083[state];
|
||||
end
|
||||
missReqSent <=
|
||||
@@ -38143,7 +38148,7 @@ module ICache(
|
||||
? (|_hitWay_T) & missReqSent
|
||||
: ~_io_resp_T & (&state) & ~missReqSent | missReqSent);
|
||||
end
|
||||
if (_GEN_16 | ~_readFire_T) begin
|
||||
if (_GEN_16 | ~(_readFire_T & io_reqValid)) begin
|
||||
end
|
||||
else begin
|
||||
automatic logic [1023:0] _GEN_2084 =
|
||||
@@ -47420,8 +47425,12 @@ module ICache(
|
||||
missValidRow_3_1 <= lookupValidRow_3_1;
|
||||
end
|
||||
if (~_GEN_17) begin
|
||||
automatic logic _GEN_2093;
|
||||
automatic logic _GEN_2094;
|
||||
_GEN_2093 = ~(|_hitWay_T) | io_respReady;
|
||||
_GEN_2094 = _io_resp_T | ~_GEN_18 | io_respReady;
|
||||
if (_io_miss_T) begin
|
||||
if (~(|_hitWay_T) | io_respReady) begin
|
||||
if (_GEN_2093) begin
|
||||
end
|
||||
else begin
|
||||
respReg_pc <= lookupPc;
|
||||
@@ -47430,7 +47439,7 @@ module ICache(
|
||||
respReg_laneValid_1 <= lookupLane1Valid;
|
||||
end
|
||||
end
|
||||
else if (_io_resp_T | ~_GEN_18 | io_respReady) begin
|
||||
else if (_GEN_2094) begin
|
||||
end
|
||||
else begin
|
||||
respReg_pc <= missPc;
|
||||
@@ -47442,6 +47451,8 @@ module ICache(
|
||||
_io_miss_T
|
||||
? (|_hitWay_T) & ~io_respReady | respReg_laneValid_0
|
||||
: ~_io_resp_T & _GEN_18 & ~io_respReady | respReg_laneValid_0;
|
||||
respReg_exception <=
|
||||
_io_miss_T ? _GEN_2093 & respReg_exception : _GEN_2094 & respReg_exception;
|
||||
end
|
||||
end // always @(posedge)
|
||||
tags_1024x204 tags_ext (
|
||||
@@ -47487,5 +47498,8 @@ module ICache(
|
||||
assign io_resp_laneValid_0 = ~_io_resp_T | respReg_laneValid_0;
|
||||
assign io_resp_laneValid_1 =
|
||||
_io_resp_T ? respReg_laneValid_1 : _io_resp_T_2 ? ~missInst : lookupLane1Valid;
|
||||
assign io_resp_exception = _io_resp_T & respReg_exception;
|
||||
assign io_resp_exceptionCause = 64'h0;
|
||||
assign io_resp_exceptionTval = 64'h0;
|
||||
endmodule
|
||||
|
||||
|
||||
@@ -6,6 +6,9 @@ module IDStage(
|
||||
io_in_inst_1,
|
||||
input io_in_laneValid_0,
|
||||
io_in_laneValid_1,
|
||||
io_in_exception,
|
||||
input [63:0] io_in_exceptionCause,
|
||||
io_in_exceptionTval,
|
||||
output io_outValid_0,
|
||||
io_outValid_1,
|
||||
output [63:0] io_out_0_pc,
|
||||
@@ -34,11 +37,21 @@ module IDStage(
|
||||
io_out_0_isWord,
|
||||
io_out_0_isSystem,
|
||||
io_out_0_isFenceI,
|
||||
io_out_0_isEcall,
|
||||
io_out_0_isEbreak,
|
||||
io_out_0_isMret,
|
||||
io_out_0_isSret,
|
||||
io_out_0_isSfenceVma,
|
||||
io_out_0_isXret,
|
||||
io_out_0_isWfi,
|
||||
io_out_0_isAmo,
|
||||
output [4:0] io_out_0_amoOp,
|
||||
output io_out_0_writesRd,
|
||||
io_out_0_illegal,
|
||||
output [63:0] io_out_1_pc,
|
||||
io_out_0_fetchException,
|
||||
output [63:0] io_out_0_fetchExceptionCause,
|
||||
io_out_0_fetchExceptionTval,
|
||||
io_out_1_pc,
|
||||
output [31:0] io_out_1_inst,
|
||||
output [4:0] io_out_1_rs1,
|
||||
io_out_1_rs2,
|
||||
@@ -64,81 +77,111 @@ module IDStage(
|
||||
io_out_1_isWord,
|
||||
io_out_1_isSystem,
|
||||
io_out_1_isFenceI,
|
||||
io_out_1_isEcall,
|
||||
io_out_1_isEbreak,
|
||||
io_out_1_isMret,
|
||||
io_out_1_isSret,
|
||||
io_out_1_isSfenceVma,
|
||||
io_out_1_isXret,
|
||||
io_out_1_isWfi,
|
||||
io_out_1_isAmo,
|
||||
output [4:0] io_out_1_amoOp,
|
||||
output io_out_1_writesRd,
|
||||
io_out_1_illegal
|
||||
io_out_1_illegal,
|
||||
io_out_1_fetchException,
|
||||
output [63:0] io_out_1_fetchExceptionCause,
|
||||
io_out_1_fetchExceptionTval
|
||||
);
|
||||
|
||||
Decoder decoders_0 (
|
||||
.io_pc (io_in_pc),
|
||||
.io_inst (io_in_inst_0),
|
||||
.io_out_pc (io_out_0_pc),
|
||||
.io_out_inst (io_out_0_inst),
|
||||
.io_out_rs1 (io_out_0_rs1),
|
||||
.io_out_rs2 (io_out_0_rs2),
|
||||
.io_out_rd (io_out_0_rd),
|
||||
.io_out_funct3 (io_out_0_funct3),
|
||||
.io_out_immI (io_out_0_immI),
|
||||
.io_out_immS (io_out_0_immS),
|
||||
.io_out_immB (io_out_0_immB),
|
||||
.io_out_immU (io_out_0_immU),
|
||||
.io_out_immJ (io_out_0_immJ),
|
||||
.io_out_opClass (io_out_0_opClass),
|
||||
.io_out_aluFn (io_out_0_aluFn),
|
||||
.io_out_memWidth (io_out_0_memWidth),
|
||||
.io_out_memSigned (io_out_0_memSigned),
|
||||
.io_out_isLoad (io_out_0_isLoad),
|
||||
.io_out_isStore (io_out_0_isStore),
|
||||
.io_out_isBranch (io_out_0_isBranch),
|
||||
.io_out_isJal (io_out_0_isJal),
|
||||
.io_out_isJalr (io_out_0_isJalr),
|
||||
.io_out_isLui (io_out_0_isLui),
|
||||
.io_out_isAuipc (io_out_0_isAuipc),
|
||||
.io_out_isOpImm (io_out_0_isOpImm),
|
||||
.io_out_isWord (io_out_0_isWord),
|
||||
.io_out_isSystem (io_out_0_isSystem),
|
||||
.io_out_isFenceI (io_out_0_isFenceI),
|
||||
.io_out_isAmo (io_out_0_isAmo),
|
||||
.io_out_amoOp (io_out_0_amoOp),
|
||||
.io_out_writesRd (io_out_0_writesRd),
|
||||
.io_out_illegal (io_out_0_illegal)
|
||||
.io_pc (io_in_pc),
|
||||
.io_inst (io_in_inst_0),
|
||||
.io_out_pc (io_out_0_pc),
|
||||
.io_out_inst (io_out_0_inst),
|
||||
.io_out_rs1 (io_out_0_rs1),
|
||||
.io_out_rs2 (io_out_0_rs2),
|
||||
.io_out_rd (io_out_0_rd),
|
||||
.io_out_funct3 (io_out_0_funct3),
|
||||
.io_out_immI (io_out_0_immI),
|
||||
.io_out_immS (io_out_0_immS),
|
||||
.io_out_immB (io_out_0_immB),
|
||||
.io_out_immU (io_out_0_immU),
|
||||
.io_out_immJ (io_out_0_immJ),
|
||||
.io_out_opClass (io_out_0_opClass),
|
||||
.io_out_aluFn (io_out_0_aluFn),
|
||||
.io_out_memWidth (io_out_0_memWidth),
|
||||
.io_out_memSigned (io_out_0_memSigned),
|
||||
.io_out_isLoad (io_out_0_isLoad),
|
||||
.io_out_isStore (io_out_0_isStore),
|
||||
.io_out_isBranch (io_out_0_isBranch),
|
||||
.io_out_isJal (io_out_0_isJal),
|
||||
.io_out_isJalr (io_out_0_isJalr),
|
||||
.io_out_isLui (io_out_0_isLui),
|
||||
.io_out_isAuipc (io_out_0_isAuipc),
|
||||
.io_out_isOpImm (io_out_0_isOpImm),
|
||||
.io_out_isWord (io_out_0_isWord),
|
||||
.io_out_isSystem (io_out_0_isSystem),
|
||||
.io_out_isFenceI (io_out_0_isFenceI),
|
||||
.io_out_isEcall (io_out_0_isEcall),
|
||||
.io_out_isEbreak (io_out_0_isEbreak),
|
||||
.io_out_isMret (io_out_0_isMret),
|
||||
.io_out_isSret (io_out_0_isSret),
|
||||
.io_out_isSfenceVma (io_out_0_isSfenceVma),
|
||||
.io_out_isXret (io_out_0_isXret),
|
||||
.io_out_isWfi (io_out_0_isWfi),
|
||||
.io_out_isAmo (io_out_0_isAmo),
|
||||
.io_out_amoOp (io_out_0_amoOp),
|
||||
.io_out_writesRd (io_out_0_writesRd),
|
||||
.io_out_illegal (io_out_0_illegal)
|
||||
);
|
||||
Decoder decoders_1 (
|
||||
.io_pc (io_in_pc + 64'h4),
|
||||
.io_inst (io_in_inst_1),
|
||||
.io_out_pc (io_out_1_pc),
|
||||
.io_out_inst (io_out_1_inst),
|
||||
.io_out_rs1 (io_out_1_rs1),
|
||||
.io_out_rs2 (io_out_1_rs2),
|
||||
.io_out_rd (io_out_1_rd),
|
||||
.io_out_funct3 (io_out_1_funct3),
|
||||
.io_out_immI (io_out_1_immI),
|
||||
.io_out_immS (io_out_1_immS),
|
||||
.io_out_immB (io_out_1_immB),
|
||||
.io_out_immU (io_out_1_immU),
|
||||
.io_out_immJ (io_out_1_immJ),
|
||||
.io_out_opClass (io_out_1_opClass),
|
||||
.io_out_aluFn (io_out_1_aluFn),
|
||||
.io_out_memWidth (io_out_1_memWidth),
|
||||
.io_out_memSigned (io_out_1_memSigned),
|
||||
.io_out_isLoad (io_out_1_isLoad),
|
||||
.io_out_isStore (io_out_1_isStore),
|
||||
.io_out_isBranch (io_out_1_isBranch),
|
||||
.io_out_isJal (io_out_1_isJal),
|
||||
.io_out_isJalr (io_out_1_isJalr),
|
||||
.io_out_isLui (io_out_1_isLui),
|
||||
.io_out_isAuipc (io_out_1_isAuipc),
|
||||
.io_out_isOpImm (io_out_1_isOpImm),
|
||||
.io_out_isWord (io_out_1_isWord),
|
||||
.io_out_isSystem (io_out_1_isSystem),
|
||||
.io_out_isFenceI (io_out_1_isFenceI),
|
||||
.io_out_isAmo (io_out_1_isAmo),
|
||||
.io_out_amoOp (io_out_1_amoOp),
|
||||
.io_out_writesRd (io_out_1_writesRd),
|
||||
.io_out_illegal (io_out_1_illegal)
|
||||
.io_pc (io_in_pc + 64'h4),
|
||||
.io_inst (io_in_inst_1),
|
||||
.io_out_pc (io_out_1_pc),
|
||||
.io_out_inst (io_out_1_inst),
|
||||
.io_out_rs1 (io_out_1_rs1),
|
||||
.io_out_rs2 (io_out_1_rs2),
|
||||
.io_out_rd (io_out_1_rd),
|
||||
.io_out_funct3 (io_out_1_funct3),
|
||||
.io_out_immI (io_out_1_immI),
|
||||
.io_out_immS (io_out_1_immS),
|
||||
.io_out_immB (io_out_1_immB),
|
||||
.io_out_immU (io_out_1_immU),
|
||||
.io_out_immJ (io_out_1_immJ),
|
||||
.io_out_opClass (io_out_1_opClass),
|
||||
.io_out_aluFn (io_out_1_aluFn),
|
||||
.io_out_memWidth (io_out_1_memWidth),
|
||||
.io_out_memSigned (io_out_1_memSigned),
|
||||
.io_out_isLoad (io_out_1_isLoad),
|
||||
.io_out_isStore (io_out_1_isStore),
|
||||
.io_out_isBranch (io_out_1_isBranch),
|
||||
.io_out_isJal (io_out_1_isJal),
|
||||
.io_out_isJalr (io_out_1_isJalr),
|
||||
.io_out_isLui (io_out_1_isLui),
|
||||
.io_out_isAuipc (io_out_1_isAuipc),
|
||||
.io_out_isOpImm (io_out_1_isOpImm),
|
||||
.io_out_isWord (io_out_1_isWord),
|
||||
.io_out_isSystem (io_out_1_isSystem),
|
||||
.io_out_isFenceI (io_out_1_isFenceI),
|
||||
.io_out_isEcall (io_out_1_isEcall),
|
||||
.io_out_isEbreak (io_out_1_isEbreak),
|
||||
.io_out_isMret (io_out_1_isMret),
|
||||
.io_out_isSret (io_out_1_isSret),
|
||||
.io_out_isSfenceVma (io_out_1_isSfenceVma),
|
||||
.io_out_isXret (io_out_1_isXret),
|
||||
.io_out_isWfi (io_out_1_isWfi),
|
||||
.io_out_isAmo (io_out_1_isAmo),
|
||||
.io_out_amoOp (io_out_1_amoOp),
|
||||
.io_out_writesRd (io_out_1_writesRd),
|
||||
.io_out_illegal (io_out_1_illegal)
|
||||
);
|
||||
assign io_outValid_0 = io_inValid & io_in_laneValid_0;
|
||||
assign io_outValid_1 = io_inValid & io_in_laneValid_1;
|
||||
assign io_out_0_fetchException = io_in_exception;
|
||||
assign io_out_0_fetchExceptionCause = io_in_exceptionCause;
|
||||
assign io_out_0_fetchExceptionTval = io_in_exceptionTval;
|
||||
assign io_out_1_fetchException = io_in_exception;
|
||||
assign io_out_1_fetchExceptionCause = io_in_exceptionCause;
|
||||
assign io_out_1_fetchExceptionTval = io_in_exceptionTval;
|
||||
endmodule
|
||||
|
||||
|
||||
1319
generated-ooo/ITLB.sv
Normal file
1319
generated-ooo/ITLB.sv
Normal file
File diff suppressed because it is too large
Load Diff
@@ -28,10 +28,20 @@ module IssueQueue(
|
||||
io_enq_0_decoded_isWord,
|
||||
io_enq_0_decoded_isSystem,
|
||||
io_enq_0_decoded_isFenceI,
|
||||
io_enq_0_decoded_isEcall,
|
||||
io_enq_0_decoded_isEbreak,
|
||||
io_enq_0_decoded_isMret,
|
||||
io_enq_0_decoded_isSret,
|
||||
io_enq_0_decoded_isSfenceVma,
|
||||
io_enq_0_decoded_isXret,
|
||||
io_enq_0_decoded_isWfi,
|
||||
io_enq_0_decoded_isAmo,
|
||||
input [4:0] io_enq_0_decoded_amoOp,
|
||||
input io_enq_0_decoded_writesRd,
|
||||
io_enq_0_decoded_illegal,
|
||||
io_enq_0_decoded_fetchException,
|
||||
input [63:0] io_enq_0_decoded_fetchExceptionCause,
|
||||
io_enq_0_decoded_fetchExceptionTval,
|
||||
input [5:0] io_enq_0_prs1,
|
||||
io_enq_0_prs2,
|
||||
input io_enq_0_src1Ready,
|
||||
@@ -62,10 +72,20 @@ module IssueQueue(
|
||||
io_enq_1_decoded_isWord,
|
||||
io_enq_1_decoded_isSystem,
|
||||
io_enq_1_decoded_isFenceI,
|
||||
io_enq_1_decoded_isEcall,
|
||||
io_enq_1_decoded_isEbreak,
|
||||
io_enq_1_decoded_isMret,
|
||||
io_enq_1_decoded_isSret,
|
||||
io_enq_1_decoded_isSfenceVma,
|
||||
io_enq_1_decoded_isXret,
|
||||
io_enq_1_decoded_isWfi,
|
||||
io_enq_1_decoded_isAmo,
|
||||
input [4:0] io_enq_1_decoded_amoOp,
|
||||
input io_enq_1_decoded_writesRd,
|
||||
io_enq_1_decoded_illegal,
|
||||
io_enq_1_decoded_fetchException,
|
||||
input [63:0] io_enq_1_decoded_fetchExceptionCause,
|
||||
io_enq_1_decoded_fetchExceptionTval,
|
||||
input [5:0] io_enq_1_prs1,
|
||||
io_enq_1_prs2,
|
||||
input io_enq_1_src1Ready,
|
||||
@@ -103,10 +123,20 @@ module IssueQueue(
|
||||
io_issue_0_decoded_isWord,
|
||||
io_issue_0_decoded_isSystem,
|
||||
io_issue_0_decoded_isFenceI,
|
||||
io_issue_0_decoded_isEcall,
|
||||
io_issue_0_decoded_isEbreak,
|
||||
io_issue_0_decoded_isMret,
|
||||
io_issue_0_decoded_isSret,
|
||||
io_issue_0_decoded_isSfenceVma,
|
||||
io_issue_0_decoded_isXret,
|
||||
io_issue_0_decoded_isWfi,
|
||||
io_issue_0_decoded_isAmo,
|
||||
output [4:0] io_issue_0_decoded_amoOp,
|
||||
output io_issue_0_decoded_writesRd,
|
||||
io_issue_0_decoded_illegal,
|
||||
io_issue_0_decoded_fetchException,
|
||||
output [63:0] io_issue_0_decoded_fetchExceptionCause,
|
||||
io_issue_0_decoded_fetchExceptionTval,
|
||||
output [5:0] io_issue_0_prs1,
|
||||
io_issue_0_prs2,
|
||||
io_issue_0_prd,
|
||||
@@ -134,165 +164,219 @@ module IssueQueue(
|
||||
io_issue_1_decoded_isWord,
|
||||
io_issue_1_decoded_isSystem,
|
||||
io_issue_1_decoded_isFenceI,
|
||||
io_issue_1_decoded_isEcall,
|
||||
io_issue_1_decoded_isEbreak,
|
||||
io_issue_1_decoded_isMret,
|
||||
io_issue_1_decoded_isSret,
|
||||
io_issue_1_decoded_isSfenceVma,
|
||||
io_issue_1_decoded_isXret,
|
||||
io_issue_1_decoded_isWfi,
|
||||
io_issue_1_decoded_isAmo,
|
||||
output [4:0] io_issue_1_decoded_amoOp,
|
||||
output io_issue_1_decoded_writesRd,
|
||||
io_issue_1_decoded_illegal,
|
||||
io_issue_1_decoded_fetchException,
|
||||
output [63:0] io_issue_1_decoded_fetchExceptionCause,
|
||||
io_issue_1_decoded_fetchExceptionTval,
|
||||
output [5:0] io_issue_1_prs1,
|
||||
io_issue_1_prs2,
|
||||
io_issue_1_prd,
|
||||
io_issue_1_robIdx,
|
||||
input io_issueReady_0,
|
||||
io_issueReady_1,
|
||||
io_flush
|
||||
io_robHeadValid,
|
||||
input [5:0] io_robHeadIdx,
|
||||
input io_flush
|
||||
);
|
||||
|
||||
ReservationStation intRs (
|
||||
.clock (clock),
|
||||
.reset (reset),
|
||||
.io_enqValid_0 (io_enqValid_0),
|
||||
.io_enqValid_1 (io_enqValid_1),
|
||||
.io_enq_0_decoded_pc (io_enq_0_decoded_pc),
|
||||
.io_enq_0_decoded_inst (io_enq_0_decoded_inst),
|
||||
.io_enq_0_decoded_rs1 (io_enq_0_decoded_rs1),
|
||||
.io_enq_0_decoded_rs2 (io_enq_0_decoded_rs2),
|
||||
.io_enq_0_decoded_funct3 (io_enq_0_decoded_funct3),
|
||||
.io_enq_0_decoded_immI (io_enq_0_decoded_immI),
|
||||
.io_enq_0_decoded_immS (io_enq_0_decoded_immS),
|
||||
.io_enq_0_decoded_immB (io_enq_0_decoded_immB),
|
||||
.io_enq_0_decoded_immU (io_enq_0_decoded_immU),
|
||||
.io_enq_0_decoded_immJ (io_enq_0_decoded_immJ),
|
||||
.io_enq_0_decoded_aluFn (io_enq_0_decoded_aluFn),
|
||||
.io_enq_0_decoded_memWidth (io_enq_0_decoded_memWidth),
|
||||
.io_enq_0_decoded_memSigned (io_enq_0_decoded_memSigned),
|
||||
.io_enq_0_decoded_isLoad (io_enq_0_decoded_isLoad),
|
||||
.io_enq_0_decoded_isStore (io_enq_0_decoded_isStore),
|
||||
.io_enq_0_decoded_isBranch (io_enq_0_decoded_isBranch),
|
||||
.io_enq_0_decoded_isJal (io_enq_0_decoded_isJal),
|
||||
.io_enq_0_decoded_isJalr (io_enq_0_decoded_isJalr),
|
||||
.io_enq_0_decoded_isLui (io_enq_0_decoded_isLui),
|
||||
.io_enq_0_decoded_isAuipc (io_enq_0_decoded_isAuipc),
|
||||
.io_enq_0_decoded_isOpImm (io_enq_0_decoded_isOpImm),
|
||||
.io_enq_0_decoded_isWord (io_enq_0_decoded_isWord),
|
||||
.io_enq_0_decoded_isSystem (io_enq_0_decoded_isSystem),
|
||||
.io_enq_0_decoded_isFenceI (io_enq_0_decoded_isFenceI),
|
||||
.io_enq_0_decoded_isAmo (io_enq_0_decoded_isAmo),
|
||||
.io_enq_0_decoded_amoOp (io_enq_0_decoded_amoOp),
|
||||
.io_enq_0_decoded_writesRd (io_enq_0_decoded_writesRd),
|
||||
.io_enq_0_decoded_illegal (io_enq_0_decoded_illegal),
|
||||
.io_enq_0_prs1 (io_enq_0_prs1),
|
||||
.io_enq_0_prs2 (io_enq_0_prs2),
|
||||
.io_enq_0_src1Ready (io_enq_0_src1Ready),
|
||||
.io_enq_0_src2Ready (io_enq_0_src2Ready),
|
||||
.io_enq_0_prd (io_enq_0_prd),
|
||||
.io_enq_0_robIdx (io_enq_0_robIdx),
|
||||
.io_enq_1_decoded_pc (io_enq_1_decoded_pc),
|
||||
.io_enq_1_decoded_inst (io_enq_1_decoded_inst),
|
||||
.io_enq_1_decoded_rs1 (io_enq_1_decoded_rs1),
|
||||
.io_enq_1_decoded_rs2 (io_enq_1_decoded_rs2),
|
||||
.io_enq_1_decoded_funct3 (io_enq_1_decoded_funct3),
|
||||
.io_enq_1_decoded_immI (io_enq_1_decoded_immI),
|
||||
.io_enq_1_decoded_immS (io_enq_1_decoded_immS),
|
||||
.io_enq_1_decoded_immB (io_enq_1_decoded_immB),
|
||||
.io_enq_1_decoded_immU (io_enq_1_decoded_immU),
|
||||
.io_enq_1_decoded_immJ (io_enq_1_decoded_immJ),
|
||||
.io_enq_1_decoded_aluFn (io_enq_1_decoded_aluFn),
|
||||
.io_enq_1_decoded_memWidth (io_enq_1_decoded_memWidth),
|
||||
.io_enq_1_decoded_memSigned (io_enq_1_decoded_memSigned),
|
||||
.io_enq_1_decoded_isLoad (io_enq_1_decoded_isLoad),
|
||||
.io_enq_1_decoded_isStore (io_enq_1_decoded_isStore),
|
||||
.io_enq_1_decoded_isBranch (io_enq_1_decoded_isBranch),
|
||||
.io_enq_1_decoded_isJal (io_enq_1_decoded_isJal),
|
||||
.io_enq_1_decoded_isJalr (io_enq_1_decoded_isJalr),
|
||||
.io_enq_1_decoded_isLui (io_enq_1_decoded_isLui),
|
||||
.io_enq_1_decoded_isAuipc (io_enq_1_decoded_isAuipc),
|
||||
.io_enq_1_decoded_isOpImm (io_enq_1_decoded_isOpImm),
|
||||
.io_enq_1_decoded_isWord (io_enq_1_decoded_isWord),
|
||||
.io_enq_1_decoded_isSystem (io_enq_1_decoded_isSystem),
|
||||
.io_enq_1_decoded_isFenceI (io_enq_1_decoded_isFenceI),
|
||||
.io_enq_1_decoded_isAmo (io_enq_1_decoded_isAmo),
|
||||
.io_enq_1_decoded_amoOp (io_enq_1_decoded_amoOp),
|
||||
.io_enq_1_decoded_writesRd (io_enq_1_decoded_writesRd),
|
||||
.io_enq_1_decoded_illegal (io_enq_1_decoded_illegal),
|
||||
.io_enq_1_prs1 (io_enq_1_prs1),
|
||||
.io_enq_1_prs2 (io_enq_1_prs2),
|
||||
.io_enq_1_src1Ready (io_enq_1_src1Ready),
|
||||
.io_enq_1_src2Ready (io_enq_1_src2Ready),
|
||||
.io_enq_1_prd (io_enq_1_prd),
|
||||
.io_enq_1_robIdx (io_enq_1_robIdx),
|
||||
.io_enqReady_0 (io_enqReady_0),
|
||||
.io_enqReady_1 (io_enqReady_1),
|
||||
.io_wakeup_0_valid (io_wakeup_0_valid),
|
||||
.io_wakeup_0_phys (io_wakeup_0_phys),
|
||||
.io_wakeup_1_valid (io_wakeup_1_valid),
|
||||
.io_wakeup_1_phys (io_wakeup_1_phys),
|
||||
.io_issueValid_0 (io_issueValid_0),
|
||||
.io_issueValid_1 (io_issueValid_1),
|
||||
.io_issue_0_decoded_pc (io_issue_0_decoded_pc),
|
||||
.io_issue_0_decoded_inst (io_issue_0_decoded_inst),
|
||||
.io_issue_0_decoded_rs1 (io_issue_0_decoded_rs1),
|
||||
.io_issue_0_decoded_funct3 (io_issue_0_decoded_funct3),
|
||||
.io_issue_0_decoded_immI (io_issue_0_decoded_immI),
|
||||
.io_issue_0_decoded_immS (io_issue_0_decoded_immS),
|
||||
.io_issue_0_decoded_immB (io_issue_0_decoded_immB),
|
||||
.io_issue_0_decoded_immU (io_issue_0_decoded_immU),
|
||||
.io_issue_0_decoded_immJ (io_issue_0_decoded_immJ),
|
||||
.io_issue_0_decoded_aluFn (io_issue_0_decoded_aluFn),
|
||||
.io_issue_0_decoded_memWidth (io_issue_0_decoded_memWidth),
|
||||
.io_issue_0_decoded_memSigned (io_issue_0_decoded_memSigned),
|
||||
.io_issue_0_decoded_isLoad (io_issue_0_decoded_isLoad),
|
||||
.io_issue_0_decoded_isStore (io_issue_0_decoded_isStore),
|
||||
.io_issue_0_decoded_isBranch (io_issue_0_decoded_isBranch),
|
||||
.io_issue_0_decoded_isJal (io_issue_0_decoded_isJal),
|
||||
.io_issue_0_decoded_isJalr (io_issue_0_decoded_isJalr),
|
||||
.io_issue_0_decoded_isLui (io_issue_0_decoded_isLui),
|
||||
.io_issue_0_decoded_isAuipc (io_issue_0_decoded_isAuipc),
|
||||
.io_issue_0_decoded_isOpImm (io_issue_0_decoded_isOpImm),
|
||||
.io_issue_0_decoded_isWord (io_issue_0_decoded_isWord),
|
||||
.io_issue_0_decoded_isSystem (io_issue_0_decoded_isSystem),
|
||||
.io_issue_0_decoded_isFenceI (io_issue_0_decoded_isFenceI),
|
||||
.io_issue_0_decoded_isAmo (io_issue_0_decoded_isAmo),
|
||||
.io_issue_0_decoded_amoOp (io_issue_0_decoded_amoOp),
|
||||
.io_issue_0_decoded_writesRd (io_issue_0_decoded_writesRd),
|
||||
.io_issue_0_decoded_illegal (io_issue_0_decoded_illegal),
|
||||
.io_issue_0_prs1 (io_issue_0_prs1),
|
||||
.io_issue_0_prs2 (io_issue_0_prs2),
|
||||
.io_issue_0_prd (io_issue_0_prd),
|
||||
.io_issue_0_robIdx (io_issue_0_robIdx),
|
||||
.io_issue_1_decoded_pc (io_issue_1_decoded_pc),
|
||||
.io_issue_1_decoded_inst (io_issue_1_decoded_inst),
|
||||
.io_issue_1_decoded_rs1 (io_issue_1_decoded_rs1),
|
||||
.io_issue_1_decoded_funct3 (io_issue_1_decoded_funct3),
|
||||
.io_issue_1_decoded_immI (io_issue_1_decoded_immI),
|
||||
.io_issue_1_decoded_immS (io_issue_1_decoded_immS),
|
||||
.io_issue_1_decoded_immB (io_issue_1_decoded_immB),
|
||||
.io_issue_1_decoded_immU (io_issue_1_decoded_immU),
|
||||
.io_issue_1_decoded_immJ (io_issue_1_decoded_immJ),
|
||||
.io_issue_1_decoded_aluFn (io_issue_1_decoded_aluFn),
|
||||
.io_issue_1_decoded_memWidth (io_issue_1_decoded_memWidth),
|
||||
.io_issue_1_decoded_memSigned (io_issue_1_decoded_memSigned),
|
||||
.io_issue_1_decoded_isLoad (io_issue_1_decoded_isLoad),
|
||||
.io_issue_1_decoded_isStore (io_issue_1_decoded_isStore),
|
||||
.io_issue_1_decoded_isBranch (io_issue_1_decoded_isBranch),
|
||||
.io_issue_1_decoded_isJal (io_issue_1_decoded_isJal),
|
||||
.io_issue_1_decoded_isJalr (io_issue_1_decoded_isJalr),
|
||||
.io_issue_1_decoded_isLui (io_issue_1_decoded_isLui),
|
||||
.io_issue_1_decoded_isAuipc (io_issue_1_decoded_isAuipc),
|
||||
.io_issue_1_decoded_isOpImm (io_issue_1_decoded_isOpImm),
|
||||
.io_issue_1_decoded_isWord (io_issue_1_decoded_isWord),
|
||||
.io_issue_1_decoded_isSystem (io_issue_1_decoded_isSystem),
|
||||
.io_issue_1_decoded_isFenceI (io_issue_1_decoded_isFenceI),
|
||||
.io_issue_1_decoded_isAmo (io_issue_1_decoded_isAmo),
|
||||
.io_issue_1_decoded_amoOp (io_issue_1_decoded_amoOp),
|
||||
.io_issue_1_decoded_writesRd (io_issue_1_decoded_writesRd),
|
||||
.io_issue_1_decoded_illegal (io_issue_1_decoded_illegal),
|
||||
.io_issue_1_prs1 (io_issue_1_prs1),
|
||||
.io_issue_1_prs2 (io_issue_1_prs2),
|
||||
.io_issue_1_prd (io_issue_1_prd),
|
||||
.io_issue_1_robIdx (io_issue_1_robIdx),
|
||||
.io_issueReady_0 (io_issueReady_0),
|
||||
.io_issueReady_1 (io_issueReady_1),
|
||||
.io_flush (io_flush)
|
||||
.clock (clock),
|
||||
.reset (reset),
|
||||
.io_enqValid_0 (io_enqValid_0),
|
||||
.io_enqValid_1 (io_enqValid_1),
|
||||
.io_enq_0_decoded_pc (io_enq_0_decoded_pc),
|
||||
.io_enq_0_decoded_inst (io_enq_0_decoded_inst),
|
||||
.io_enq_0_decoded_rs1 (io_enq_0_decoded_rs1),
|
||||
.io_enq_0_decoded_rs2 (io_enq_0_decoded_rs2),
|
||||
.io_enq_0_decoded_funct3 (io_enq_0_decoded_funct3),
|
||||
.io_enq_0_decoded_immI (io_enq_0_decoded_immI),
|
||||
.io_enq_0_decoded_immS (io_enq_0_decoded_immS),
|
||||
.io_enq_0_decoded_immB (io_enq_0_decoded_immB),
|
||||
.io_enq_0_decoded_immU (io_enq_0_decoded_immU),
|
||||
.io_enq_0_decoded_immJ (io_enq_0_decoded_immJ),
|
||||
.io_enq_0_decoded_aluFn (io_enq_0_decoded_aluFn),
|
||||
.io_enq_0_decoded_memWidth (io_enq_0_decoded_memWidth),
|
||||
.io_enq_0_decoded_memSigned (io_enq_0_decoded_memSigned),
|
||||
.io_enq_0_decoded_isLoad (io_enq_0_decoded_isLoad),
|
||||
.io_enq_0_decoded_isStore (io_enq_0_decoded_isStore),
|
||||
.io_enq_0_decoded_isBranch (io_enq_0_decoded_isBranch),
|
||||
.io_enq_0_decoded_isJal (io_enq_0_decoded_isJal),
|
||||
.io_enq_0_decoded_isJalr (io_enq_0_decoded_isJalr),
|
||||
.io_enq_0_decoded_isLui (io_enq_0_decoded_isLui),
|
||||
.io_enq_0_decoded_isAuipc (io_enq_0_decoded_isAuipc),
|
||||
.io_enq_0_decoded_isOpImm (io_enq_0_decoded_isOpImm),
|
||||
.io_enq_0_decoded_isWord (io_enq_0_decoded_isWord),
|
||||
.io_enq_0_decoded_isSystem (io_enq_0_decoded_isSystem),
|
||||
.io_enq_0_decoded_isFenceI (io_enq_0_decoded_isFenceI),
|
||||
.io_enq_0_decoded_isEcall (io_enq_0_decoded_isEcall),
|
||||
.io_enq_0_decoded_isEbreak (io_enq_0_decoded_isEbreak),
|
||||
.io_enq_0_decoded_isMret (io_enq_0_decoded_isMret),
|
||||
.io_enq_0_decoded_isSret (io_enq_0_decoded_isSret),
|
||||
.io_enq_0_decoded_isSfenceVma (io_enq_0_decoded_isSfenceVma),
|
||||
.io_enq_0_decoded_isXret (io_enq_0_decoded_isXret),
|
||||
.io_enq_0_decoded_isWfi (io_enq_0_decoded_isWfi),
|
||||
.io_enq_0_decoded_isAmo (io_enq_0_decoded_isAmo),
|
||||
.io_enq_0_decoded_amoOp (io_enq_0_decoded_amoOp),
|
||||
.io_enq_0_decoded_writesRd (io_enq_0_decoded_writesRd),
|
||||
.io_enq_0_decoded_illegal (io_enq_0_decoded_illegal),
|
||||
.io_enq_0_decoded_fetchException (io_enq_0_decoded_fetchException),
|
||||
.io_enq_0_decoded_fetchExceptionCause (io_enq_0_decoded_fetchExceptionCause),
|
||||
.io_enq_0_decoded_fetchExceptionTval (io_enq_0_decoded_fetchExceptionTval),
|
||||
.io_enq_0_prs1 (io_enq_0_prs1),
|
||||
.io_enq_0_prs2 (io_enq_0_prs2),
|
||||
.io_enq_0_src1Ready (io_enq_0_src1Ready),
|
||||
.io_enq_0_src2Ready (io_enq_0_src2Ready),
|
||||
.io_enq_0_prd (io_enq_0_prd),
|
||||
.io_enq_0_robIdx (io_enq_0_robIdx),
|
||||
.io_enq_1_decoded_pc (io_enq_1_decoded_pc),
|
||||
.io_enq_1_decoded_inst (io_enq_1_decoded_inst),
|
||||
.io_enq_1_decoded_rs1 (io_enq_1_decoded_rs1),
|
||||
.io_enq_1_decoded_rs2 (io_enq_1_decoded_rs2),
|
||||
.io_enq_1_decoded_funct3 (io_enq_1_decoded_funct3),
|
||||
.io_enq_1_decoded_immI (io_enq_1_decoded_immI),
|
||||
.io_enq_1_decoded_immS (io_enq_1_decoded_immS),
|
||||
.io_enq_1_decoded_immB (io_enq_1_decoded_immB),
|
||||
.io_enq_1_decoded_immU (io_enq_1_decoded_immU),
|
||||
.io_enq_1_decoded_immJ (io_enq_1_decoded_immJ),
|
||||
.io_enq_1_decoded_aluFn (io_enq_1_decoded_aluFn),
|
||||
.io_enq_1_decoded_memWidth (io_enq_1_decoded_memWidth),
|
||||
.io_enq_1_decoded_memSigned (io_enq_1_decoded_memSigned),
|
||||
.io_enq_1_decoded_isLoad (io_enq_1_decoded_isLoad),
|
||||
.io_enq_1_decoded_isStore (io_enq_1_decoded_isStore),
|
||||
.io_enq_1_decoded_isBranch (io_enq_1_decoded_isBranch),
|
||||
.io_enq_1_decoded_isJal (io_enq_1_decoded_isJal),
|
||||
.io_enq_1_decoded_isJalr (io_enq_1_decoded_isJalr),
|
||||
.io_enq_1_decoded_isLui (io_enq_1_decoded_isLui),
|
||||
.io_enq_1_decoded_isAuipc (io_enq_1_decoded_isAuipc),
|
||||
.io_enq_1_decoded_isOpImm (io_enq_1_decoded_isOpImm),
|
||||
.io_enq_1_decoded_isWord (io_enq_1_decoded_isWord),
|
||||
.io_enq_1_decoded_isSystem (io_enq_1_decoded_isSystem),
|
||||
.io_enq_1_decoded_isFenceI (io_enq_1_decoded_isFenceI),
|
||||
.io_enq_1_decoded_isEcall (io_enq_1_decoded_isEcall),
|
||||
.io_enq_1_decoded_isEbreak (io_enq_1_decoded_isEbreak),
|
||||
.io_enq_1_decoded_isMret (io_enq_1_decoded_isMret),
|
||||
.io_enq_1_decoded_isSret (io_enq_1_decoded_isSret),
|
||||
.io_enq_1_decoded_isSfenceVma (io_enq_1_decoded_isSfenceVma),
|
||||
.io_enq_1_decoded_isXret (io_enq_1_decoded_isXret),
|
||||
.io_enq_1_decoded_isWfi (io_enq_1_decoded_isWfi),
|
||||
.io_enq_1_decoded_isAmo (io_enq_1_decoded_isAmo),
|
||||
.io_enq_1_decoded_amoOp (io_enq_1_decoded_amoOp),
|
||||
.io_enq_1_decoded_writesRd (io_enq_1_decoded_writesRd),
|
||||
.io_enq_1_decoded_illegal (io_enq_1_decoded_illegal),
|
||||
.io_enq_1_decoded_fetchException (io_enq_1_decoded_fetchException),
|
||||
.io_enq_1_decoded_fetchExceptionCause (io_enq_1_decoded_fetchExceptionCause),
|
||||
.io_enq_1_decoded_fetchExceptionTval (io_enq_1_decoded_fetchExceptionTval),
|
||||
.io_enq_1_prs1 (io_enq_1_prs1),
|
||||
.io_enq_1_prs2 (io_enq_1_prs2),
|
||||
.io_enq_1_src1Ready (io_enq_1_src1Ready),
|
||||
.io_enq_1_src2Ready (io_enq_1_src2Ready),
|
||||
.io_enq_1_prd (io_enq_1_prd),
|
||||
.io_enq_1_robIdx (io_enq_1_robIdx),
|
||||
.io_enqReady_0 (io_enqReady_0),
|
||||
.io_enqReady_1 (io_enqReady_1),
|
||||
.io_wakeup_0_valid (io_wakeup_0_valid),
|
||||
.io_wakeup_0_phys (io_wakeup_0_phys),
|
||||
.io_wakeup_1_valid (io_wakeup_1_valid),
|
||||
.io_wakeup_1_phys (io_wakeup_1_phys),
|
||||
.io_issueValid_0 (io_issueValid_0),
|
||||
.io_issueValid_1 (io_issueValid_1),
|
||||
.io_issue_0_decoded_pc (io_issue_0_decoded_pc),
|
||||
.io_issue_0_decoded_inst (io_issue_0_decoded_inst),
|
||||
.io_issue_0_decoded_rs1 (io_issue_0_decoded_rs1),
|
||||
.io_issue_0_decoded_funct3 (io_issue_0_decoded_funct3),
|
||||
.io_issue_0_decoded_immI (io_issue_0_decoded_immI),
|
||||
.io_issue_0_decoded_immS (io_issue_0_decoded_immS),
|
||||
.io_issue_0_decoded_immB (io_issue_0_decoded_immB),
|
||||
.io_issue_0_decoded_immU (io_issue_0_decoded_immU),
|
||||
.io_issue_0_decoded_immJ (io_issue_0_decoded_immJ),
|
||||
.io_issue_0_decoded_aluFn (io_issue_0_decoded_aluFn),
|
||||
.io_issue_0_decoded_memWidth (io_issue_0_decoded_memWidth),
|
||||
.io_issue_0_decoded_memSigned (io_issue_0_decoded_memSigned),
|
||||
.io_issue_0_decoded_isLoad (io_issue_0_decoded_isLoad),
|
||||
.io_issue_0_decoded_isStore (io_issue_0_decoded_isStore),
|
||||
.io_issue_0_decoded_isBranch (io_issue_0_decoded_isBranch),
|
||||
.io_issue_0_decoded_isJal (io_issue_0_decoded_isJal),
|
||||
.io_issue_0_decoded_isJalr (io_issue_0_decoded_isJalr),
|
||||
.io_issue_0_decoded_isLui (io_issue_0_decoded_isLui),
|
||||
.io_issue_0_decoded_isAuipc (io_issue_0_decoded_isAuipc),
|
||||
.io_issue_0_decoded_isOpImm (io_issue_0_decoded_isOpImm),
|
||||
.io_issue_0_decoded_isWord (io_issue_0_decoded_isWord),
|
||||
.io_issue_0_decoded_isSystem (io_issue_0_decoded_isSystem),
|
||||
.io_issue_0_decoded_isFenceI (io_issue_0_decoded_isFenceI),
|
||||
.io_issue_0_decoded_isEcall (io_issue_0_decoded_isEcall),
|
||||
.io_issue_0_decoded_isEbreak (io_issue_0_decoded_isEbreak),
|
||||
.io_issue_0_decoded_isMret (io_issue_0_decoded_isMret),
|
||||
.io_issue_0_decoded_isSret (io_issue_0_decoded_isSret),
|
||||
.io_issue_0_decoded_isSfenceVma (io_issue_0_decoded_isSfenceVma),
|
||||
.io_issue_0_decoded_isXret (io_issue_0_decoded_isXret),
|
||||
.io_issue_0_decoded_isWfi (io_issue_0_decoded_isWfi),
|
||||
.io_issue_0_decoded_isAmo (io_issue_0_decoded_isAmo),
|
||||
.io_issue_0_decoded_amoOp (io_issue_0_decoded_amoOp),
|
||||
.io_issue_0_decoded_writesRd (io_issue_0_decoded_writesRd),
|
||||
.io_issue_0_decoded_illegal (io_issue_0_decoded_illegal),
|
||||
.io_issue_0_decoded_fetchException (io_issue_0_decoded_fetchException),
|
||||
.io_issue_0_decoded_fetchExceptionCause (io_issue_0_decoded_fetchExceptionCause),
|
||||
.io_issue_0_decoded_fetchExceptionTval (io_issue_0_decoded_fetchExceptionTval),
|
||||
.io_issue_0_prs1 (io_issue_0_prs1),
|
||||
.io_issue_0_prs2 (io_issue_0_prs2),
|
||||
.io_issue_0_prd (io_issue_0_prd),
|
||||
.io_issue_0_robIdx (io_issue_0_robIdx),
|
||||
.io_issue_1_decoded_pc (io_issue_1_decoded_pc),
|
||||
.io_issue_1_decoded_inst (io_issue_1_decoded_inst),
|
||||
.io_issue_1_decoded_rs1 (io_issue_1_decoded_rs1),
|
||||
.io_issue_1_decoded_funct3 (io_issue_1_decoded_funct3),
|
||||
.io_issue_1_decoded_immI (io_issue_1_decoded_immI),
|
||||
.io_issue_1_decoded_immS (io_issue_1_decoded_immS),
|
||||
.io_issue_1_decoded_immB (io_issue_1_decoded_immB),
|
||||
.io_issue_1_decoded_immU (io_issue_1_decoded_immU),
|
||||
.io_issue_1_decoded_immJ (io_issue_1_decoded_immJ),
|
||||
.io_issue_1_decoded_aluFn (io_issue_1_decoded_aluFn),
|
||||
.io_issue_1_decoded_memWidth (io_issue_1_decoded_memWidth),
|
||||
.io_issue_1_decoded_memSigned (io_issue_1_decoded_memSigned),
|
||||
.io_issue_1_decoded_isLoad (io_issue_1_decoded_isLoad),
|
||||
.io_issue_1_decoded_isStore (io_issue_1_decoded_isStore),
|
||||
.io_issue_1_decoded_isBranch (io_issue_1_decoded_isBranch),
|
||||
.io_issue_1_decoded_isJal (io_issue_1_decoded_isJal),
|
||||
.io_issue_1_decoded_isJalr (io_issue_1_decoded_isJalr),
|
||||
.io_issue_1_decoded_isLui (io_issue_1_decoded_isLui),
|
||||
.io_issue_1_decoded_isAuipc (io_issue_1_decoded_isAuipc),
|
||||
.io_issue_1_decoded_isOpImm (io_issue_1_decoded_isOpImm),
|
||||
.io_issue_1_decoded_isWord (io_issue_1_decoded_isWord),
|
||||
.io_issue_1_decoded_isSystem (io_issue_1_decoded_isSystem),
|
||||
.io_issue_1_decoded_isFenceI (io_issue_1_decoded_isFenceI),
|
||||
.io_issue_1_decoded_isEcall (io_issue_1_decoded_isEcall),
|
||||
.io_issue_1_decoded_isEbreak (io_issue_1_decoded_isEbreak),
|
||||
.io_issue_1_decoded_isMret (io_issue_1_decoded_isMret),
|
||||
.io_issue_1_decoded_isSret (io_issue_1_decoded_isSret),
|
||||
.io_issue_1_decoded_isSfenceVma (io_issue_1_decoded_isSfenceVma),
|
||||
.io_issue_1_decoded_isXret (io_issue_1_decoded_isXret),
|
||||
.io_issue_1_decoded_isWfi (io_issue_1_decoded_isWfi),
|
||||
.io_issue_1_decoded_isAmo (io_issue_1_decoded_isAmo),
|
||||
.io_issue_1_decoded_amoOp (io_issue_1_decoded_amoOp),
|
||||
.io_issue_1_decoded_writesRd (io_issue_1_decoded_writesRd),
|
||||
.io_issue_1_decoded_illegal (io_issue_1_decoded_illegal),
|
||||
.io_issue_1_decoded_fetchException (io_issue_1_decoded_fetchException),
|
||||
.io_issue_1_decoded_fetchExceptionCause (io_issue_1_decoded_fetchExceptionCause),
|
||||
.io_issue_1_decoded_fetchExceptionTval (io_issue_1_decoded_fetchExceptionTval),
|
||||
.io_issue_1_prs1 (io_issue_1_prs1),
|
||||
.io_issue_1_prs2 (io_issue_1_prs2),
|
||||
.io_issue_1_prd (io_issue_1_prd),
|
||||
.io_issue_1_robIdx (io_issue_1_robIdx),
|
||||
.io_issueReady_0 (io_issueReady_0),
|
||||
.io_issueReady_1 (io_issueReady_1),
|
||||
.io_robHeadValid (io_robHeadValid),
|
||||
.io_robHeadIdx (io_robHeadIdx),
|
||||
.io_flush (io_flush)
|
||||
);
|
||||
endmodule
|
||||
|
||||
|
||||
@@ -28,10 +28,20 @@ module IssueStage(
|
||||
io_in_0_decoded_isWord,
|
||||
io_in_0_decoded_isSystem,
|
||||
io_in_0_decoded_isFenceI,
|
||||
io_in_0_decoded_isEcall,
|
||||
io_in_0_decoded_isEbreak,
|
||||
io_in_0_decoded_isMret,
|
||||
io_in_0_decoded_isSret,
|
||||
io_in_0_decoded_isSfenceVma,
|
||||
io_in_0_decoded_isXret,
|
||||
io_in_0_decoded_isWfi,
|
||||
io_in_0_decoded_isAmo,
|
||||
input [4:0] io_in_0_decoded_amoOp,
|
||||
input io_in_0_decoded_writesRd,
|
||||
io_in_0_decoded_illegal,
|
||||
io_in_0_decoded_fetchException,
|
||||
input [63:0] io_in_0_decoded_fetchExceptionCause,
|
||||
io_in_0_decoded_fetchExceptionTval,
|
||||
input [5:0] io_in_0_prs1,
|
||||
io_in_0_prs2,
|
||||
input io_in_0_src1Ready,
|
||||
@@ -62,10 +72,20 @@ module IssueStage(
|
||||
io_in_1_decoded_isWord,
|
||||
io_in_1_decoded_isSystem,
|
||||
io_in_1_decoded_isFenceI,
|
||||
io_in_1_decoded_isEcall,
|
||||
io_in_1_decoded_isEbreak,
|
||||
io_in_1_decoded_isMret,
|
||||
io_in_1_decoded_isSret,
|
||||
io_in_1_decoded_isSfenceVma,
|
||||
io_in_1_decoded_isXret,
|
||||
io_in_1_decoded_isWfi,
|
||||
io_in_1_decoded_isAmo,
|
||||
input [4:0] io_in_1_decoded_amoOp,
|
||||
input io_in_1_decoded_writesRd,
|
||||
io_in_1_decoded_illegal,
|
||||
io_in_1_decoded_fetchException,
|
||||
input [63:0] io_in_1_decoded_fetchExceptionCause,
|
||||
io_in_1_decoded_fetchExceptionTval,
|
||||
input [5:0] io_in_1_prs1,
|
||||
io_in_1_prs2,
|
||||
input io_in_1_src1Ready,
|
||||
@@ -103,10 +123,20 @@ module IssueStage(
|
||||
io_out_0_decoded_isWord,
|
||||
io_out_0_decoded_isSystem,
|
||||
io_out_0_decoded_isFenceI,
|
||||
io_out_0_decoded_isEcall,
|
||||
io_out_0_decoded_isEbreak,
|
||||
io_out_0_decoded_isMret,
|
||||
io_out_0_decoded_isSret,
|
||||
io_out_0_decoded_isSfenceVma,
|
||||
io_out_0_decoded_isXret,
|
||||
io_out_0_decoded_isWfi,
|
||||
io_out_0_decoded_isAmo,
|
||||
output [4:0] io_out_0_decoded_amoOp,
|
||||
output io_out_0_decoded_writesRd,
|
||||
io_out_0_decoded_illegal,
|
||||
io_out_0_decoded_fetchException,
|
||||
output [63:0] io_out_0_decoded_fetchExceptionCause,
|
||||
io_out_0_decoded_fetchExceptionTval,
|
||||
output [5:0] io_out_0_prs1,
|
||||
io_out_0_prs2,
|
||||
io_out_0_prd,
|
||||
@@ -134,165 +164,219 @@ module IssueStage(
|
||||
io_out_1_decoded_isWord,
|
||||
io_out_1_decoded_isSystem,
|
||||
io_out_1_decoded_isFenceI,
|
||||
io_out_1_decoded_isEcall,
|
||||
io_out_1_decoded_isEbreak,
|
||||
io_out_1_decoded_isMret,
|
||||
io_out_1_decoded_isSret,
|
||||
io_out_1_decoded_isSfenceVma,
|
||||
io_out_1_decoded_isXret,
|
||||
io_out_1_decoded_isWfi,
|
||||
io_out_1_decoded_isAmo,
|
||||
output [4:0] io_out_1_decoded_amoOp,
|
||||
output io_out_1_decoded_writesRd,
|
||||
io_out_1_decoded_illegal,
|
||||
io_out_1_decoded_fetchException,
|
||||
output [63:0] io_out_1_decoded_fetchExceptionCause,
|
||||
io_out_1_decoded_fetchExceptionTval,
|
||||
output [5:0] io_out_1_prs1,
|
||||
io_out_1_prs2,
|
||||
io_out_1_prd,
|
||||
io_out_1_robIdx,
|
||||
input io_outReady_0,
|
||||
io_outReady_1,
|
||||
io_flush
|
||||
io_robHeadValid,
|
||||
input [5:0] io_robHeadIdx,
|
||||
input io_flush
|
||||
);
|
||||
|
||||
IssueQueue queue (
|
||||
.clock (clock),
|
||||
.reset (reset),
|
||||
.io_enqValid_0 (io_inValid_0),
|
||||
.io_enqValid_1 (io_inValid_1),
|
||||
.io_enq_0_decoded_pc (io_in_0_decoded_pc),
|
||||
.io_enq_0_decoded_inst (io_in_0_decoded_inst),
|
||||
.io_enq_0_decoded_rs1 (io_in_0_decoded_rs1),
|
||||
.io_enq_0_decoded_rs2 (io_in_0_decoded_rs2),
|
||||
.io_enq_0_decoded_funct3 (io_in_0_decoded_funct3),
|
||||
.io_enq_0_decoded_immI (io_in_0_decoded_immI),
|
||||
.io_enq_0_decoded_immS (io_in_0_decoded_immS),
|
||||
.io_enq_0_decoded_immB (io_in_0_decoded_immB),
|
||||
.io_enq_0_decoded_immU (io_in_0_decoded_immU),
|
||||
.io_enq_0_decoded_immJ (io_in_0_decoded_immJ),
|
||||
.io_enq_0_decoded_aluFn (io_in_0_decoded_aluFn),
|
||||
.io_enq_0_decoded_memWidth (io_in_0_decoded_memWidth),
|
||||
.io_enq_0_decoded_memSigned (io_in_0_decoded_memSigned),
|
||||
.io_enq_0_decoded_isLoad (io_in_0_decoded_isLoad),
|
||||
.io_enq_0_decoded_isStore (io_in_0_decoded_isStore),
|
||||
.io_enq_0_decoded_isBranch (io_in_0_decoded_isBranch),
|
||||
.io_enq_0_decoded_isJal (io_in_0_decoded_isJal),
|
||||
.io_enq_0_decoded_isJalr (io_in_0_decoded_isJalr),
|
||||
.io_enq_0_decoded_isLui (io_in_0_decoded_isLui),
|
||||
.io_enq_0_decoded_isAuipc (io_in_0_decoded_isAuipc),
|
||||
.io_enq_0_decoded_isOpImm (io_in_0_decoded_isOpImm),
|
||||
.io_enq_0_decoded_isWord (io_in_0_decoded_isWord),
|
||||
.io_enq_0_decoded_isSystem (io_in_0_decoded_isSystem),
|
||||
.io_enq_0_decoded_isFenceI (io_in_0_decoded_isFenceI),
|
||||
.io_enq_0_decoded_isAmo (io_in_0_decoded_isAmo),
|
||||
.io_enq_0_decoded_amoOp (io_in_0_decoded_amoOp),
|
||||
.io_enq_0_decoded_writesRd (io_in_0_decoded_writesRd),
|
||||
.io_enq_0_decoded_illegal (io_in_0_decoded_illegal),
|
||||
.io_enq_0_prs1 (io_in_0_prs1),
|
||||
.io_enq_0_prs2 (io_in_0_prs2),
|
||||
.io_enq_0_src1Ready (io_in_0_src1Ready),
|
||||
.io_enq_0_src2Ready (io_in_0_src2Ready),
|
||||
.io_enq_0_prd (io_in_0_prd),
|
||||
.io_enq_0_robIdx (io_in_0_robIdx),
|
||||
.io_enq_1_decoded_pc (io_in_1_decoded_pc),
|
||||
.io_enq_1_decoded_inst (io_in_1_decoded_inst),
|
||||
.io_enq_1_decoded_rs1 (io_in_1_decoded_rs1),
|
||||
.io_enq_1_decoded_rs2 (io_in_1_decoded_rs2),
|
||||
.io_enq_1_decoded_funct3 (io_in_1_decoded_funct3),
|
||||
.io_enq_1_decoded_immI (io_in_1_decoded_immI),
|
||||
.io_enq_1_decoded_immS (io_in_1_decoded_immS),
|
||||
.io_enq_1_decoded_immB (io_in_1_decoded_immB),
|
||||
.io_enq_1_decoded_immU (io_in_1_decoded_immU),
|
||||
.io_enq_1_decoded_immJ (io_in_1_decoded_immJ),
|
||||
.io_enq_1_decoded_aluFn (io_in_1_decoded_aluFn),
|
||||
.io_enq_1_decoded_memWidth (io_in_1_decoded_memWidth),
|
||||
.io_enq_1_decoded_memSigned (io_in_1_decoded_memSigned),
|
||||
.io_enq_1_decoded_isLoad (io_in_1_decoded_isLoad),
|
||||
.io_enq_1_decoded_isStore (io_in_1_decoded_isStore),
|
||||
.io_enq_1_decoded_isBranch (io_in_1_decoded_isBranch),
|
||||
.io_enq_1_decoded_isJal (io_in_1_decoded_isJal),
|
||||
.io_enq_1_decoded_isJalr (io_in_1_decoded_isJalr),
|
||||
.io_enq_1_decoded_isLui (io_in_1_decoded_isLui),
|
||||
.io_enq_1_decoded_isAuipc (io_in_1_decoded_isAuipc),
|
||||
.io_enq_1_decoded_isOpImm (io_in_1_decoded_isOpImm),
|
||||
.io_enq_1_decoded_isWord (io_in_1_decoded_isWord),
|
||||
.io_enq_1_decoded_isSystem (io_in_1_decoded_isSystem),
|
||||
.io_enq_1_decoded_isFenceI (io_in_1_decoded_isFenceI),
|
||||
.io_enq_1_decoded_isAmo (io_in_1_decoded_isAmo),
|
||||
.io_enq_1_decoded_amoOp (io_in_1_decoded_amoOp),
|
||||
.io_enq_1_decoded_writesRd (io_in_1_decoded_writesRd),
|
||||
.io_enq_1_decoded_illegal (io_in_1_decoded_illegal),
|
||||
.io_enq_1_prs1 (io_in_1_prs1),
|
||||
.io_enq_1_prs2 (io_in_1_prs2),
|
||||
.io_enq_1_src1Ready (io_in_1_src1Ready),
|
||||
.io_enq_1_src2Ready (io_in_1_src2Ready),
|
||||
.io_enq_1_prd (io_in_1_prd),
|
||||
.io_enq_1_robIdx (io_in_1_robIdx),
|
||||
.io_enqReady_0 (io_inReady_0),
|
||||
.io_enqReady_1 (io_inReady_1),
|
||||
.io_wakeup_0_valid (io_wakeup_0_valid),
|
||||
.io_wakeup_0_phys (io_wakeup_0_phys),
|
||||
.io_wakeup_1_valid (io_wakeup_1_valid),
|
||||
.io_wakeup_1_phys (io_wakeup_1_phys),
|
||||
.io_issueValid_0 (io_outValid_0),
|
||||
.io_issueValid_1 (io_outValid_1),
|
||||
.io_issue_0_decoded_pc (io_out_0_decoded_pc),
|
||||
.io_issue_0_decoded_inst (io_out_0_decoded_inst),
|
||||
.io_issue_0_decoded_rs1 (io_out_0_decoded_rs1),
|
||||
.io_issue_0_decoded_funct3 (io_out_0_decoded_funct3),
|
||||
.io_issue_0_decoded_immI (io_out_0_decoded_immI),
|
||||
.io_issue_0_decoded_immS (io_out_0_decoded_immS),
|
||||
.io_issue_0_decoded_immB (io_out_0_decoded_immB),
|
||||
.io_issue_0_decoded_immU (io_out_0_decoded_immU),
|
||||
.io_issue_0_decoded_immJ (io_out_0_decoded_immJ),
|
||||
.io_issue_0_decoded_aluFn (io_out_0_decoded_aluFn),
|
||||
.io_issue_0_decoded_memWidth (io_out_0_decoded_memWidth),
|
||||
.io_issue_0_decoded_memSigned (io_out_0_decoded_memSigned),
|
||||
.io_issue_0_decoded_isLoad (io_out_0_decoded_isLoad),
|
||||
.io_issue_0_decoded_isStore (io_out_0_decoded_isStore),
|
||||
.io_issue_0_decoded_isBranch (io_out_0_decoded_isBranch),
|
||||
.io_issue_0_decoded_isJal (io_out_0_decoded_isJal),
|
||||
.io_issue_0_decoded_isJalr (io_out_0_decoded_isJalr),
|
||||
.io_issue_0_decoded_isLui (io_out_0_decoded_isLui),
|
||||
.io_issue_0_decoded_isAuipc (io_out_0_decoded_isAuipc),
|
||||
.io_issue_0_decoded_isOpImm (io_out_0_decoded_isOpImm),
|
||||
.io_issue_0_decoded_isWord (io_out_0_decoded_isWord),
|
||||
.io_issue_0_decoded_isSystem (io_out_0_decoded_isSystem),
|
||||
.io_issue_0_decoded_isFenceI (io_out_0_decoded_isFenceI),
|
||||
.io_issue_0_decoded_isAmo (io_out_0_decoded_isAmo),
|
||||
.io_issue_0_decoded_amoOp (io_out_0_decoded_amoOp),
|
||||
.io_issue_0_decoded_writesRd (io_out_0_decoded_writesRd),
|
||||
.io_issue_0_decoded_illegal (io_out_0_decoded_illegal),
|
||||
.io_issue_0_prs1 (io_out_0_prs1),
|
||||
.io_issue_0_prs2 (io_out_0_prs2),
|
||||
.io_issue_0_prd (io_out_0_prd),
|
||||
.io_issue_0_robIdx (io_out_0_robIdx),
|
||||
.io_issue_1_decoded_pc (io_out_1_decoded_pc),
|
||||
.io_issue_1_decoded_inst (io_out_1_decoded_inst),
|
||||
.io_issue_1_decoded_rs1 (io_out_1_decoded_rs1),
|
||||
.io_issue_1_decoded_funct3 (io_out_1_decoded_funct3),
|
||||
.io_issue_1_decoded_immI (io_out_1_decoded_immI),
|
||||
.io_issue_1_decoded_immS (io_out_1_decoded_immS),
|
||||
.io_issue_1_decoded_immB (io_out_1_decoded_immB),
|
||||
.io_issue_1_decoded_immU (io_out_1_decoded_immU),
|
||||
.io_issue_1_decoded_immJ (io_out_1_decoded_immJ),
|
||||
.io_issue_1_decoded_aluFn (io_out_1_decoded_aluFn),
|
||||
.io_issue_1_decoded_memWidth (io_out_1_decoded_memWidth),
|
||||
.io_issue_1_decoded_memSigned (io_out_1_decoded_memSigned),
|
||||
.io_issue_1_decoded_isLoad (io_out_1_decoded_isLoad),
|
||||
.io_issue_1_decoded_isStore (io_out_1_decoded_isStore),
|
||||
.io_issue_1_decoded_isBranch (io_out_1_decoded_isBranch),
|
||||
.io_issue_1_decoded_isJal (io_out_1_decoded_isJal),
|
||||
.io_issue_1_decoded_isJalr (io_out_1_decoded_isJalr),
|
||||
.io_issue_1_decoded_isLui (io_out_1_decoded_isLui),
|
||||
.io_issue_1_decoded_isAuipc (io_out_1_decoded_isAuipc),
|
||||
.io_issue_1_decoded_isOpImm (io_out_1_decoded_isOpImm),
|
||||
.io_issue_1_decoded_isWord (io_out_1_decoded_isWord),
|
||||
.io_issue_1_decoded_isSystem (io_out_1_decoded_isSystem),
|
||||
.io_issue_1_decoded_isFenceI (io_out_1_decoded_isFenceI),
|
||||
.io_issue_1_decoded_isAmo (io_out_1_decoded_isAmo),
|
||||
.io_issue_1_decoded_amoOp (io_out_1_decoded_amoOp),
|
||||
.io_issue_1_decoded_writesRd (io_out_1_decoded_writesRd),
|
||||
.io_issue_1_decoded_illegal (io_out_1_decoded_illegal),
|
||||
.io_issue_1_prs1 (io_out_1_prs1),
|
||||
.io_issue_1_prs2 (io_out_1_prs2),
|
||||
.io_issue_1_prd (io_out_1_prd),
|
||||
.io_issue_1_robIdx (io_out_1_robIdx),
|
||||
.io_issueReady_0 (io_outReady_0),
|
||||
.io_issueReady_1 (io_outReady_1),
|
||||
.io_flush (io_flush)
|
||||
.clock (clock),
|
||||
.reset (reset),
|
||||
.io_enqValid_0 (io_inValid_0),
|
||||
.io_enqValid_1 (io_inValid_1),
|
||||
.io_enq_0_decoded_pc (io_in_0_decoded_pc),
|
||||
.io_enq_0_decoded_inst (io_in_0_decoded_inst),
|
||||
.io_enq_0_decoded_rs1 (io_in_0_decoded_rs1),
|
||||
.io_enq_0_decoded_rs2 (io_in_0_decoded_rs2),
|
||||
.io_enq_0_decoded_funct3 (io_in_0_decoded_funct3),
|
||||
.io_enq_0_decoded_immI (io_in_0_decoded_immI),
|
||||
.io_enq_0_decoded_immS (io_in_0_decoded_immS),
|
||||
.io_enq_0_decoded_immB (io_in_0_decoded_immB),
|
||||
.io_enq_0_decoded_immU (io_in_0_decoded_immU),
|
||||
.io_enq_0_decoded_immJ (io_in_0_decoded_immJ),
|
||||
.io_enq_0_decoded_aluFn (io_in_0_decoded_aluFn),
|
||||
.io_enq_0_decoded_memWidth (io_in_0_decoded_memWidth),
|
||||
.io_enq_0_decoded_memSigned (io_in_0_decoded_memSigned),
|
||||
.io_enq_0_decoded_isLoad (io_in_0_decoded_isLoad),
|
||||
.io_enq_0_decoded_isStore (io_in_0_decoded_isStore),
|
||||
.io_enq_0_decoded_isBranch (io_in_0_decoded_isBranch),
|
||||
.io_enq_0_decoded_isJal (io_in_0_decoded_isJal),
|
||||
.io_enq_0_decoded_isJalr (io_in_0_decoded_isJalr),
|
||||
.io_enq_0_decoded_isLui (io_in_0_decoded_isLui),
|
||||
.io_enq_0_decoded_isAuipc (io_in_0_decoded_isAuipc),
|
||||
.io_enq_0_decoded_isOpImm (io_in_0_decoded_isOpImm),
|
||||
.io_enq_0_decoded_isWord (io_in_0_decoded_isWord),
|
||||
.io_enq_0_decoded_isSystem (io_in_0_decoded_isSystem),
|
||||
.io_enq_0_decoded_isFenceI (io_in_0_decoded_isFenceI),
|
||||
.io_enq_0_decoded_isEcall (io_in_0_decoded_isEcall),
|
||||
.io_enq_0_decoded_isEbreak (io_in_0_decoded_isEbreak),
|
||||
.io_enq_0_decoded_isMret (io_in_0_decoded_isMret),
|
||||
.io_enq_0_decoded_isSret (io_in_0_decoded_isSret),
|
||||
.io_enq_0_decoded_isSfenceVma (io_in_0_decoded_isSfenceVma),
|
||||
.io_enq_0_decoded_isXret (io_in_0_decoded_isXret),
|
||||
.io_enq_0_decoded_isWfi (io_in_0_decoded_isWfi),
|
||||
.io_enq_0_decoded_isAmo (io_in_0_decoded_isAmo),
|
||||
.io_enq_0_decoded_amoOp (io_in_0_decoded_amoOp),
|
||||
.io_enq_0_decoded_writesRd (io_in_0_decoded_writesRd),
|
||||
.io_enq_0_decoded_illegal (io_in_0_decoded_illegal),
|
||||
.io_enq_0_decoded_fetchException (io_in_0_decoded_fetchException),
|
||||
.io_enq_0_decoded_fetchExceptionCause (io_in_0_decoded_fetchExceptionCause),
|
||||
.io_enq_0_decoded_fetchExceptionTval (io_in_0_decoded_fetchExceptionTval),
|
||||
.io_enq_0_prs1 (io_in_0_prs1),
|
||||
.io_enq_0_prs2 (io_in_0_prs2),
|
||||
.io_enq_0_src1Ready (io_in_0_src1Ready),
|
||||
.io_enq_0_src2Ready (io_in_0_src2Ready),
|
||||
.io_enq_0_prd (io_in_0_prd),
|
||||
.io_enq_0_robIdx (io_in_0_robIdx),
|
||||
.io_enq_1_decoded_pc (io_in_1_decoded_pc),
|
||||
.io_enq_1_decoded_inst (io_in_1_decoded_inst),
|
||||
.io_enq_1_decoded_rs1 (io_in_1_decoded_rs1),
|
||||
.io_enq_1_decoded_rs2 (io_in_1_decoded_rs2),
|
||||
.io_enq_1_decoded_funct3 (io_in_1_decoded_funct3),
|
||||
.io_enq_1_decoded_immI (io_in_1_decoded_immI),
|
||||
.io_enq_1_decoded_immS (io_in_1_decoded_immS),
|
||||
.io_enq_1_decoded_immB (io_in_1_decoded_immB),
|
||||
.io_enq_1_decoded_immU (io_in_1_decoded_immU),
|
||||
.io_enq_1_decoded_immJ (io_in_1_decoded_immJ),
|
||||
.io_enq_1_decoded_aluFn (io_in_1_decoded_aluFn),
|
||||
.io_enq_1_decoded_memWidth (io_in_1_decoded_memWidth),
|
||||
.io_enq_1_decoded_memSigned (io_in_1_decoded_memSigned),
|
||||
.io_enq_1_decoded_isLoad (io_in_1_decoded_isLoad),
|
||||
.io_enq_1_decoded_isStore (io_in_1_decoded_isStore),
|
||||
.io_enq_1_decoded_isBranch (io_in_1_decoded_isBranch),
|
||||
.io_enq_1_decoded_isJal (io_in_1_decoded_isJal),
|
||||
.io_enq_1_decoded_isJalr (io_in_1_decoded_isJalr),
|
||||
.io_enq_1_decoded_isLui (io_in_1_decoded_isLui),
|
||||
.io_enq_1_decoded_isAuipc (io_in_1_decoded_isAuipc),
|
||||
.io_enq_1_decoded_isOpImm (io_in_1_decoded_isOpImm),
|
||||
.io_enq_1_decoded_isWord (io_in_1_decoded_isWord),
|
||||
.io_enq_1_decoded_isSystem (io_in_1_decoded_isSystem),
|
||||
.io_enq_1_decoded_isFenceI (io_in_1_decoded_isFenceI),
|
||||
.io_enq_1_decoded_isEcall (io_in_1_decoded_isEcall),
|
||||
.io_enq_1_decoded_isEbreak (io_in_1_decoded_isEbreak),
|
||||
.io_enq_1_decoded_isMret (io_in_1_decoded_isMret),
|
||||
.io_enq_1_decoded_isSret (io_in_1_decoded_isSret),
|
||||
.io_enq_1_decoded_isSfenceVma (io_in_1_decoded_isSfenceVma),
|
||||
.io_enq_1_decoded_isXret (io_in_1_decoded_isXret),
|
||||
.io_enq_1_decoded_isWfi (io_in_1_decoded_isWfi),
|
||||
.io_enq_1_decoded_isAmo (io_in_1_decoded_isAmo),
|
||||
.io_enq_1_decoded_amoOp (io_in_1_decoded_amoOp),
|
||||
.io_enq_1_decoded_writesRd (io_in_1_decoded_writesRd),
|
||||
.io_enq_1_decoded_illegal (io_in_1_decoded_illegal),
|
||||
.io_enq_1_decoded_fetchException (io_in_1_decoded_fetchException),
|
||||
.io_enq_1_decoded_fetchExceptionCause (io_in_1_decoded_fetchExceptionCause),
|
||||
.io_enq_1_decoded_fetchExceptionTval (io_in_1_decoded_fetchExceptionTval),
|
||||
.io_enq_1_prs1 (io_in_1_prs1),
|
||||
.io_enq_1_prs2 (io_in_1_prs2),
|
||||
.io_enq_1_src1Ready (io_in_1_src1Ready),
|
||||
.io_enq_1_src2Ready (io_in_1_src2Ready),
|
||||
.io_enq_1_prd (io_in_1_prd),
|
||||
.io_enq_1_robIdx (io_in_1_robIdx),
|
||||
.io_enqReady_0 (io_inReady_0),
|
||||
.io_enqReady_1 (io_inReady_1),
|
||||
.io_wakeup_0_valid (io_wakeup_0_valid),
|
||||
.io_wakeup_0_phys (io_wakeup_0_phys),
|
||||
.io_wakeup_1_valid (io_wakeup_1_valid),
|
||||
.io_wakeup_1_phys (io_wakeup_1_phys),
|
||||
.io_issueValid_0 (io_outValid_0),
|
||||
.io_issueValid_1 (io_outValid_1),
|
||||
.io_issue_0_decoded_pc (io_out_0_decoded_pc),
|
||||
.io_issue_0_decoded_inst (io_out_0_decoded_inst),
|
||||
.io_issue_0_decoded_rs1 (io_out_0_decoded_rs1),
|
||||
.io_issue_0_decoded_funct3 (io_out_0_decoded_funct3),
|
||||
.io_issue_0_decoded_immI (io_out_0_decoded_immI),
|
||||
.io_issue_0_decoded_immS (io_out_0_decoded_immS),
|
||||
.io_issue_0_decoded_immB (io_out_0_decoded_immB),
|
||||
.io_issue_0_decoded_immU (io_out_0_decoded_immU),
|
||||
.io_issue_0_decoded_immJ (io_out_0_decoded_immJ),
|
||||
.io_issue_0_decoded_aluFn (io_out_0_decoded_aluFn),
|
||||
.io_issue_0_decoded_memWidth (io_out_0_decoded_memWidth),
|
||||
.io_issue_0_decoded_memSigned (io_out_0_decoded_memSigned),
|
||||
.io_issue_0_decoded_isLoad (io_out_0_decoded_isLoad),
|
||||
.io_issue_0_decoded_isStore (io_out_0_decoded_isStore),
|
||||
.io_issue_0_decoded_isBranch (io_out_0_decoded_isBranch),
|
||||
.io_issue_0_decoded_isJal (io_out_0_decoded_isJal),
|
||||
.io_issue_0_decoded_isJalr (io_out_0_decoded_isJalr),
|
||||
.io_issue_0_decoded_isLui (io_out_0_decoded_isLui),
|
||||
.io_issue_0_decoded_isAuipc (io_out_0_decoded_isAuipc),
|
||||
.io_issue_0_decoded_isOpImm (io_out_0_decoded_isOpImm),
|
||||
.io_issue_0_decoded_isWord (io_out_0_decoded_isWord),
|
||||
.io_issue_0_decoded_isSystem (io_out_0_decoded_isSystem),
|
||||
.io_issue_0_decoded_isFenceI (io_out_0_decoded_isFenceI),
|
||||
.io_issue_0_decoded_isEcall (io_out_0_decoded_isEcall),
|
||||
.io_issue_0_decoded_isEbreak (io_out_0_decoded_isEbreak),
|
||||
.io_issue_0_decoded_isMret (io_out_0_decoded_isMret),
|
||||
.io_issue_0_decoded_isSret (io_out_0_decoded_isSret),
|
||||
.io_issue_0_decoded_isSfenceVma (io_out_0_decoded_isSfenceVma),
|
||||
.io_issue_0_decoded_isXret (io_out_0_decoded_isXret),
|
||||
.io_issue_0_decoded_isWfi (io_out_0_decoded_isWfi),
|
||||
.io_issue_0_decoded_isAmo (io_out_0_decoded_isAmo),
|
||||
.io_issue_0_decoded_amoOp (io_out_0_decoded_amoOp),
|
||||
.io_issue_0_decoded_writesRd (io_out_0_decoded_writesRd),
|
||||
.io_issue_0_decoded_illegal (io_out_0_decoded_illegal),
|
||||
.io_issue_0_decoded_fetchException (io_out_0_decoded_fetchException),
|
||||
.io_issue_0_decoded_fetchExceptionCause (io_out_0_decoded_fetchExceptionCause),
|
||||
.io_issue_0_decoded_fetchExceptionTval (io_out_0_decoded_fetchExceptionTval),
|
||||
.io_issue_0_prs1 (io_out_0_prs1),
|
||||
.io_issue_0_prs2 (io_out_0_prs2),
|
||||
.io_issue_0_prd (io_out_0_prd),
|
||||
.io_issue_0_robIdx (io_out_0_robIdx),
|
||||
.io_issue_1_decoded_pc (io_out_1_decoded_pc),
|
||||
.io_issue_1_decoded_inst (io_out_1_decoded_inst),
|
||||
.io_issue_1_decoded_rs1 (io_out_1_decoded_rs1),
|
||||
.io_issue_1_decoded_funct3 (io_out_1_decoded_funct3),
|
||||
.io_issue_1_decoded_immI (io_out_1_decoded_immI),
|
||||
.io_issue_1_decoded_immS (io_out_1_decoded_immS),
|
||||
.io_issue_1_decoded_immB (io_out_1_decoded_immB),
|
||||
.io_issue_1_decoded_immU (io_out_1_decoded_immU),
|
||||
.io_issue_1_decoded_immJ (io_out_1_decoded_immJ),
|
||||
.io_issue_1_decoded_aluFn (io_out_1_decoded_aluFn),
|
||||
.io_issue_1_decoded_memWidth (io_out_1_decoded_memWidth),
|
||||
.io_issue_1_decoded_memSigned (io_out_1_decoded_memSigned),
|
||||
.io_issue_1_decoded_isLoad (io_out_1_decoded_isLoad),
|
||||
.io_issue_1_decoded_isStore (io_out_1_decoded_isStore),
|
||||
.io_issue_1_decoded_isBranch (io_out_1_decoded_isBranch),
|
||||
.io_issue_1_decoded_isJal (io_out_1_decoded_isJal),
|
||||
.io_issue_1_decoded_isJalr (io_out_1_decoded_isJalr),
|
||||
.io_issue_1_decoded_isLui (io_out_1_decoded_isLui),
|
||||
.io_issue_1_decoded_isAuipc (io_out_1_decoded_isAuipc),
|
||||
.io_issue_1_decoded_isOpImm (io_out_1_decoded_isOpImm),
|
||||
.io_issue_1_decoded_isWord (io_out_1_decoded_isWord),
|
||||
.io_issue_1_decoded_isSystem (io_out_1_decoded_isSystem),
|
||||
.io_issue_1_decoded_isFenceI (io_out_1_decoded_isFenceI),
|
||||
.io_issue_1_decoded_isEcall (io_out_1_decoded_isEcall),
|
||||
.io_issue_1_decoded_isEbreak (io_out_1_decoded_isEbreak),
|
||||
.io_issue_1_decoded_isMret (io_out_1_decoded_isMret),
|
||||
.io_issue_1_decoded_isSret (io_out_1_decoded_isSret),
|
||||
.io_issue_1_decoded_isSfenceVma (io_out_1_decoded_isSfenceVma),
|
||||
.io_issue_1_decoded_isXret (io_out_1_decoded_isXret),
|
||||
.io_issue_1_decoded_isWfi (io_out_1_decoded_isWfi),
|
||||
.io_issue_1_decoded_isAmo (io_out_1_decoded_isAmo),
|
||||
.io_issue_1_decoded_amoOp (io_out_1_decoded_amoOp),
|
||||
.io_issue_1_decoded_writesRd (io_out_1_decoded_writesRd),
|
||||
.io_issue_1_decoded_illegal (io_out_1_decoded_illegal),
|
||||
.io_issue_1_decoded_fetchException (io_out_1_decoded_fetchException),
|
||||
.io_issue_1_decoded_fetchExceptionCause (io_out_1_decoded_fetchExceptionCause),
|
||||
.io_issue_1_decoded_fetchExceptionTval (io_out_1_decoded_fetchExceptionTval),
|
||||
.io_issue_1_prs1 (io_out_1_prs1),
|
||||
.io_issue_1_prs2 (io_out_1_prs2),
|
||||
.io_issue_1_prd (io_out_1_prd),
|
||||
.io_issue_1_robIdx (io_out_1_robIdx),
|
||||
.io_issueReady_0 (io_outReady_0),
|
||||
.io_issueReady_1 (io_outReady_1),
|
||||
.io_robHeadValid (io_robHeadValid),
|
||||
.io_robHeadIdx (io_robHeadIdx),
|
||||
.io_flush (io_flush)
|
||||
);
|
||||
endmodule
|
||||
|
||||
|
||||
@@ -10,6 +10,10 @@ module LSU(
|
||||
io_req_isAmo,
|
||||
input [4:0] io_req_amoOp,
|
||||
input [2:0] io_req_size,
|
||||
input io_checkOnly,
|
||||
io_sfenceVma,
|
||||
input [1:0] io_currentPriv,
|
||||
input [63:0] io_mstatus,
|
||||
output io_reqReady,
|
||||
input [63:0] io_satp,
|
||||
output io_dmemReqValid,
|
||||
@@ -21,7 +25,10 @@ module LSU(
|
||||
input [63:0] io_dmemRespData,
|
||||
output io_respValid,
|
||||
output [63:0] io_respData,
|
||||
output io_pageFault
|
||||
output io_pageFault,
|
||||
io_misaligned,
|
||||
output [63:0] io_faultCause,
|
||||
io_faultAddr
|
||||
);
|
||||
|
||||
wire _dcache_io_reqReady;
|
||||
@@ -37,26 +44,96 @@ module LSU(
|
||||
wire _mmu_io_refill_valid;
|
||||
wire [26:0] _mmu_io_refill_vpn;
|
||||
wire [43:0] _mmu_io_refill_ppn;
|
||||
wire [1:0] _mmu_io_refill_level;
|
||||
wire [7:0] _mmu_io_refill_flags;
|
||||
wire _dtlb_io_resp_hit;
|
||||
wire _dtlb_io_resp_miss;
|
||||
wire [63:0] _dtlb_io_resp_paddr;
|
||||
wire _dtlb_io_resp_pageFault;
|
||||
wire [1:0] effectivePriv =
|
||||
(&io_currentPriv) & io_mstatus[17] ? io_mstatus[12:11] : io_currentPriv;
|
||||
reg pendingValid;
|
||||
reg [63:0] pendingReq_addr;
|
||||
reg [63:0] pendingReq_data;
|
||||
reg pendingReq_isStore;
|
||||
reg pendingReq_isSigned;
|
||||
reg pendingReq_isAmo;
|
||||
reg [4:0] pendingReq_amoOp;
|
||||
reg [2:0] pendingReq_size;
|
||||
reg pendingCheckOnly;
|
||||
reg [1:0] pendingPriv;
|
||||
reg [63:0] pendingMstatus;
|
||||
reg [63:0] pendingSatp;
|
||||
wire io_reqReady_0 = _dcache_io_reqReady & ~pendingValid;
|
||||
wire acceptCurrent = io_reqValid & io_reqReady_0;
|
||||
wire activeValid = pendingValid | acceptCurrent;
|
||||
wire [2:0] activeReq_size = pendingValid ? pendingReq_size : io_req_size;
|
||||
wire activeReq_isStore = pendingValid ? pendingReq_isStore : io_req_isStore;
|
||||
wire [63:0] io_faultAddr_0 = pendingValid ? pendingReq_addr : io_req_addr;
|
||||
wire activeCheckOnly = pendingValid ? pendingCheckOnly : io_checkOnly;
|
||||
wire [1:0] activePriv = pendingValid ? pendingPriv : effectivePriv;
|
||||
wire [1:0] activeMstatus = pendingValid ? pendingMstatus[19:18] : io_mstatus[19:18];
|
||||
wire [63:0] activeSatp = pendingValid ? pendingSatp : io_satp;
|
||||
wire translate = (|(activeSatp[63:60])) & activePriv != 2'h3;
|
||||
wire dtlb_io_req_valid = activeValid & translate;
|
||||
reg ptwOutstanding;
|
||||
wire ptwReqFire = _mmu_io_ptwMemReq_valid & ~ptwOutstanding;
|
||||
wire ptwRespFire = io_dmemRespValid & (ptwOutstanding | ptwReqFire);
|
||||
wire translationReady = ~translate | _dtlb_io_resp_hit;
|
||||
wire translationFault = _dtlb_io_resp_pageFault | _mmu_io_resp_pageFault;
|
||||
wire misaligned =
|
||||
activeValid
|
||||
& (|((activeReq_size == 3'h3
|
||||
? 3'h0
|
||||
: activeReq_size == 3'h2
|
||||
? 3'h4
|
||||
: activeReq_size == 3'h1 ? 3'h2 : {2'h0, activeReq_size == 3'h0}) - 3'h1
|
||||
& io_faultAddr_0[2:0]));
|
||||
wire newFault = activeValid & (translationFault | misaligned);
|
||||
wire checkOnlyDispatch =
|
||||
activeValid & activeCheckOnly & translationReady & ~translationFault & ~misaligned;
|
||||
wire dcacheDispatch =
|
||||
activeValid & ~activeCheckOnly & translationReady & ~translationFault & ~misaligned
|
||||
& _dcache_io_reqReady;
|
||||
wire storeComplete = dcacheDispatch & activeReq_isStore | checkOnlyDispatch;
|
||||
always @(posedge clock) begin
|
||||
if (reset)
|
||||
automatic logic latchPending;
|
||||
automatic logic clearPending;
|
||||
latchPending = acceptCurrent & ~dcacheDispatch & ~newFault;
|
||||
clearPending = pendingValid & (dcacheDispatch | checkOnlyDispatch | newFault);
|
||||
if (reset) begin
|
||||
pendingValid <= 1'h0;
|
||||
ptwOutstanding <= 1'h0;
|
||||
else
|
||||
ptwOutstanding <=
|
||||
_mmu_io_ptwMemReq_valid | ~(io_dmemRespValid & ptwOutstanding) & ptwOutstanding;
|
||||
end
|
||||
else begin
|
||||
pendingValid <= ~clearPending & (latchPending | pendingValid);
|
||||
ptwOutstanding <= ~ptwRespFire & (ptwReqFire | ptwOutstanding);
|
||||
end
|
||||
if (clearPending | ~latchPending) begin
|
||||
end
|
||||
else begin
|
||||
pendingReq_addr <= io_req_addr;
|
||||
pendingReq_data <= io_req_data;
|
||||
pendingReq_isStore <= io_req_isStore;
|
||||
pendingReq_isSigned <= io_req_isSigned;
|
||||
pendingReq_isAmo <= io_req_isAmo;
|
||||
pendingReq_amoOp <= io_req_amoOp;
|
||||
pendingReq_size <= io_req_size;
|
||||
pendingCheckOnly <= io_checkOnly;
|
||||
pendingPriv <= effectivePriv;
|
||||
pendingMstatus <= io_mstatus;
|
||||
pendingSatp <= io_satp;
|
||||
end
|
||||
end // always @(posedge)
|
||||
DTLB dtlb (
|
||||
.clock (clock),
|
||||
.reset (reset),
|
||||
.io_req_valid (io_reqValid & (|(io_satp[63:60]))),
|
||||
.io_req_vaddr (io_req_addr),
|
||||
.io_req_isStore (io_req_isStore),
|
||||
.io_req_valid (dtlb_io_req_valid),
|
||||
.io_req_vaddr (io_faultAddr_0),
|
||||
.io_req_isStore (activeReq_isStore),
|
||||
.io_req_priv (activePriv),
|
||||
.io_req_sum (activeMstatus[0]),
|
||||
.io_req_mxr (activeMstatus[1]),
|
||||
.io_resp_hit (_dtlb_io_resp_hit),
|
||||
.io_resp_miss (_dtlb_io_resp_miss),
|
||||
.io_resp_paddr (_dtlb_io_resp_paddr),
|
||||
@@ -64,56 +141,68 @@ module LSU(
|
||||
.io_refill_valid (_mmu_io_refill_valid),
|
||||
.io_refill_vpn (_mmu_io_refill_vpn),
|
||||
.io_refill_ppn (_mmu_io_refill_ppn),
|
||||
.io_refill_flags (_mmu_io_refill_flags)
|
||||
.io_refill_level (_mmu_io_refill_level),
|
||||
.io_refill_flags (_mmu_io_refill_flags),
|
||||
.io_flush (io_sfenceVma)
|
||||
);
|
||||
MMU mmu (
|
||||
.clock (clock),
|
||||
.reset (reset),
|
||||
.io_satp (io_satp),
|
||||
.io_req_valid (io_reqValid & (|(io_satp[63:60])) & _dtlb_io_resp_miss),
|
||||
.io_req_vaddr (io_req_addr),
|
||||
.io_req_isStore (io_req_isStore),
|
||||
.io_satp (activeSatp),
|
||||
.io_req_valid (dtlb_io_req_valid & _dtlb_io_resp_miss),
|
||||
.io_req_vaddr (io_faultAddr_0),
|
||||
.io_req_isStore (activeReq_isStore),
|
||||
.io_req_isFetch (1'h0),
|
||||
.io_req_priv (activePriv),
|
||||
.io_req_sum (activeMstatus[0]),
|
||||
.io_req_mxr (activeMstatus[1]),
|
||||
.io_resp_pageFault (_mmu_io_resp_pageFault),
|
||||
.io_ptwMemReq_valid (_mmu_io_ptwMemReq_valid),
|
||||
.io_ptwMemReq_addr (_mmu_io_ptwMemReq_addr),
|
||||
.io_ptwMemResp_valid (io_dmemRespValid & ptwOutstanding),
|
||||
.io_ptwMemResp_valid (ptwRespFire),
|
||||
.io_ptwMemResp_data (io_dmemRespData),
|
||||
.io_refill_valid (_mmu_io_refill_valid),
|
||||
.io_refill_vpn (_mmu_io_refill_vpn),
|
||||
.io_refill_ppn (_mmu_io_refill_ppn),
|
||||
.io_refill_level (_mmu_io_refill_level),
|
||||
.io_refill_flags (_mmu_io_refill_flags)
|
||||
);
|
||||
DCache dcache (
|
||||
.clock (clock),
|
||||
.reset (reset),
|
||||
.io_reqValid
|
||||
(io_reqValid & (~(|(io_satp[63:60])) | _dtlb_io_resp_hit) & ~translationFault),
|
||||
.io_req_addr ((|(io_satp[63:60])) ? _dtlb_io_resp_paddr : io_req_addr),
|
||||
.io_req_data (io_req_data),
|
||||
.io_req_isStore (io_req_isStore),
|
||||
.io_req_isSigned (io_req_isSigned),
|
||||
.io_req_isAmo (io_req_isAmo),
|
||||
.io_req_amoOp (io_req_amoOp),
|
||||
.io_req_size (io_req_size),
|
||||
.io_reqValid (dcacheDispatch),
|
||||
.io_req_addr (translate ? _dtlb_io_resp_paddr : io_faultAddr_0),
|
||||
.io_req_data (pendingValid ? pendingReq_data : io_req_data),
|
||||
.io_req_isStore (activeReq_isStore),
|
||||
.io_req_isSigned (pendingValid ? pendingReq_isSigned : io_req_isSigned),
|
||||
.io_req_isAmo (pendingValid ? pendingReq_isAmo : io_req_isAmo),
|
||||
.io_req_amoOp (pendingValid ? pendingReq_amoOp : io_req_amoOp),
|
||||
.io_req_size (activeReq_size),
|
||||
.io_reqReady (_dcache_io_reqReady),
|
||||
.io_memReqValid (_dcache_io_memReqValid),
|
||||
.io_memReq_addr (_dcache_io_memReq_addr),
|
||||
.io_memReq_data (_dcache_io_memReq_data),
|
||||
.io_memReq_isStore (_dcache_io_memReq_isStore),
|
||||
.io_memReq_size (_dcache_io_memReq_size),
|
||||
.io_memRespValid (io_dmemRespValid & ~ptwOutstanding),
|
||||
.io_memRespValid (io_dmemRespValid & ~ptwOutstanding & ~ptwReqFire),
|
||||
.io_memRespData (io_dmemRespData),
|
||||
.io_respValid (_dcache_io_respValid),
|
||||
.io_respData (io_respData)
|
||||
);
|
||||
assign io_reqReady = _dcache_io_reqReady & ~ptwOutstanding;
|
||||
assign io_dmemReqValid = _mmu_io_ptwMemReq_valid | _dcache_io_memReqValid;
|
||||
assign io_dmemReq_addr =
|
||||
_mmu_io_ptwMemReq_valid ? _mmu_io_ptwMemReq_addr : _dcache_io_memReq_addr;
|
||||
assign io_dmemReq_data = _mmu_io_ptwMemReq_valid ? 64'h0 : _dcache_io_memReq_data;
|
||||
assign io_dmemReq_isStore = ~_mmu_io_ptwMemReq_valid & _dcache_io_memReq_isStore;
|
||||
assign io_dmemReq_size = _mmu_io_ptwMemReq_valid ? 3'h3 : _dcache_io_memReq_size;
|
||||
assign io_respValid = _dcache_io_respValid | translationFault;
|
||||
assign io_reqReady = io_reqReady_0;
|
||||
assign io_dmemReqValid = ptwReqFire | _dcache_io_memReqValid;
|
||||
assign io_dmemReq_addr = ptwReqFire ? _mmu_io_ptwMemReq_addr : _dcache_io_memReq_addr;
|
||||
assign io_dmemReq_data = ptwReqFire ? 64'h0 : _dcache_io_memReq_data;
|
||||
assign io_dmemReq_isStore = ~ptwReqFire & _dcache_io_memReq_isStore;
|
||||
assign io_dmemReq_size = ptwReqFire ? 3'h3 : _dcache_io_memReq_size;
|
||||
assign io_respValid = _dcache_io_respValid | newFault | storeComplete;
|
||||
assign io_pageFault = translationFault;
|
||||
assign io_misaligned = misaligned;
|
||||
assign io_faultCause =
|
||||
{56'h0,
|
||||
misaligned
|
||||
? {6'h1, activeReq_isStore, 1'h0}
|
||||
: {4'h0, translationFault, 1'h1, activeReq_isStore, 1'h1}};
|
||||
assign io_faultAddr = io_faultAddr_0;
|
||||
endmodule
|
||||
|
||||
|
||||
@@ -6,6 +6,10 @@ module MMU(
|
||||
input io_req_valid,
|
||||
input [63:0] io_req_vaddr,
|
||||
input io_req_isStore,
|
||||
io_req_isFetch,
|
||||
input [1:0] io_req_priv,
|
||||
input io_req_sum,
|
||||
io_req_mxr,
|
||||
output io_resp_pageFault,
|
||||
io_ptwMemReq_valid,
|
||||
output [63:0] io_ptwMemReq_addr,
|
||||
@@ -14,6 +18,7 @@ module MMU(
|
||||
output io_refill_valid,
|
||||
output [26:0] io_refill_vpn,
|
||||
output [43:0] io_refill_ppn,
|
||||
output [1:0] io_refill_level,
|
||||
output [7:0] io_refill_flags
|
||||
);
|
||||
|
||||
@@ -25,6 +30,10 @@ module MMU(
|
||||
.io_reqValid (io_req_valid & (|(io_satp[63:60]))),
|
||||
.io_reqVpn (io_req_vaddr[38:12]),
|
||||
.io_isStore (io_req_isStore),
|
||||
.io_isFetch (io_req_isFetch),
|
||||
.io_priv (io_req_priv),
|
||||
.io_sum (io_req_sum),
|
||||
.io_mxr (io_req_mxr),
|
||||
.io_satp (io_satp),
|
||||
.io_memReq_valid (io_ptwMemReq_valid),
|
||||
.io_memReq_addr (io_ptwMemReq_addr),
|
||||
@@ -34,6 +43,7 @@ module MMU(
|
||||
.io_refill_valid (io_refill_valid),
|
||||
.io_refill_vpn (io_refill_vpn),
|
||||
.io_refill_ppn (io_refill_ppn),
|
||||
.io_refill_level (io_refill_level),
|
||||
.io_refill_flags (io_refill_flags),
|
||||
.io_pageFault (_walker_io_pageFault)
|
||||
);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -5,6 +5,10 @@ module PageTableWalker(
|
||||
io_reqValid,
|
||||
input [26:0] io_reqVpn,
|
||||
input io_isStore,
|
||||
io_isFetch,
|
||||
input [1:0] io_priv,
|
||||
input io_sum,
|
||||
io_mxr,
|
||||
input [63:0] io_satp,
|
||||
output io_memReq_valid,
|
||||
output [63:0] io_memReq_addr,
|
||||
@@ -14,6 +18,7 @@ module PageTableWalker(
|
||||
io_refill_valid,
|
||||
output [26:0] io_refill_vpn,
|
||||
output [43:0] io_refill_ppn,
|
||||
output [1:0] io_refill_level,
|
||||
output [7:0] io_refill_flags,
|
||||
output io_pageFault
|
||||
);
|
||||
@@ -21,20 +26,28 @@ module PageTableWalker(
|
||||
reg [2:0] state;
|
||||
reg [26:0] vpnReg;
|
||||
reg isStoreReg;
|
||||
reg walkFault;
|
||||
reg [43:0] nextPpn;
|
||||
reg isFetchReg;
|
||||
reg [1:0] privReg;
|
||||
reg sumReg;
|
||||
reg mxrReg;
|
||||
wire _io_memReq_addr_T = state == 3'h1;
|
||||
wire _io_memReq_addr_T_1 = state == 3'h2;
|
||||
reg walkFault;
|
||||
reg [43:0] nextPpn;
|
||||
reg [7:0] leafFlagsReg;
|
||||
reg [1:0] leafLevelReg;
|
||||
reg [43:0] curPpn;
|
||||
wire _io_memReq_valid_T_3 = state == 3'h3;
|
||||
wire io_respValid_0 = state == 3'h4;
|
||||
always @(posedge clock) begin
|
||||
automatic logic pteIsLeaf;
|
||||
automatic logic invalidPte;
|
||||
automatic logic _GEN;
|
||||
automatic logic _GEN_0;
|
||||
automatic logic _GEN_1;
|
||||
automatic logic _GEN_2;
|
||||
automatic logic [1:0] level;
|
||||
automatic logic pteIsLeaf;
|
||||
automatic logic invalidPte;
|
||||
automatic logic _GEN;
|
||||
automatic logic _GEN_0;
|
||||
automatic logic _GEN_1;
|
||||
automatic logic _GEN_2;
|
||||
level = _io_memReq_addr_T ? 2'h2 : {1'h0, _io_memReq_addr_T_1};
|
||||
pteIsLeaf = io_memResp_data[1] | io_memResp_data[3];
|
||||
invalidPte = ~(io_memResp_data[0]) | ~(io_memResp_data[1]) & io_memResp_data[2];
|
||||
_GEN = state == 3'h0;
|
||||
@@ -60,25 +73,36 @@ module PageTableWalker(
|
||||
& (_GEN_1
|
||||
? invalidPte
|
||||
| (pteIsLeaf
|
||||
? (isStoreReg
|
||||
? ~(io_memResp_data[2]) | ~(io_memResp_data[7])
|
||||
: ~(io_memResp_data[1])) | ~(io_memResp_data[6]) | walkFault
|
||||
? privReg == 2'h1 & io_memResp_data[4] & (isFetchReg | ~sumReg)
|
||||
| privReg == 2'h0 & ~(io_memResp_data[4])
|
||||
| ~(isFetchReg
|
||||
? io_memResp_data[3]
|
||||
: isStoreReg
|
||||
? io_memResp_data[2] & io_memResp_data[7]
|
||||
: io_memResp_data[1] | mxrReg & io_memResp_data[3])
|
||||
| ~(io_memResp_data[6]) | level == 2'h2
|
||||
& (|(io_memResp_data[27:10])) | level == 2'h1
|
||||
& (|(io_memResp_data[18:10])) | walkFault
|
||||
: ~_GEN_0 | walkFault)
|
||||
: walkFault);
|
||||
end
|
||||
if (_GEN & io_reqValid) begin
|
||||
vpnReg <= io_reqVpn;
|
||||
isStoreReg <= io_isStore;
|
||||
isFetchReg <= io_isFetch;
|
||||
privReg <= io_priv;
|
||||
sumReg <= io_sum;
|
||||
mxrReg <= io_mxr;
|
||||
end
|
||||
if (_GEN | ~_GEN_1 | invalidPte | ~pteIsLeaf) begin
|
||||
end
|
||||
else begin
|
||||
automatic logic [1:0] level =
|
||||
_io_memReq_addr_T ? 2'h2 : {1'h0, _io_memReq_addr_T_1};
|
||||
nextPpn <=
|
||||
{io_memResp_data[53:28],
|
||||
level[1] ? vpnReg[17:9] : io_memResp_data[27:19],
|
||||
level == 2'h0 ? io_memResp_data[18:10] : vpnReg[8:0]};
|
||||
leafFlagsReg <= io_memResp_data[7:0];
|
||||
leafLevelReg <= level;
|
||||
end
|
||||
if (_GEN | ~_GEN_1 | _GEN_2) begin
|
||||
end
|
||||
@@ -96,7 +120,8 @@ module PageTableWalker(
|
||||
assign io_refill_valid = io_respValid_0 & ~walkFault;
|
||||
assign io_refill_vpn = vpnReg;
|
||||
assign io_refill_ppn = nextPpn;
|
||||
assign io_refill_flags = io_memResp_data[7:0];
|
||||
assign io_refill_level = leafLevelReg;
|
||||
assign io_refill_flags = leafFlagsReg;
|
||||
assign io_pageFault = walkFault;
|
||||
endmodule
|
||||
|
||||
|
||||
19
generated-ooo/PrivilegeControl.sv
Normal file
19
generated-ooo/PrivilegeControl.sv
Normal file
@@ -0,0 +1,19 @@
|
||||
// Generated by CIRCT firtool-1.139.0
|
||||
module PrivilegeControl(
|
||||
input clock,
|
||||
reset,
|
||||
input [1:0] io_nextPriv,
|
||||
input io_setPriv,
|
||||
output [1:0] io_priv
|
||||
);
|
||||
|
||||
reg [1:0] privReg;
|
||||
always @(posedge clock) begin
|
||||
if (reset)
|
||||
privReg <= 2'h3;
|
||||
else if (io_setPriv)
|
||||
privReg <= io_nextPriv;
|
||||
end // always @(posedge)
|
||||
assign io_priv = privReg;
|
||||
endmodule
|
||||
|
||||
8023
generated-ooo/ROB.sv
8023
generated-ooo/ROB.sv
File diff suppressed because it is too large
Load Diff
@@ -30,11 +30,21 @@ module RenameStage(
|
||||
io_in_0_isWord,
|
||||
io_in_0_isSystem,
|
||||
io_in_0_isFenceI,
|
||||
io_in_0_isEcall,
|
||||
io_in_0_isEbreak,
|
||||
io_in_0_isMret,
|
||||
io_in_0_isSret,
|
||||
io_in_0_isSfenceVma,
|
||||
io_in_0_isXret,
|
||||
io_in_0_isWfi,
|
||||
io_in_0_isAmo,
|
||||
input [4:0] io_in_0_amoOp,
|
||||
input io_in_0_writesRd,
|
||||
io_in_0_illegal,
|
||||
input [63:0] io_in_1_pc,
|
||||
io_in_0_fetchException,
|
||||
input [63:0] io_in_0_fetchExceptionCause,
|
||||
io_in_0_fetchExceptionTval,
|
||||
io_in_1_pc,
|
||||
input [31:0] io_in_1_inst,
|
||||
input [4:0] io_in_1_rs1,
|
||||
io_in_1_rs2,
|
||||
@@ -60,10 +70,20 @@ module RenameStage(
|
||||
io_in_1_isWord,
|
||||
io_in_1_isSystem,
|
||||
io_in_1_isFenceI,
|
||||
io_in_1_isEcall,
|
||||
io_in_1_isEbreak,
|
||||
io_in_1_isMret,
|
||||
io_in_1_isSret,
|
||||
io_in_1_isSfenceVma,
|
||||
io_in_1_isXret,
|
||||
io_in_1_isWfi,
|
||||
io_in_1_isAmo,
|
||||
input [4:0] io_in_1_amoOp,
|
||||
input io_in_1_writesRd,
|
||||
io_in_1_illegal,
|
||||
io_in_1_fetchException,
|
||||
input [63:0] io_in_1_fetchExceptionCause,
|
||||
io_in_1_fetchExceptionTval,
|
||||
output io_outValid_0,
|
||||
io_outValid_1,
|
||||
output [63:0] io_out_0_decoded_pc,
|
||||
@@ -90,10 +110,20 @@ module RenameStage(
|
||||
io_out_0_decoded_isWord,
|
||||
io_out_0_decoded_isSystem,
|
||||
io_out_0_decoded_isFenceI,
|
||||
io_out_0_decoded_isEcall,
|
||||
io_out_0_decoded_isEbreak,
|
||||
io_out_0_decoded_isMret,
|
||||
io_out_0_decoded_isSret,
|
||||
io_out_0_decoded_isSfenceVma,
|
||||
io_out_0_decoded_isXret,
|
||||
io_out_0_decoded_isWfi,
|
||||
io_out_0_decoded_isAmo,
|
||||
output [4:0] io_out_0_decoded_amoOp,
|
||||
output io_out_0_decoded_writesRd,
|
||||
io_out_0_decoded_illegal,
|
||||
io_out_0_decoded_fetchException,
|
||||
output [63:0] io_out_0_decoded_fetchExceptionCause,
|
||||
io_out_0_decoded_fetchExceptionTval,
|
||||
output [5:0] io_out_0_prs1,
|
||||
io_out_0_prs2,
|
||||
output io_out_0_src1Ready,
|
||||
@@ -124,10 +154,20 @@ module RenameStage(
|
||||
io_out_1_decoded_isWord,
|
||||
io_out_1_decoded_isSystem,
|
||||
io_out_1_decoded_isFenceI,
|
||||
io_out_1_decoded_isEcall,
|
||||
io_out_1_decoded_isEbreak,
|
||||
io_out_1_decoded_isMret,
|
||||
io_out_1_decoded_isSret,
|
||||
io_out_1_decoded_isSfenceVma,
|
||||
io_out_1_decoded_isXret,
|
||||
io_out_1_decoded_isWfi,
|
||||
io_out_1_decoded_isAmo,
|
||||
output [4:0] io_out_1_decoded_amoOp,
|
||||
output io_out_1_decoded_writesRd,
|
||||
io_out_1_decoded_illegal,
|
||||
io_out_1_decoded_fetchException,
|
||||
output [63:0] io_out_1_decoded_fetchExceptionCause,
|
||||
io_out_1_decoded_fetchExceptionTval,
|
||||
output [5:0] io_out_1_prs1,
|
||||
io_out_1_prs2,
|
||||
output io_out_1_src1Ready,
|
||||
@@ -163,11 +203,21 @@ module RenameStage(
|
||||
io_completeCsrRs1_1,
|
||||
input [4:0] io_completeCsrZimm_0,
|
||||
io_completeCsrZimm_1,
|
||||
input io_commitReady_0,
|
||||
input io_completeFenceI_0,
|
||||
io_completeFenceI_1,
|
||||
io_completeSfenceVma_0,
|
||||
io_completeSfenceVma_1,
|
||||
io_completeXret_0,
|
||||
io_completeXret_1,
|
||||
io_completeXretIsMret_0,
|
||||
io_completeXretIsMret_1,
|
||||
io_commitReady_0,
|
||||
io_commitReady_1,
|
||||
output io_commitValid_0,
|
||||
io_commitValid_1,
|
||||
io_commitEntry_0_valid,
|
||||
output [5:0] io_commitEntry_0_robIdx,
|
||||
output [63:0] io_commitEntry_0_pc,
|
||||
output [4:0] io_commitEntry_0_archDest,
|
||||
output io_commitEntry_0_writesDest,
|
||||
output [3:0] io_commitEntry_0_opClass,
|
||||
@@ -184,7 +234,11 @@ module RenameStage(
|
||||
output [63:0] io_commitEntry_0_csrRs1,
|
||||
output [4:0] io_commitEntry_0_csrZimm,
|
||||
output io_commitEntry_0_fenceI,
|
||||
io_commitEntry_0_sfenceVma,
|
||||
io_commitEntry_0_xret,
|
||||
io_commitEntry_0_xretIsMret,
|
||||
output [5:0] io_commitEntry_1_robIdx,
|
||||
output [63:0] io_commitEntry_1_pc,
|
||||
output [4:0] io_commitEntry_1_archDest,
|
||||
output io_commitEntry_1_writesDest,
|
||||
output [3:0] io_commitEntry_1_opClass,
|
||||
@@ -201,6 +255,9 @@ module RenameStage(
|
||||
output [63:0] io_commitEntry_1_csrRs1,
|
||||
output [4:0] io_commitEntry_1_csrZimm,
|
||||
output io_commitEntry_1_fenceI,
|
||||
io_commitEntry_1_sfenceVma,
|
||||
io_commitEntry_1_xret,
|
||||
io_commitEntry_1_xretIsMret,
|
||||
input io_commitMapValid_0,
|
||||
io_commitMapValid_1,
|
||||
input [4:0] io_commitArch_0,
|
||||
@@ -893,18 +950,26 @@ module RenameStage(
|
||||
.reset (reset),
|
||||
.io_allocateValid_0 (e_valid),
|
||||
.io_allocateValid_1 (e_1_valid),
|
||||
.io_allocateEntry_0_pc (io_in_0_pc),
|
||||
.io_allocateEntry_0_archDest (io_in_0_rd),
|
||||
.io_allocateEntry_0_writesDest (io_in_0_writesRd),
|
||||
.io_allocateEntry_0_opClass (io_in_0_opClass),
|
||||
.io_allocateEntry_0_dest (e_dest),
|
||||
.io_allocateEntry_0_oldDest (_table_io_oldPrd_0),
|
||||
.io_allocateEntry_0_fenceI (io_in_0_isFenceI),
|
||||
.io_allocateEntry_0_sfenceVma (io_in_0_isSfenceVma),
|
||||
.io_allocateEntry_0_xret (io_in_0_isXret),
|
||||
.io_allocateEntry_0_xretIsMret (io_in_0_isMret),
|
||||
.io_allocateEntry_1_pc (io_in_1_pc),
|
||||
.io_allocateEntry_1_archDest (io_in_1_rd),
|
||||
.io_allocateEntry_1_writesDest (io_in_1_writesRd),
|
||||
.io_allocateEntry_1_opClass (io_in_1_opClass),
|
||||
.io_allocateEntry_1_dest (e_1_dest),
|
||||
.io_allocateEntry_1_oldDest (_table_io_oldPrd_1),
|
||||
.io_allocateEntry_1_fenceI (io_in_1_isFenceI),
|
||||
.io_allocateEntry_1_sfenceVma (io_in_1_isSfenceVma),
|
||||
.io_allocateEntry_1_xret (io_in_1_isXret),
|
||||
.io_allocateEntry_1_xretIsMret (io_in_1_isMret),
|
||||
.io_allocateIdx_0 (io_out_0_robIdx),
|
||||
.io_allocateIdx_1 (io_out_1_robIdx),
|
||||
.io_canAllocate (_rob_io_canAllocate),
|
||||
@@ -932,9 +997,19 @@ module RenameStage(
|
||||
.io_completeCsrRs1_1 (io_completeCsrRs1_1),
|
||||
.io_completeCsrZimm_0 (io_completeCsrZimm_0),
|
||||
.io_completeCsrZimm_1 (io_completeCsrZimm_1),
|
||||
.io_completeFenceI_0 (io_completeFenceI_0),
|
||||
.io_completeFenceI_1 (io_completeFenceI_1),
|
||||
.io_completeSfenceVma_0 (io_completeSfenceVma_0),
|
||||
.io_completeSfenceVma_1 (io_completeSfenceVma_1),
|
||||
.io_completeXret_0 (io_completeXret_0),
|
||||
.io_completeXret_1 (io_completeXret_1),
|
||||
.io_completeXretIsMret_0 (io_completeXretIsMret_0),
|
||||
.io_completeXretIsMret_1 (io_completeXretIsMret_1),
|
||||
.io_commitValid_0 (io_commitValid_0),
|
||||
.io_commitValid_1 (io_commitValid_1),
|
||||
.io_commit_0_valid (io_commitEntry_0_valid),
|
||||
.io_commit_0_robIdx (io_commitEntry_0_robIdx),
|
||||
.io_commit_0_pc (io_commitEntry_0_pc),
|
||||
.io_commit_0_archDest (io_commitEntry_0_archDest),
|
||||
.io_commit_0_writesDest (io_commitEntry_0_writesDest),
|
||||
.io_commit_0_opClass (io_commitEntry_0_opClass),
|
||||
@@ -951,7 +1026,11 @@ module RenameStage(
|
||||
.io_commit_0_csrRs1 (io_commitEntry_0_csrRs1),
|
||||
.io_commit_0_csrZimm (io_commitEntry_0_csrZimm),
|
||||
.io_commit_0_fenceI (io_commitEntry_0_fenceI),
|
||||
.io_commit_0_sfenceVma (io_commitEntry_0_sfenceVma),
|
||||
.io_commit_0_xret (io_commitEntry_0_xret),
|
||||
.io_commit_0_xretIsMret (io_commitEntry_0_xretIsMret),
|
||||
.io_commit_1_robIdx (io_commitEntry_1_robIdx),
|
||||
.io_commit_1_pc (io_commitEntry_1_pc),
|
||||
.io_commit_1_archDest (io_commitEntry_1_archDest),
|
||||
.io_commit_1_writesDest (io_commitEntry_1_writesDest),
|
||||
.io_commit_1_opClass (io_commitEntry_1_opClass),
|
||||
@@ -968,6 +1047,9 @@ module RenameStage(
|
||||
.io_commit_1_csrRs1 (io_commitEntry_1_csrRs1),
|
||||
.io_commit_1_csrZimm (io_commitEntry_1_csrZimm),
|
||||
.io_commit_1_fenceI (io_commitEntry_1_fenceI),
|
||||
.io_commit_1_sfenceVma (io_commitEntry_1_sfenceVma),
|
||||
.io_commit_1_xret (io_commitEntry_1_xret),
|
||||
.io_commit_1_xretIsMret (io_commitEntry_1_xretIsMret),
|
||||
.io_commitReady_0 (io_commitReady_0),
|
||||
.io_commitReady_1 (io_commitReady_1),
|
||||
.io_flush (io_flush)
|
||||
@@ -998,10 +1080,20 @@ module RenameStage(
|
||||
assign io_out_0_decoded_isWord = io_in_0_isWord;
|
||||
assign io_out_0_decoded_isSystem = io_in_0_isSystem;
|
||||
assign io_out_0_decoded_isFenceI = io_in_0_isFenceI;
|
||||
assign io_out_0_decoded_isEcall = io_in_0_isEcall;
|
||||
assign io_out_0_decoded_isEbreak = io_in_0_isEbreak;
|
||||
assign io_out_0_decoded_isMret = io_in_0_isMret;
|
||||
assign io_out_0_decoded_isSret = io_in_0_isSret;
|
||||
assign io_out_0_decoded_isSfenceVma = io_in_0_isSfenceVma;
|
||||
assign io_out_0_decoded_isXret = io_in_0_isXret;
|
||||
assign io_out_0_decoded_isWfi = io_in_0_isWfi;
|
||||
assign io_out_0_decoded_isAmo = io_in_0_isAmo;
|
||||
assign io_out_0_decoded_amoOp = io_in_0_amoOp;
|
||||
assign io_out_0_decoded_writesRd = io_in_0_writesRd;
|
||||
assign io_out_0_decoded_illegal = io_in_0_illegal;
|
||||
assign io_out_0_decoded_fetchException = io_in_0_fetchException;
|
||||
assign io_out_0_decoded_fetchExceptionCause = io_in_0_fetchExceptionCause;
|
||||
assign io_out_0_decoded_fetchExceptionTval = io_in_0_fetchExceptionTval;
|
||||
assign io_out_0_prs1 = _table_io_prs1_0;
|
||||
assign io_out_0_prs2 = _table_io_prs2_0;
|
||||
assign io_out_0_src1Ready =
|
||||
@@ -1039,10 +1131,20 @@ module RenameStage(
|
||||
assign io_out_1_decoded_isWord = io_in_1_isWord;
|
||||
assign io_out_1_decoded_isSystem = io_in_1_isSystem;
|
||||
assign io_out_1_decoded_isFenceI = io_in_1_isFenceI;
|
||||
assign io_out_1_decoded_isEcall = io_in_1_isEcall;
|
||||
assign io_out_1_decoded_isEbreak = io_in_1_isEbreak;
|
||||
assign io_out_1_decoded_isMret = io_in_1_isMret;
|
||||
assign io_out_1_decoded_isSret = io_in_1_isSret;
|
||||
assign io_out_1_decoded_isSfenceVma = io_in_1_isSfenceVma;
|
||||
assign io_out_1_decoded_isXret = io_in_1_isXret;
|
||||
assign io_out_1_decoded_isWfi = io_in_1_isWfi;
|
||||
assign io_out_1_decoded_isAmo = io_in_1_isAmo;
|
||||
assign io_out_1_decoded_amoOp = io_in_1_amoOp;
|
||||
assign io_out_1_decoded_writesRd = io_in_1_writesRd;
|
||||
assign io_out_1_decoded_illegal = io_in_1_illegal;
|
||||
assign io_out_1_decoded_fetchException = io_in_1_fetchException;
|
||||
assign io_out_1_decoded_fetchExceptionCause = io_in_1_fetchExceptionCause;
|
||||
assign io_out_1_decoded_fetchExceptionTval = io_in_1_fetchExceptionTval;
|
||||
assign io_out_1_prs1 = _table_io_prs1_1;
|
||||
assign io_out_1_prs2 = _table_io_prs2_1;
|
||||
assign io_out_1_src1Ready =
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,3 +1,6 @@
|
||||
ITLB.sv
|
||||
PageTableWalker.sv
|
||||
MMU.sv
|
||||
tags_1024x204.sv
|
||||
data_1024x256.sv
|
||||
ICache.sv
|
||||
@@ -20,12 +23,12 @@ CommitStage.sv
|
||||
LoadQueue.sv
|
||||
StoreQueue.sv
|
||||
DTLB.sv
|
||||
PageTableWalker.sv
|
||||
MMU.sv
|
||||
verification/assert/DCache_Verification_Assert.sv
|
||||
tags_64x416.sv
|
||||
data_64x4096.sv
|
||||
DCache.sv
|
||||
LSU.sv
|
||||
CSRFile.sv
|
||||
OoOBackend.sv
|
||||
PrivilegeControl.sv
|
||||
Core.sv
|
||||
|
||||
@@ -0,0 +1,38 @@
|
||||
// Generated by CIRCT firtool-1.139.0
|
||||
|
||||
// Users can define 'STOP_COND' to add an extra gate to stop conditions.
|
||||
`ifndef STOP_COND_
|
||||
`ifdef STOP_COND
|
||||
`define STOP_COND_ (`STOP_COND)
|
||||
`else // STOP_COND
|
||||
`define STOP_COND_ 1
|
||||
`endif // STOP_COND
|
||||
`endif // not def STOP_COND_
|
||||
|
||||
// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing.
|
||||
`ifndef ASSERT_VERBOSE_COND_
|
||||
`ifdef ASSERT_VERBOSE_COND
|
||||
`define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND)
|
||||
`else // ASSERT_VERBOSE_COND
|
||||
`define ASSERT_VERBOSE_COND_ 1
|
||||
`endif // ASSERT_VERBOSE_COND
|
||||
`endif // not def ASSERT_VERBOSE_COND_
|
||||
module DCache_Verification_Assert();
|
||||
`ifndef SYNTHESIS
|
||||
always @(posedge DCache.clock) begin
|
||||
if (~DCache.reset & DCache.io_reqValid
|
||||
& (|((DCache._storeEndSet_T_6
|
||||
? 3'h0
|
||||
: DCache._storeEndSet_T_4
|
||||
? 3'h4
|
||||
: DCache._storeEndSet_T_2 ? 3'h2 : {2'h0, DCache._storeEndSet_T})
|
||||
- 3'h1 & DCache.io_req_addr[2:0]))) begin
|
||||
if (`ASSERT_VERBOSE_COND_)
|
||||
$error("Assertion failed: DCache received misaligned request; LSU must trap before DCache\n");
|
||||
if (`STOP_COND_)
|
||||
$fatal;
|
||||
end
|
||||
end // always @(posedge)
|
||||
`endif // not def SYNTHESIS
|
||||
endmodule
|
||||
|
||||
@@ -2,4 +2,5 @@
|
||||
`ifndef layers_Core_Verification_Assert
|
||||
`define layers_Core_Verification_Assert
|
||||
`include "layers-Core-Verification.sv"
|
||||
`include "layers-OoOBackend-Verification-Assert.sv"
|
||||
`endif // not def layers_Core_Verification_Assert
|
||||
|
||||
@@ -0,0 +1,6 @@
|
||||
// Generated by CIRCT firtool-1.139.0
|
||||
`ifndef layers_DCache_Verification_Assert
|
||||
`define layers_DCache_Verification_Assert
|
||||
`include "layers-DCache-Verification.sv"
|
||||
bind DCache DCache_Verification_Assert verification_assert ();
|
||||
`endif // not def layers_DCache_Verification_Assert
|
||||
@@ -0,0 +1,6 @@
|
||||
// Generated by CIRCT firtool-1.139.0
|
||||
`ifndef layers_LSU_Verification_Assert
|
||||
`define layers_LSU_Verification_Assert
|
||||
`include "layers-LSU-Verification.sv"
|
||||
`include "layers-DCache-Verification-Assert.sv"
|
||||
`endif // not def layers_LSU_Verification_Assert
|
||||
@@ -0,0 +1,6 @@
|
||||
// Generated by CIRCT firtool-1.139.0
|
||||
`ifndef layers_OoOBackend_Verification_Assert
|
||||
`define layers_OoOBackend_Verification_Assert
|
||||
`include "layers-OoOBackend-Verification.sv"
|
||||
`include "layers-LSU-Verification-Assert.sv"
|
||||
`endif // not def layers_OoOBackend_Verification_Assert
|
||||
@@ -1,4 +1,5 @@
|
||||
// Generated by CIRCT firtool-1.139.0
|
||||
`ifndef layers_Core_Verification
|
||||
`define layers_Core_Verification
|
||||
`include "layers-OoOBackend-Verification.sv"
|
||||
`endif // not def layers_Core_Verification
|
||||
|
||||
4
generated-ooo/verification/layers-DCache-Verification.sv
Normal file
4
generated-ooo/verification/layers-DCache-Verification.sv
Normal file
@@ -0,0 +1,4 @@
|
||||
// Generated by CIRCT firtool-1.139.0
|
||||
`ifndef layers_DCache_Verification
|
||||
`define layers_DCache_Verification
|
||||
`endif // not def layers_DCache_Verification
|
||||
5
generated-ooo/verification/layers-LSU-Verification.sv
Normal file
5
generated-ooo/verification/layers-LSU-Verification.sv
Normal file
@@ -0,0 +1,5 @@
|
||||
// Generated by CIRCT firtool-1.139.0
|
||||
`ifndef layers_LSU_Verification
|
||||
`define layers_LSU_Verification
|
||||
`include "layers-DCache-Verification.sv"
|
||||
`endif // not def layers_LSU_Verification
|
||||
@@ -1,6 +1,5 @@
|
||||
// Generated by CIRCT firtool-1.139.0
|
||||
`ifndef layers_OoOBackend_Verification
|
||||
`define layers_OoOBackend_Verification
|
||||
`include "layers-RenameStage-Verification.sv"
|
||||
bind OoOBackend OoOBackend_Verification verification ();
|
||||
`include "layers-LSU-Verification.sv"
|
||||
`endif // not def layers_OoOBackend_Verification
|
||||
|
||||
Reference in New Issue
Block a user