fix: resolve OoO simulation timeout
This commit is contained in:
abnerhexu
@@ -4,23 +4,50 @@ import chisel3.util._
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class FreeList(p: CoreParams = CoreParams()) extends Module {
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private val physBits = log2Ceil(p.physRegs)
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val io = IO(new Bundle {
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val alloc = Input(Bool())
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val allocPhys = Output(UInt(physBits.W))
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val canAlloc = Output(Bool())
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val free = Input(Bool())
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val freePhys = Input(UInt(physBits.W))
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val allocReq = Input(Vec(p.issueWidth, Bool()))
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val allocPhys = Output(Vec(p.issueWidth, UInt(physBits.W)))
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val allocValid = Output(Vec(p.issueWidth, Bool()))
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val canAllocate = Output(Bool())
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val freeReq = Input(Vec(p.issueWidth, Bool()))
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val freePhys = Input(Vec(p.issueWidth, UInt(physBits.W)))
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val recover = Input(Bool())
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val committedPhys = Input(Vec(p.archRegs, UInt(physBits.W)))
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})
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val freeBits = RegInit(VecInit((0 until p.physRegs).map(i => (i >= p.archRegs).B)))
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val chosen = PriorityEncoder(freeBits)
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io.canAlloc := freeBits.asUInt.orR
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io.allocPhys := chosen
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val freeMask = freeBits.asUInt
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val firstOH = PriorityEncoderOH(freeMask)
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val secondMask = freeMask & ~firstOH
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val secondOH = PriorityEncoderOH(secondMask)
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val freeCount = PopCount(freeMask)
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dontTouch(freeMask)
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dontTouch(freeCount)
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when(io.alloc && io.canAlloc) {
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freeBits(chosen) := false.B
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io.canAllocate := freeCount >= p.issueWidth.U
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io.allocPhys(0) := OHToUInt(firstOH)
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io.allocPhys(1) := OHToUInt(secondOH)
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io.allocValid(0) := io.allocReq(0) && freeMask.orR
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io.allocValid(1) := io.allocReq(1) && secondMask.orR
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val nextFree = Wire(Vec(p.physRegs, Bool()))
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nextFree := freeBits
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when(io.allocReq(0) && io.allocValid(0)) {
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nextFree(io.allocPhys(0)) := false.B
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}
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when(io.free && io.freePhys >= p.archRegs.U) {
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freeBits(io.freePhys) := true.B
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when(io.allocReq(1) && io.allocValid(1)) {
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nextFree(io.allocPhys(1)) := false.B
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}
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for (i <- 0 until p.issueWidth) {
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when(io.freeReq(i) && io.freePhys(i) =/= 0.U) {
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nextFree(io.freePhys(i)) := true.B
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}
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}
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when(io.recover) {
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for (i <- 0 until p.physRegs) {
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val isCommitted = io.committedPhys.map(_ === i.U).foldLeft(false.B)(_ || _)
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freeBits(i) := !isCommitted
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}
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}.otherwise {
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freeBits := nextFree
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}
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}
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@@ -3,69 +3,184 @@ import chisel3.util._
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class RobEntry(p: CoreParams = CoreParams()) extends Bundle {
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val valid = Bool()
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val robIdx = UInt(log2Ceil(p.robEntries).W)
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val pc = UInt(p.xlen.W)
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val archDest = UInt(5.W)
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val writesDest = Bool()
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val opClass = UInt(Consts.OpClassWidth.W)
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val dest = UInt(log2Ceil(p.physRegs).W)
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val oldDest = UInt(log2Ceil(p.physRegs).W)
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val completed = Bool()
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val exception = Bool()
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val exceptionCause = UInt(p.xlen.W)
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val badAddr = UInt(p.xlen.W)
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val branchMispredict = Bool()
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val redirectPc = UInt(p.xlen.W)
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val csrValid = Bool()
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val csrAddr = UInt(12.W)
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val csrCmd = UInt(3.W)
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val csrRs1 = UInt(p.xlen.W)
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val csrZimm = UInt(5.W)
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}
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class ROB(p: CoreParams = CoreParams()) extends Module {
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private val idxBits = log2Ceil(p.robEntries)
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val io = IO(new Bundle {
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val allocate = Input(Bool())
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val allocatePc = Input(UInt(p.xlen.W))
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val allocateClass = Input(UInt(Consts.OpClassWidth.W))
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val allocateDest = Input(UInt(log2Ceil(p.physRegs).W))
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val allocateOldDest = Input(UInt(log2Ceil(p.physRegs).W))
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val allocateIdx = Output(UInt(idxBits.W))
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val allocateValid = Input(Vec(p.issueWidth, Bool()))
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val allocateEntry = Input(Vec(p.issueWidth, new RobEntry(p)))
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val allocateIdx = Output(Vec(p.issueWidth, UInt(idxBits.W)))
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val canAllocate = Output(Bool())
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val complete = Input(Bool())
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val completeIdx = Input(UInt(idxBits.W))
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val commitValid = Output(Bool())
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val commit = Output(new RobEntry(p))
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val commitReady = Input(Bool())
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val completeValid = Input(Vec(p.issueWidth, Bool()))
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val completeIdx = Input(Vec(p.issueWidth, UInt(idxBits.W)))
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val completeException = Input(Vec(p.issueWidth, Bool()))
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val completeCause = Input(Vec(p.issueWidth, UInt(p.xlen.W)))
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val completeBadAddr = Input(Vec(p.issueWidth, UInt(p.xlen.W)))
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val completeMispredict = Input(Vec(p.issueWidth, Bool()))
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val completeRedirectPc = Input(Vec(p.issueWidth, UInt(p.xlen.W)))
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val completeCsrValid = Input(Vec(p.issueWidth, Bool()))
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val completeCsrAddr = Input(Vec(p.issueWidth, UInt(12.W)))
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val completeCsrCmd = Input(Vec(p.issueWidth, UInt(3.W)))
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val completeCsrRs1 = Input(Vec(p.issueWidth, UInt(p.xlen.W)))
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val completeCsrZimm = Input(Vec(p.issueWidth, UInt(5.W)))
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val commitValid = Output(Vec(p.issueWidth, Bool()))
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val commit = Output(Vec(p.issueWidth, new RobEntry(p)))
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val commitReady = Input(Vec(p.issueWidth, Bool()))
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val flush = Input(Bool())
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val empty = Output(Bool())
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})
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val entries = RegInit(VecInit(Seq.fill(p.robEntries)(0.U.asTypeOf(new RobEntry(p)))))
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val valid = RegInit(VecInit(Seq.fill(p.robEntries)(false.B)))
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val completed = RegInit(VecInit(Seq.fill(p.robEntries)(false.B)))
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val exception = RegInit(VecInit(Seq.fill(p.robEntries)(false.B)))
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val exceptionCause = RegInit(VecInit(Seq.fill(p.robEntries)(0.U(p.xlen.W))))
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val badAddr = RegInit(VecInit(Seq.fill(p.robEntries)(0.U(p.xlen.W))))
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val branchMispredict = RegInit(VecInit(Seq.fill(p.robEntries)(false.B)))
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val redirectPc = RegInit(VecInit(Seq.fill(p.robEntries)(0.U(p.xlen.W))))
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val csrValid = RegInit(VecInit(Seq.fill(p.robEntries)(false.B)))
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val csrAddr = RegInit(VecInit(Seq.fill(p.robEntries)(0.U(12.W))))
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val csrCmd = RegInit(VecInit(Seq.fill(p.robEntries)(0.U(3.W))))
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val csrRs1 = RegInit(VecInit(Seq.fill(p.robEntries)(0.U(p.xlen.W))))
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val csrZimm = RegInit(VecInit(Seq.fill(p.robEntries)(0.U(5.W))))
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val head = RegInit(0.U(idxBits.W))
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val tail = RegInit(0.U(idxBits.W))
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val count = RegInit(0.U(log2Ceil(p.robEntries + 1).W))
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val allocCount = PopCount(io.allocateValid)
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io.canAllocate := count =/= p.robEntries.U
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io.allocateIdx := tail
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io.commit := entries(head)
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io.commitValid := count =/= 0.U && entries(head).valid && entries(head).completed
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val head0 = head
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val head1 = head + 1.U
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val tail0 = tail
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val tail1 = tail + 1.U
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val headEntry0 = Wire(new RobEntry(p))
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val headEntry1 = Wire(new RobEntry(p))
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headEntry0 := entries(head0)
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headEntry0.valid := valid(head0)
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headEntry0.completed := completed(head0)
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headEntry0.exception := exception(head0)
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headEntry0.exceptionCause := exceptionCause(head0)
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headEntry0.badAddr := badAddr(head0)
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headEntry0.branchMispredict := branchMispredict(head0)
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headEntry0.redirectPc := redirectPc(head0)
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headEntry0.csrValid := csrValid(head0)
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headEntry0.csrAddr := csrAddr(head0)
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headEntry0.csrCmd := csrCmd(head0)
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headEntry0.csrRs1 := csrRs1(head0)
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headEntry0.csrZimm := csrZimm(head0)
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headEntry1 := entries(head1)
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headEntry1.valid := valid(head1)
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headEntry1.completed := completed(head1)
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headEntry1.exception := exception(head1)
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headEntry1.exceptionCause := exceptionCause(head1)
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headEntry1.badAddr := badAddr(head1)
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headEntry1.branchMispredict := branchMispredict(head1)
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headEntry1.redirectPc := redirectPc(head1)
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headEntry1.csrValid := csrValid(head1)
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headEntry1.csrAddr := csrAddr(head1)
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headEntry1.csrCmd := csrCmd(head1)
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headEntry1.csrRs1 := csrRs1(head1)
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headEntry1.csrZimm := csrZimm(head1)
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io.empty := count === 0.U
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io.canAllocate := (p.robEntries.U - count) >= p.issueWidth.U
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io.allocateIdx(0) := tail0
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io.allocateIdx(1) := tail1
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io.commit(0) := headEntry0
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io.commit(1) := headEntry1
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io.commitValid(0) := count =/= 0.U && valid(head0) && completed(head0)
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io.commitValid(1) := count > 1.U && io.commitValid(0) && !headEntry0.exception &&
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!headEntry0.branchMispredict && valid(head1) && completed(head1)
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when(io.flush) {
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entries.foreach(_.valid := false.B)
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valid := VecInit(Seq.fill(p.robEntries)(false.B))
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completed := VecInit(Seq.fill(p.robEntries)(false.B))
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exception := VecInit(Seq.fill(p.robEntries)(false.B))
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branchMispredict := VecInit(Seq.fill(p.robEntries)(false.B))
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csrValid := VecInit(Seq.fill(p.robEntries)(false.B))
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head := 0.U
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tail := 0.U
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count := 0.U
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}.otherwise {
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when(io.allocate && io.canAllocate) {
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entries(tail).valid := true.B
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entries(tail).pc := io.allocatePc
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entries(tail).opClass := io.allocateClass
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entries(tail).dest := io.allocateDest
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entries(tail).oldDest := io.allocateOldDest
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entries(tail).completed := false.B
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entries(tail).exception := false.B
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entries(tail).branchMispredict := false.B
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tail := tail + 1.U
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count := count + 1.U
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when(io.allocateValid(0) && io.canAllocate) {
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entries(tail0) := io.allocateEntry(0)
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entries(tail0).robIdx := tail0
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valid(tail0) := true.B
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completed(tail0) := false.B
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exception(tail0) := false.B
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exceptionCause(tail0) := 0.U
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badAddr(tail0) := 0.U
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branchMispredict(tail0) := false.B
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redirectPc(tail0) := 0.U
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csrValid(tail0) := false.B
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csrAddr(tail0) := 0.U
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csrCmd(tail0) := 0.U
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csrRs1(tail0) := 0.U
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csrZimm(tail0) := 0.U
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}
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when(io.complete) {
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entries(io.completeIdx).completed := true.B
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when(io.allocateValid(1) && io.canAllocate) {
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entries(tail1) := io.allocateEntry(1)
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entries(tail1).robIdx := tail1
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valid(tail1) := true.B
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completed(tail1) := false.B
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exception(tail1) := false.B
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exceptionCause(tail1) := 0.U
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badAddr(tail1) := 0.U
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branchMispredict(tail1) := false.B
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redirectPc(tail1) := 0.U
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csrValid(tail1) := false.B
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csrAddr(tail1) := 0.U
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csrCmd(tail1) := 0.U
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csrRs1(tail1) := 0.U
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csrZimm(tail1) := 0.U
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}
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when(io.commitValid && io.commitReady) {
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entries(head).valid := false.B
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head := head + 1.U
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count := count - 1.U
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for (i <- 0 until p.issueWidth) {
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when(io.completeValid(i)) {
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completed(io.completeIdx(i)) := true.B
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exception(io.completeIdx(i)) := io.completeException(i)
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exceptionCause(io.completeIdx(i)) := io.completeCause(i)
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badAddr(io.completeIdx(i)) := io.completeBadAddr(i)
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branchMispredict(io.completeIdx(i)) := io.completeMispredict(i)
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redirectPc(io.completeIdx(i)) := io.completeRedirectPc(i)
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csrValid(io.completeIdx(i)) := io.completeCsrValid(i)
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csrAddr(io.completeIdx(i)) := io.completeCsrAddr(i)
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csrCmd(io.completeIdx(i)) := io.completeCsrCmd(i)
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csrRs1(io.completeIdx(i)) := io.completeCsrRs1(i)
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csrZimm(io.completeIdx(i)) := io.completeCsrZimm(i)
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}
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}
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val commit0 = io.commitValid(0) && io.commitReady(0)
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val commit1 = io.commitValid(1) && io.commitReady(1)
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when(commit0) { valid(head0) := false.B }
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when(commit1) { valid(head1) := false.B }
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val committed = PopCount(VecInit(Seq(commit0, commit1)))
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val allocated = Mux(io.canAllocate, allocCount, 0.U)
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head := head + committed
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tail := tail + allocated
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count := count + allocated - committed
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when(!commit0 && !commit1 && allocated === 0.U) {
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head := head
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tail := tail
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count := count
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}
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}
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}
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@@ -2,13 +2,43 @@ import chisel3._
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import chisel3.util._
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class RenameStage(p: CoreParams = CoreParams()) extends Module {
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private val physBits = log2Ceil(p.physRegs)
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private val robBits = log2Ceil(p.robEntries)
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val io = IO(new Bundle {
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val inValid = Input(Bool())
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val in = Input(new DecodedInst(p))
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val outValid = Output(Bool())
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val out = Output(new RenamePacket(p))
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val commitFree = Input(Bool())
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val commitOldPhys = Input(UInt(log2Ceil(p.physRegs).W))
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val inValid = Input(Vec(p.issueWidth, Bool()))
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val in = Input(Vec(p.issueWidth, new DecodedInst(p)))
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val outValid = Output(Vec(p.issueWidth, Bool()))
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val out = Output(Vec(p.issueWidth, new RenamePacket(p)))
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val canAccept = Output(Bool())
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val wbValid = Input(Vec(p.issueWidth, Bool()))
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val wbPhys = Input(Vec(p.issueWidth, UInt(physBits.W)))
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val completeValid = Input(Vec(p.issueWidth, Bool()))
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val completeIdx = Input(Vec(p.issueWidth, UInt(robBits.W)))
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val completeException = Input(Vec(p.issueWidth, Bool()))
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val completeCause = Input(Vec(p.issueWidth, UInt(p.xlen.W)))
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val completeBadAddr = Input(Vec(p.issueWidth, UInt(p.xlen.W)))
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val completeMispredict = Input(Vec(p.issueWidth, Bool()))
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val completeRedirectPc = Input(Vec(p.issueWidth, UInt(p.xlen.W)))
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val completeCsrValid = Input(Vec(p.issueWidth, Bool()))
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val completeCsrAddr = Input(Vec(p.issueWidth, UInt(12.W)))
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val completeCsrCmd = Input(Vec(p.issueWidth, UInt(3.W)))
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val completeCsrRs1 = Input(Vec(p.issueWidth, UInt(p.xlen.W)))
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val completeCsrZimm = Input(Vec(p.issueWidth, UInt(5.W)))
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val commitReady = Input(Vec(p.issueWidth, Bool()))
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val commitValid = Output(Vec(p.issueWidth, Bool()))
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val commitEntry = Output(Vec(p.issueWidth, new RobEntry(p)))
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val robEmpty = Output(Bool())
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val commitMapValid = Input(Vec(p.issueWidth, Bool()))
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val commitArch = Input(Vec(p.issueWidth, UInt(5.W)))
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val commitPhys = Input(Vec(p.issueWidth, UInt(physBits.W)))
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val commitFreeOld = Input(Vec(p.issueWidth, Bool()))
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val commitOldPhys = Input(Vec(p.issueWidth, UInt(physBits.W)))
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val flush = Input(Bool())
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})
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@@ -16,34 +46,97 @@ class RenameStage(p: CoreParams = CoreParams()) extends Module {
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val freeList = Module(new FreeList(p))
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val rob = Module(new ROB(p))
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table.io.rs1 := io.in.rs1
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table.io.rs2 := io.in.rs2
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table.io.rd := io.in.rd
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val needsPhys = Wire(Vec(p.issueWidth, Bool()))
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for (i <- 0 until p.issueWidth) {
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needsPhys(i) := io.inValid(i) && io.in(i).writesRd
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}
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table.io.rs1 := VecInit(io.in.map(_.rs1))
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table.io.rs2 := VecInit(io.in.map(_.rs2))
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table.io.rd := VecInit(io.in.map(_.rd))
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table.io.newPhys := freeList.io.allocPhys
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table.io.wen := io.inValid && io.in.writesRd && freeList.io.canAlloc && rob.io.canAllocate
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table.io.wen := VecInit((0 until p.issueWidth).map(i => io.outValid(i) && io.in(i).writesRd))
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table.io.commitWen := io.commitMapValid
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table.io.commitRd := io.commitArch
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table.io.commitPhys := io.commitPhys
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table.io.recover := io.flush
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freeList.io.alloc := table.io.wen
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freeList.io.free := io.commitFree
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freeList.io.allocReq := needsPhys
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freeList.io.freeReq := io.commitFreeOld
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freeList.io.freePhys := io.commitOldPhys
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freeList.io.recover := io.flush
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freeList.io.committedPhys := table.io.committedPhys
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rob.io.allocate := io.inValid && rob.io.canAllocate && (!io.in.writesRd || freeList.io.canAlloc)
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rob.io.allocatePc := io.in.pc
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rob.io.allocateClass := io.in.opClass
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rob.io.allocateDest := Mux(io.in.writesRd, freeList.io.allocPhys, table.io.oldPrd)
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rob.io.allocateOldDest := table.io.oldPrd
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rob.io.complete := false.B
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rob.io.completeIdx := 0.U
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rob.io.commitReady := false.B
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val requested = PopCount(io.inValid)
|
||||
val canRename = freeList.io.canAllocate && rob.io.canAllocate
|
||||
io.canAccept := canRename
|
||||
|
||||
val readyReg = RegInit(VecInit(Seq.fill(p.physRegs)(true.B)))
|
||||
when(io.flush) {
|
||||
readyReg := VecInit(Seq.fill(p.physRegs)(true.B))
|
||||
}.otherwise {
|
||||
for (i <- 0 until p.issueWidth) {
|
||||
when(io.wbValid(i)) {
|
||||
readyReg(io.wbPhys(i)) := true.B
|
||||
}
|
||||
when(io.outValid(i) && io.in(i).writesRd) {
|
||||
readyReg(freeList.io.allocPhys(i)) := false.B
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
rob.io.allocateValid := VecInit((0 until p.issueWidth).map(i => io.inValid(i) && canRename))
|
||||
for (i <- 0 until p.issueWidth) {
|
||||
val e = WireDefault(0.U.asTypeOf(new RobEntry(p)))
|
||||
e.valid := io.inValid(i) && canRename
|
||||
e.pc := io.in(i).pc
|
||||
e.archDest := io.in(i).rd
|
||||
e.writesDest := io.in(i).writesRd
|
||||
e.opClass := io.in(i).opClass
|
||||
e.dest := Mux(io.in(i).writesRd, freeList.io.allocPhys(i), table.io.oldPrd(i))
|
||||
e.oldDest := table.io.oldPrd(i)
|
||||
rob.io.allocateEntry(i) := e
|
||||
}
|
||||
rob.io.completeValid := io.completeValid
|
||||
rob.io.completeIdx := io.completeIdx
|
||||
rob.io.completeException := io.completeException
|
||||
rob.io.completeCause := io.completeCause
|
||||
rob.io.completeBadAddr := io.completeBadAddr
|
||||
rob.io.completeMispredict := io.completeMispredict
|
||||
rob.io.completeRedirectPc := io.completeRedirectPc
|
||||
rob.io.completeCsrValid := io.completeCsrValid
|
||||
rob.io.completeCsrAddr := io.completeCsrAddr
|
||||
rob.io.completeCsrCmd := io.completeCsrCmd
|
||||
rob.io.completeCsrRs1 := io.completeCsrRs1
|
||||
rob.io.completeCsrZimm := io.completeCsrZimm
|
||||
rob.io.commitReady := io.commitReady
|
||||
rob.io.flush := io.flush
|
||||
io.commitValid := rob.io.commitValid
|
||||
io.commitEntry := rob.io.commit
|
||||
io.robEmpty := rob.io.empty
|
||||
|
||||
io.outValid := rob.io.allocate
|
||||
io.out.valid := io.outValid
|
||||
io.out.decoded := io.in
|
||||
io.out.prs1 := table.io.prs1
|
||||
io.out.prs2 := table.io.prs2
|
||||
io.out.prd := Mux(io.in.writesRd, freeList.io.allocPhys, table.io.oldPrd)
|
||||
io.out.oldPrd := table.io.oldPrd
|
||||
io.out.robIdx := rob.io.allocateIdx
|
||||
for (i <- 0 until p.issueWidth) {
|
||||
val src1FromOlder = (0 until i).map(j =>
|
||||
io.outValid(j) && io.in(j).writesRd && io.in(j).rd =/= 0.U && io.in(j).rd === io.in(i).rs1
|
||||
).foldLeft(false.B)(_ || _)
|
||||
val src2FromOlder = (0 until i).map(j =>
|
||||
io.outValid(j) && io.in(j).writesRd && io.in(j).rd =/= 0.U && io.in(j).rd === io.in(i).rs2
|
||||
).foldLeft(false.B)(_ || _)
|
||||
|
||||
io.outValid(i) := io.inValid(i) && canRename
|
||||
io.out(i).valid := io.outValid(i)
|
||||
io.out(i).decoded := io.in(i)
|
||||
io.out(i).prs1 := table.io.prs1(i)
|
||||
io.out(i).prs2 := table.io.prs2(i)
|
||||
io.out(i).src1Ready := io.in(i).rs1 === 0.U || (!src1FromOlder && readyReg(table.io.prs1(i)))
|
||||
io.out(i).src2Ready := io.in(i).rs2 === 0.U || (!src2FromOlder && readyReg(table.io.prs2(i)))
|
||||
io.out(i).prd := Mux(io.in(i).writesRd, freeList.io.allocPhys(i), table.io.oldPrd(i))
|
||||
io.out(i).oldPrd := table.io.oldPrd(i)
|
||||
io.out(i).robIdx := rob.io.allocateIdx(i)
|
||||
|
||||
}
|
||||
|
||||
when(requested === 0.U) {
|
||||
io.canAccept := true.B
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -4,29 +4,45 @@ import chisel3.util._
|
||||
class RenameTable(p: CoreParams = CoreParams()) extends Module {
|
||||
private val physBits = log2Ceil(p.physRegs)
|
||||
val io = IO(new Bundle {
|
||||
val rs1 = Input(UInt(5.W))
|
||||
val rs2 = Input(UInt(5.W))
|
||||
val rd = Input(UInt(5.W))
|
||||
val newPhys = Input(UInt(physBits.W))
|
||||
val wen = Input(Bool())
|
||||
val prs1 = Output(UInt(physBits.W))
|
||||
val prs2 = Output(UInt(physBits.W))
|
||||
val oldPrd = Output(UInt(physBits.W))
|
||||
val rs1 = Input(Vec(p.issueWidth, UInt(5.W)))
|
||||
val rs2 = Input(Vec(p.issueWidth, UInt(5.W)))
|
||||
val rd = Input(Vec(p.issueWidth, UInt(5.W)))
|
||||
val newPhys = Input(Vec(p.issueWidth, UInt(physBits.W)))
|
||||
val wen = Input(Vec(p.issueWidth, Bool()))
|
||||
val prs1 = Output(Vec(p.issueWidth, UInt(physBits.W)))
|
||||
val prs2 = Output(Vec(p.issueWidth, UInt(physBits.W)))
|
||||
val oldPrd = Output(Vec(p.issueWidth, UInt(physBits.W)))
|
||||
val commitWen = Input(Vec(p.issueWidth, Bool()))
|
||||
val commitRd = Input(Vec(p.issueWidth, UInt(5.W)))
|
||||
val commitPhys = Input(Vec(p.issueWidth, UInt(physBits.W)))
|
||||
val recover = Input(Bool())
|
||||
val committedPhys = Output(Vec(p.archRegs, UInt(physBits.W)))
|
||||
})
|
||||
|
||||
val init = VecInit((0 until p.archRegs).map(_.U(physBits.W)))
|
||||
val speculative = RegInit(init)
|
||||
val committed = RegInit(init)
|
||||
io.committedPhys := committed
|
||||
|
||||
io.prs1 := speculative(io.rs1)
|
||||
io.prs2 := speculative(io.rs2)
|
||||
io.oldPrd := speculative(io.rd)
|
||||
io.prs1(0) := speculative(io.rs1(0))
|
||||
io.prs2(0) := speculative(io.rs2(0))
|
||||
io.oldPrd(0) := speculative(io.rd(0))
|
||||
|
||||
val slot0Writes = io.wen(0) && io.rd(0) =/= 0.U
|
||||
io.prs1(1) := Mux(slot0Writes && io.rd(0) === io.rs1(1), io.newPhys(0), speculative(io.rs1(1)))
|
||||
io.prs2(1) := Mux(slot0Writes && io.rd(0) === io.rs2(1), io.newPhys(0), speculative(io.rs2(1)))
|
||||
io.oldPrd(1) := Mux(slot0Writes && io.rd(0) === io.rd(1), io.newPhys(0), speculative(io.rd(1)))
|
||||
|
||||
when(io.recover) {
|
||||
speculative := committed
|
||||
}.elsewhen(io.wen && io.rd =/= 0.U) {
|
||||
speculative(io.rd) := io.newPhys
|
||||
}.otherwise {
|
||||
for (i <- 0 until p.issueWidth) {
|
||||
when(io.wen(i) && io.rd(i) =/= 0.U) {
|
||||
speculative(io.rd(i)) := io.newPhys(i)
|
||||
}
|
||||
when(io.commitWen(i) && io.commitRd(i) =/= 0.U) {
|
||||
committed(io.commitRd(i)) := io.commitPhys(i)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user