fix: resolve OoO simulation timeout
This commit is contained in:
abnerhexu
@@ -1,23 +1,180 @@
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import chisel3._
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import chisel3.util._
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class ICache(p: CoreParams = CoreParams()) extends Module {
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private val lineInsts = p.fetchWidth
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private val lineBytes = lineInsts * 4
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private val sets = p.iCacheBytes / (p.iCacheWays * lineBytes)
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private val setBits = log2Ceil(sets)
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private val instBits = log2Ceil(lineInsts)
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private val offsetBits = log2Ceil(lineBytes)
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val io = IO(new Bundle {
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val reqValid = Input(Bool())
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val reqAddr = Input(UInt(p.xlen.W))
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val reqPc = Input(UInt(p.xlen.W))
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val flush = Input(Bool())
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val respReady = Input(Bool())
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val memReqValid = Output(Bool())
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val memReqAddr = Output(UInt(p.xlen.W))
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val memRespValid = Input(Bool())
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val memRespBits = Input(Vec(p.fetchWidth, UInt(32.W)))
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val respValid = Output(Bool())
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val resp = Output(new FetchPacket(p))
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val miss = Output(Bool())
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})
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io.memReqValid := io.reqValid
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io.memReqAddr := io.reqAddr
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io.respValid := io.memRespValid
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io.resp.pc := io.reqAddr
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io.resp.inst := io.memRespBits
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io.resp.predictedTaken := false.B
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io.resp.predictedTarget := io.reqAddr + (4 * p.fetchWidth).U
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}
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def setIndex(addr: UInt): UInt = addr(offsetBits + setBits - 1, offsetBits)
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def instIndex(addr: UInt): UInt = addr(offsetBits - 1, 2)
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def tag(addr: UInt): UInt = addr(p.xlen - 1, offsetBits + setBits)
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def alignedFetchAddr(addr: UInt): UInt = Cat(addr(p.xlen - 1, offsetBits), 0.U(offsetBits.W))
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val valid = RegInit(VecInit(Seq.fill(sets)(VecInit(Seq.fill(p.iCacheWays)(
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VecInit(Seq.fill(lineInsts)(false.B)))))))
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val tags = SyncReadMem(sets, Vec(p.iCacheWays, UInt((p.xlen - offsetBits - setBits).W)))
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val data = SyncReadMem(sets, Vec(p.iCacheWays, Vec(lineInsts, UInt(32.W))))
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val repl = RegInit(VecInit(Seq.fill(sets)(0.U(log2Ceil(p.iCacheWays).W))))
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val sIdle :: sLookup :: sResp :: sMiss :: Nil = Enum(4)
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val state = RegInit(sIdle)
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val lookupAddr = Reg(UInt(p.xlen.W))
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val lookupPc = Reg(UInt(p.xlen.W))
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val lookupSet = Reg(UInt(setBits.W))
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val lookupInst = Reg(UInt(instBits.W))
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val lookupValidRow = Reg(Vec(p.iCacheWays, Vec(lineInsts, Bool())))
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val missAddr = Reg(UInt(p.xlen.W))
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val missPc = Reg(UInt(p.xlen.W))
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val missSet = Reg(UInt(setBits.W))
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val missInst = Reg(UInt(instBits.W))
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val missWay = Reg(UInt(log2Ceil(p.iCacheWays).W))
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val missRefillExisting = Reg(Bool())
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val missTagRow = Reg(Vec(p.iCacheWays, UInt((p.xlen - offsetBits - setBits).W)))
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val missDataRow = Reg(Vec(p.iCacheWays, Vec(lineInsts, UInt(32.W))))
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val missValidRow = Reg(Vec(p.iCacheWays, Vec(lineInsts, Bool())))
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val missReqSent = RegInit(false.B)
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val respReg = Reg(new FetchPacket(p))
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val reqSet = setIndex(io.reqAddr)
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val reqInst = instIndex(io.reqAddr)
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val readFire = state === sIdle && io.reqValid && !io.flush
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val readTags = tags.read(reqSet, readFire)
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val readData = data.read(reqSet, readFire)
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val tagHitVec = VecInit((0 until p.iCacheWays).map(w => lookupValidRow(w).asUInt.orR && readTags(w) === tag(lookupAddr)))
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val hitVec = VecInit((0 until p.iCacheWays).map(w => tagHitVec(w) && lookupValidRow(w)(lookupInst)))
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val hit = hitVec.asUInt.orR
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val hitWay = OHToUInt(hitVec)
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val tagHit = tagHitVec.asUInt.orR
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val tagHitWay = OHToUInt(tagHitVec)
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val lastInst = (lineInsts - 1).U(instBits.W)
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val nextInst = lookupInst + 1.U
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val lookupCanFetchPair = lookupInst =/= lastInst
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val lookupLane1Valid = lookupCanFetchPair && lookupValidRow(hitWay)(nextInst)
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val lookupResp = WireDefault(0.U.asTypeOf(new FetchPacket(p)))
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lookupResp.pc := lookupPc
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lookupResp.inst(0) := readData(hitWay)(lookupInst)
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lookupResp.inst(1) := Mux(lookupLane1Valid, readData(hitWay)(nextInst), 0.U)
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lookupResp.laneValid(0) := true.B
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lookupResp.laneValid(1) := lookupLane1Valid
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lookupResp.predictedTaken := false.B
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lookupResp.predictedTarget := lookupPc + (4 * p.fetchWidth).U
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val missCanFetchPair = missInst =/= lastInst
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val missResp = WireDefault(0.U.asTypeOf(new FetchPacket(p)))
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missResp.pc := missPc
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missResp.inst(0) := io.memRespBits(0)
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missResp.inst(1) := Mux(missCanFetchPair, io.memRespBits(1), 0.U)
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missResp.laneValid(0) := true.B
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missResp.laneValid(1) := missCanFetchPair
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missResp.predictedTaken := false.B
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missResp.predictedTarget := missPc + (4 * p.fetchWidth).U
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io.memReqValid := state === sMiss && !missReqSent
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io.memReqAddr := Mux(state === sMiss,
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Mux(missCanFetchPair, alignedFetchAddr(missAddr), missAddr),
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Mux(reqInst =/= lastInst, alignedFetchAddr(io.reqAddr), io.reqAddr))
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io.respValid := (state === sLookup && hit) || state === sResp || (state === sMiss && io.memRespValid)
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io.resp := Mux(state === sResp, respReg,
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Mux(state === sMiss && io.memRespValid, missResp, lookupResp))
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io.miss := state === sLookup && !hit || state === sMiss
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when(io.flush) {
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state := sIdle
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missReqSent := false.B
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}.elsewhen(state === sIdle) {
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when(io.reqValid) {
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lookupAddr := io.reqAddr
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lookupPc := io.reqPc
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lookupSet := reqSet
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lookupInst := reqInst
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lookupValidRow := valid(reqSet)
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state := sLookup
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}
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}.elsewhen(state === sLookup) {
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when(hit) {
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repl(lookupSet) := hitWay
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when(io.respReady) {
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state := sIdle
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}.otherwise {
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respReg := lookupResp
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state := sResp
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}
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}.otherwise {
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missAddr := lookupAddr
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missPc := lookupPc
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missSet := lookupSet
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missInst := lookupInst
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missWay := Mux(tagHit, tagHitWay, repl(lookupSet))
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missRefillExisting := tagHit
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missTagRow := readTags
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missDataRow := readData
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missValidRow := lookupValidRow
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missReqSent := false.B
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state := sMiss
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}
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}.elsewhen(state === sResp) {
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when(io.respReady) {
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state := sIdle
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}
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}.elsewhen(state === sMiss) {
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when(!missReqSent) {
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missReqSent := true.B
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}
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when(io.memRespValid) {
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val tagWrite = Wire(Vec(p.iCacheWays, UInt((p.xlen - offsetBits - setBits).W)))
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val dataWrite = Wire(Vec(p.iCacheWays, Vec(lineInsts, UInt(32.W))))
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val validWrite = Wire(Vec(p.iCacheWays, Vec(lineInsts, Bool())))
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tagWrite := missTagRow
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dataWrite := missDataRow
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validWrite := missValidRow
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tagWrite(missWay) := tag(missAddr)
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when(!missRefillExisting) {
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for (i <- 0 until lineInsts) {
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validWrite(missWay)(i) := false.B
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}
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}
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dataWrite(missWay)(missInst) := io.memRespBits(0)
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validWrite(missWay)(missInst) := true.B
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when(missCanFetchPair) {
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dataWrite(missWay)(missInst + 1.U) := io.memRespBits(1)
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validWrite(missWay)(missInst + 1.U) := true.B
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}
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valid(missSet) := validWrite
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tags.write(missSet, tagWrite)
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data.write(missSet, dataWrite)
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when(!missRefillExisting) {
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repl(missSet) := missWay + 1.U
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}
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when(io.respReady) {
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state := sIdle
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}.otherwise {
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respReg := missResp
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state := sResp
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}
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}
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}
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}
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