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fix: resolve OoO simulation timeout

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This commit is contained in:
abnerhexu
2026-06-27 03:38:34 +00:00
parent 502803c37f
commit a2e0126199
68 changed files with 78250 additions and 210 deletions
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34
src/main/scala/csr/CSRFile.scala
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@@ -4,6 +4,7 @@ import chisel3.util._
class CSRFile(p: CoreParams = CoreParams()) extends Module {
val io = IO(new Bundle {
val cmd = Input(new CsrCommand(p))
val readAddr = Input(UInt(12.W))
val rdata = Output(UInt(p.xlen.W))
val trap = Input(Bool())
val trapPc = Input(UInt(p.xlen.W))
@@ -39,7 +40,7 @@ class CSRFile(p: CoreParams = CoreParams()) extends Module {
io.mepc := mepcReg
val r = WireDefault(0.U(p.xlen.W))
switch(io.cmd.addr) {
switch(io.readAddr) {
is("h300".U) { r := mstatus }
is("h301".U) { r := misa }
is("h302".U) { r := medeleg }
@@ -64,11 +65,36 @@ class CSRFile(p: CoreParams = CoreParams()) extends Module {
}
io.rdata := r
val writeOld = WireDefault(0.U(p.xlen.W))
switch(io.cmd.addr) {
is("h300".U) { writeOld := mstatus }
is("h301".U) { writeOld := misa }
is("h302".U) { writeOld := medeleg }
is("h303".U) { writeOld := mideleg }
is("h304".U) { writeOld := mie }
is("h305".U) { writeOld := mtvecReg }
is("h341".U) { writeOld := mepcReg }
is("h342".U) { writeOld := mcause }
is("h343".U) { writeOld := mtval }
is("h344".U) { writeOld := mip }
is("h100".U) { writeOld := sstatus }
is("h105".U) { writeOld := stvec }
is("h140".U) { writeOld := sscratch }
is("h141".U) { writeOld := sepc }
is("h142".U) { writeOld := scause }
is("h143".U) { writeOld := stval }
is("h180".U) { writeOld := satpReg }
is("hf14".U) { writeOld := 0.U }
is("hc00".U) { writeOld := cycle }
is("hc01".U) { writeOld := 0.U }
is("hc02".U) { writeOld := instret }
}
val operand = Mux(io.cmd.cmd(2), io.cmd.zimm, io.cmd.rs1)
val next = MuxLookup(io.cmd.cmd(1, 0), r)(Seq(
val next = MuxLookup(io.cmd.cmd(1, 0), writeOld)(Seq(
1.U -> operand,
2.U -> (r | operand),
3.U -> (r & ~operand)
2.U -> (writeOld | operand),
3.U -> (writeOld & ~operand)
))
when(io.cmd.valid && io.cmd.cmd =/= 0.U) {