fix: resolve OoO simulation timeout
This commit is contained in:
abnerhexu
282
src/main/scala/OoOBackend.scala
Normal file
282
src/main/scala/OoOBackend.scala
Normal file
@@ -0,0 +1,282 @@
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import chisel3._
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import chisel3.util._
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import _root_.circt.stage.ChiselStage
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class OoOBackend(p: CoreParams = CoreParams()) extends Module {
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private val physBits = log2Ceil(p.physRegs)
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private val robBits = log2Ceil(p.robEntries)
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val io = IO(new Bundle {
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val decodeValid = Input(Vec(p.issueWidth, Bool()))
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val decode = Input(Vec(p.issueWidth, new DecodedInst(p)))
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val decodeReady = Output(Bool())
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val commitValid = Output(Vec(p.issueWidth, Bool()))
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val commitEntry = Output(Vec(p.issueWidth, new RobEntry(p)))
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val flush = Output(Bool())
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val redirectPc = Output(UInt(p.xlen.W))
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val dmemReqValid = Output(Bool())
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val dmemReq = Output(new MemRequest(p))
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val dmemRespValid = Input(Bool())
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val dmemRespData = Input(UInt(p.xlen.W))
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val satp = Input(UInt(p.xlen.W))
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})
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val rename = Module(new RenameStage(p))
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val issue = Module(new IssueStage(p))
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val prf = Module(new PhysicalRegFile(p))
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val exec = Seq.fill(p.issueWidth)(Module(new ExecStage(p)))
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val wb = Seq.fill(p.issueWidth)(Module(new WriteBackStage(p)))
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val commit = Module(new CommitStage(p))
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val lq = Module(new LoadQueue(p))
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val sq = Module(new StoreQueue(p))
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val lsu = Module(new LSU(p))
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val csr = Module(new CSRFile(p))
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val completeValid = Wire(Vec(p.issueWidth, Bool()))
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val completeIdx = Wire(Vec(p.issueWidth, UInt(robBits.W)))
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val completeException = Wire(Vec(p.issueWidth, Bool()))
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val completeCause = Wire(Vec(p.issueWidth, UInt(p.xlen.W)))
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val completeBadAddr = Wire(Vec(p.issueWidth, UInt(p.xlen.W)))
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val completeMispredict = Wire(Vec(p.issueWidth, Bool()))
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val completeRedirectPc = Wire(Vec(p.issueWidth, UInt(p.xlen.W)))
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val completeCsrValid = Wire(Vec(p.issueWidth, Bool()))
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val completeCsrAddr = Wire(Vec(p.issueWidth, UInt(12.W)))
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val completeCsrCmd = Wire(Vec(p.issueWidth, UInt(3.W)))
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val completeCsrRs1 = Wire(Vec(p.issueWidth, UInt(p.xlen.W)))
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val completeCsrZimm = Wire(Vec(p.issueWidth, UInt(5.W)))
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val wakeup = Wire(Vec(p.issueWidth, new Wakeup(p)))
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val wakeupReg = RegInit(VecInit(Seq.fill(p.issueWidth)(0.U.asTypeOf(new Wakeup(p)))))
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val csrRData = Wire(Vec(p.issueWidth, UInt(p.xlen.W)))
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rename.io.inValid := VecInit((0 until p.issueWidth).map(i => io.decodeValid(i) && issue.io.inReady(i)))
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rename.io.in := io.decode
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rename.io.wbValid := VecInit(wb.map(_.io.wen))
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rename.io.wbPhys := VecInit(wb.map(_.io.waddr))
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rename.io.completeValid := completeValid
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rename.io.completeIdx := completeIdx
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rename.io.completeException := completeException
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rename.io.completeCause := completeCause
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rename.io.completeBadAddr := completeBadAddr
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rename.io.completeMispredict := completeMispredict
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rename.io.completeRedirectPc := completeRedirectPc
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rename.io.completeCsrValid := completeCsrValid
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rename.io.completeCsrAddr := completeCsrAddr
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rename.io.completeCsrCmd := completeCsrCmd
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rename.io.completeCsrRs1 := completeCsrRs1
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rename.io.completeCsrZimm := completeCsrZimm
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rename.io.commitReady := commit.io.commitReady
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rename.io.commitMapValid := commit.io.commitMapValid
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rename.io.commitArch := commit.io.commitArch
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rename.io.commitPhys := commit.io.commitPhys
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rename.io.commitFreeOld := commit.io.freeOldPhys
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rename.io.commitOldPhys := commit.io.oldPhys
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rename.io.flush := commit.io.flush
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issue.io.inValid := rename.io.outValid
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issue.io.in := rename.io.out
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issue.io.wakeup := wakeupReg
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val loadPending = RegInit(false.B)
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val loadPendingRob = Reg(UInt(robBits.W))
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val loadPendingPhys = Reg(UInt(physBits.W))
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val loadPendingLq = Reg(UInt(log2Ceil(p.loadQueueEntries).W))
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val loadRespValid = lsu.io.respValid && loadPending
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val memIssue = Wire(Vec(p.issueWidth, Bool()))
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for (i <- 0 until p.issueWidth) {
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memIssue(i) := issue.io.outValid(i) && (issue.io.out(i).decoded.isLoad || issue.io.out(i).decoded.isStore)
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}
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val csrReadReq = Wire(Vec(p.issueWidth, Bool()))
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for (i <- 0 until p.issueWidth) {
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val decoded = issue.io.out(i).decoded
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csrReadReq(i) := issue.io.outValid(i) && decoded.isSystem && decoded.funct3 =/= 0.U
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}
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val stallSecondCsrRead = csrReadReq(0) && csrReadReq(1)
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val memSlot0 = memIssue(0)
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val memSlot1 = !memSlot0 && memIssue(1)
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val memSlot = Mux(memSlot0, 0.U, 1.U)
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val canIssueMem = !loadPending
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val issue_io_outReady_0 = Wire(Bool())
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val issue_io_outReady_1 = Wire(Bool())
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dontTouch(issue_io_outReady_0)
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dontTouch(issue_io_outReady_1)
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val isMem0 = issue.io.out(0).decoded.isLoad || issue.io.out(0).decoded.isStore
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val isMem1 = issue.io.out(1).decoded.isLoad || issue.io.out(1).decoded.isStore
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val memReady0 = !isMem0 || (lsu.io.reqReady && canIssueMem)
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val memReady1 = !isMem1 || (lsu.io.reqReady && canIssueMem && !memSlot0)
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issue_io_outReady_0 := memReady0
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issue_io_outReady_1 := memReady1 && !stallSecondCsrRead
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issue.io.outReady := VecInit(Seq(issue_io_outReady_0, issue_io_outReady_1))
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val issueFire = Wire(Vec(p.issueWidth, Bool()))
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for (i <- 0 until p.issueWidth) {
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issueFire(i) := issue.io.outValid(i) && issue.io.outReady(i)
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}
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issue.io.flush := commit.io.flush
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io.decodeReady := rename.io.canAccept && issue.io.inReady.asUInt.andR
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val memDecoded = issue.io.out(memSlot).decoded
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val memSrc1 = Mux(memSlot0, prf.io.rdata(0), prf.io.rdata(2))
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val memSrc2 = Mux(memSlot0, prf.io.rdata(1), prf.io.rdata(3))
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val memAddr = memSrc1 + Mux(memDecoded.isStore, memDecoded.immS, memDecoded.immI)
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val loadEnq = (memSlot0 || memSlot1) && memDecoded.isLoad && issue.io.outReady(memSlot)
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val storeEnq = (memSlot0 || memSlot1) && memDecoded.isStore && issue.io.outReady(memSlot)
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val lsuLoadReq = loadEnq && !sq.io.forwardValid
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lq.io.enqValid := loadEnq
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lq.io.enqRobIdx := issue.io.out(memSlot).robIdx
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lq.io.addrValid := loadEnq
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lq.io.addrIdx := lq.io.enqIdx
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lq.io.addr := memAddr
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lq.io.size := memDecoded.memWidth
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lq.io.complete := loadRespValid
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lq.io.completeIdx := loadPendingLq
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lq.io.storeAddrValid := storeEnq
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lq.io.storeRobIdx := issue.io.out(memSlot).robIdx
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lq.io.storeAddr := memAddr
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lq.io.storeSize := memDecoded.memWidth
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lq.io.flush := commit.io.flush
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sq.io.enqValid := storeEnq
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sq.io.enqRobIdx := issue.io.out(memSlot).robIdx
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sq.io.writeAddr := storeEnq
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sq.io.writeData := storeEnq
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sq.io.writeIdx := sq.io.enqIdx
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sq.io.addr := memAddr
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sq.io.data := memSrc2
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sq.io.size := memDecoded.memWidth
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sq.io.loadAddr := memAddr
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sq.io.loadSize := memDecoded.memWidth
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sq.io.loadRobIdx := issue.io.out(memSlot).robIdx
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val commitStore0 = commit.io.commitReady(0) && rename.io.commitValid(0) &&
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rename.io.commitEntry(0).opClass === Consts.OP_STORE
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val commitStore1 = commit.io.commitReady(1) && rename.io.commitValid(1) &&
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rename.io.commitEntry(1).opClass === Consts.OP_STORE
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sq.io.commitValid := commitStore0 || commitStore1
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sq.io.commitRobIdx := Mux(commitStore0, rename.io.commitEntry(0).robIdx, rename.io.commitEntry(1).robIdx)
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sq.io.drainReady := !lsuLoadReq && lsu.io.reqReady
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sq.io.flush := commit.io.flush
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lsu.io.reqValid := lsuLoadReq || sq.io.drainValid
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lsu.io.req := Mux(sq.io.drainValid, sq.io.drain, 0.U.asTypeOf(new MemRequest(p)))
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when(lsuLoadReq) {
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lsu.io.req.addr := memAddr
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lsu.io.req.data := 0.U
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lsu.io.req.isStore := false.B
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lsu.io.req.size := memDecoded.memWidth
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}
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lsu.io.dmemRespValid := io.dmemRespValid
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lsu.io.dmemRespData := io.dmemRespData
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lsu.io.satp := csr.io.satp
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io.dmemReqValid := lsu.io.dmemReqValid
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io.dmemReq := lsu.io.dmemReq
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val csrReadFire = VecInit((0 until p.issueWidth).map(i => csrReadReq(i) && issue.io.outReady(i)))
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csr.io.readAddr := Mux(csrReadFire(0), issue.io.out(0).decoded.inst(31, 20), issue.io.out(1).decoded.inst(31, 20))
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csrRData(0) := csr.io.rdata
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csrRData(1) := csr.io.rdata
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csr.io.trap := commit.io.flush && commit.io.exception
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csr.io.trapPc := commit.io.badAddr
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csr.io.trapCause := commit.io.exceptionCause
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val commitCsr0 = commit.io.commitReady(0) && rename.io.commitValid(0) && rename.io.commitEntry(0).csrValid
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val commitCsr1 = commit.io.commitReady(1) && rename.io.commitValid(1) && rename.io.commitEntry(1).csrValid
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val commitCsrEntry = Mux(commitCsr0, rename.io.commitEntry(0), rename.io.commitEntry(1))
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csr.io.cmd.valid := commitCsr0 || commitCsr1
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csr.io.cmd.addr := commitCsrEntry.csrAddr
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csr.io.cmd.cmd := commitCsrEntry.csrCmd
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csr.io.cmd.rs1 := commitCsrEntry.csrRs1
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csr.io.cmd.zimm := commitCsrEntry.csrZimm
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when(commit.io.flush) {
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loadPending := false.B
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}.elsewhen(loadEnq && !sq.io.forwardValid) {
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loadPending := true.B
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loadPendingRob := issue.io.out(memSlot).robIdx
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loadPendingPhys := issue.io.out(memSlot).prd
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loadPendingLq := lq.io.enqIdx
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}.elsewhen(loadRespValid) {
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loadPending := false.B
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}
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for (i <- 0 until p.issueWidth) {
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prf.io.raddr(2 * i) := issue.io.out(i).prs1
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prf.io.raddr(2 * i + 1) := issue.io.out(i).prs2
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}
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for (i <- 0 until p.issueWidth) {
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val decoded = issue.io.out(i).decoded
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val src1 = prf.io.rdata(2 * i)
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val rs2Val = prf.io.rdata(2 * i + 1)
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val src2 = Mux(decoded.isOpImm || decoded.isLoad || decoded.isJalr, decoded.immI, rs2Val)
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exec(i).io.inValid := issueFire(i)
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exec(i).io.in := decoded
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exec(i).io.src1 := src1
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exec(i).io.src2 := src2
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val isLoadRespSlot = i.U === 0.U && loadRespValid
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val useExecWb = exec(i).io.outValid && decoded.writesRd && !decoded.isLoad
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wb(i).io.valid := useExecWb || isLoadRespSlot
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wb(i).io.physDest := Mux(isLoadRespSlot, loadPendingPhys, issue.io.out(i).prd)
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wb(i).io.data := Mux(isLoadRespSlot, lsu.io.respData, Mux(decoded.isLui, decoded.immU,
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Mux(decoded.isAuipc, decoded.pc + decoded.immU,
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Mux(decoded.isJal || decoded.isJalr, decoded.pc + 4.U,
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Mux(decoded.isSystem && decoded.funct3 =/= 0.U, csrRData(i), exec(i).io.result)))))
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prf.io.wen(i) := wb(i).io.wen
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prf.io.waddr(i) := wb(i).io.waddr
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prf.io.wdata(i) := wb(i).io.wdata
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wakeup(i).valid := wb(i).io.wen
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wakeup(i).phys := wb(i).io.waddr
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wakeup(i).data := wb(i).io.wdata
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val branchTarget = decoded.pc + decoded.immB
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val jalTarget = decoded.pc + decoded.immJ
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val jalrTarget = (src1 + decoded.immI) & (~1.U(p.xlen.W))
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val branchRedirect = Mux(decoded.isJal, jalTarget,
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Mux(decoded.isJalr, jalrTarget,
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Mux(decoded.isBranch && exec(i).io.branchTaken, branchTarget, decoded.pc + 4.U)))
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val isEcall = decoded.inst === "h00000073".U
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val isEbreak = decoded.inst === "h00100073".U
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val isMret = decoded.inst === "h30200073".U
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val completeLoadResp = i.U === 0.U && loadRespValid
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completeValid(i) := (issueFire(i) && !decoded.isLoad) || completeLoadResp
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completeIdx(i) := Mux(completeLoadResp, loadPendingRob, issue.io.out(i).robIdx)
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completeException(i) := (issueFire(i) && (decoded.illegal || isEcall || isEbreak || lq.io.violation)) ||
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(completeLoadResp && lsu.io.pageFault)
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completeCause(i) := Mux(completeLoadResp && lsu.io.pageFault, 13.U,
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Mux(issueFire(i) && isEbreak, 3.U,
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Mux(issueFire(i) && isEcall, 11.U,
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Mux(issueFire(i) && decoded.illegal, 2.U, 0.U))))
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completeBadAddr(i) := decoded.pc
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completeMispredict(i) := issueFire(i) &&
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(decoded.isJal || decoded.isJalr || isMret || (decoded.isBranch && exec(i).io.branchTaken))
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completeRedirectPc(i) := Mux(isEcall || isEbreak, csr.io.mtvec, Mux(isMret, csr.io.mepc, branchRedirect))
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completeCsrValid(i) := issueFire(i) && decoded.isSystem && decoded.funct3 =/= 0.U &&
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!(decoded.funct3(1) && decoded.rs1 === 0.U)
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completeCsrAddr(i) := decoded.inst(31, 20)
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completeCsrCmd(i) := decoded.funct3
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completeCsrRs1(i) := src1
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completeCsrZimm(i) := decoded.rs1
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}
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wakeupReg := wakeup
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commit.io.robValid := rename.io.commitValid
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commit.io.robEntry := rename.io.commitEntry
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io.commitValid := VecInit((0 until p.issueWidth).map(i => rename.io.commitValid(i) && commit.io.commitReady(i)))
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io.commitEntry := rename.io.commitEntry
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io.flush := commit.io.flush
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io.redirectPc := Mux(commit.io.exception, csr.io.mtvec, commit.io.redirectPc)
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}
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object OoOBackend extends App {
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ChiselStage.emitSystemVerilogFile(
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new OoOBackend(),
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args = Array("--target-dir", "generated"),
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firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
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)
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}
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Reference in New Issue
Block a user