fix: resolve OoO simulation timeout

src/main/scala/Core.scala

@@ -19,6 +19,47 @@ class Core(p: CoreParams = CoreParams()) extends Module {
     val dmem_resp_bits = Input(UInt(p.xlen.W))
   })
 
+  if (p.useOoOBackend) {
+    val frontend = Module(new Frontend(p))
+    val id = Module(new IDStage(p))
+    val backend = Module(new OoOBackend(p))
+
+    frontend.io.redirectValid := backend.io.flush
+    frontend.io.redirectPc := backend.io.redirectPc
+    frontend.io.imemRespValid := io.imem_resp_valid
+    frontend.io.imemRespBits(0) := io.imem_resp_bits_0
+    frontend.io.imemRespBits(1) := io.imem_resp_bits_1
+    frontend.io.branchUpdate := 0.U.asTypeOf(new BranchUpdate(p))
+
+    val fetchValid = RegInit(false.B)
+    val fetchReg = Reg(new FetchPacket(p))
+    val fetchReady = !fetchValid || backend.io.decodeReady
+    frontend.io.outReady := fetchReady
+    when(backend.io.flush) {
+      fetchValid := false.B
+    }.elsewhen(fetchReady) {
+      fetchValid := frontend.io.outValid
+      fetchReg := frontend.io.out
+    }
+
+    id.io.inValid := fetchValid
+    id.io.in := fetchReg
+
+    backend.io.decodeValid := id.io.outValid
+    backend.io.decode := id.io.out
+    backend.io.dmemRespValid := io.dmem_resp_valid
+    backend.io.dmemRespData := io.dmem_resp_bits
+    backend.io.satp := 0.U
+
+    io.imem_req_valid := frontend.io.imemReqValid
+    io.imem_req_bits := frontend.io.imemReqAddr
+    io.dmem_req_valid := backend.io.dmemReqValid
+    io.dmem_req_bits_addr := backend.io.dmemReq.addr
+    io.dmem_req_bits_data := backend.io.dmemReq.data
+    io.dmem_req_bits_isStore := backend.io.dmemReq.isStore
+    io.dmem_req_bits_size := backend.io.dmemReq.size
+  } else {
+
   val sFetch :: sExec :: sLoadWait :: Nil = Enum(3)
   val state = RegInit(sFetch)
   val pc = RegInit(Consts.ResetVector)
@@ -67,6 +108,7 @@ class Core(p: CoreParams = CoreParams()) extends Module {
   csr.io.cmd.cmd := dec.funct3
   csr.io.cmd.rs1 := src1
   csr.io.cmd.zimm := dec.rs1
+  csr.io.readAddr := instReg(31, 20)
   val isEcall = instReg === "h00000073".U
   val isEbreak = instReg === "h00100073".U
   val isMret = instReg === "h30200073".U
@@ -162,6 +204,7 @@ class Core(p: CoreParams = CoreParams()) extends Module {
     }
   }
 
+  }
 }
 
 object Core extends App {
@@ -171,3 +214,11 @@ object Core extends App {
     firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
   )
 }
+
+object CoreOoO extends App {
+  ChiselStage.emitSystemVerilogFile(
+    new Core(CoreParams(useOoOBackend = true)),
+    args = Array("--target-dir", "generated-ooo"),
+    firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
+  )
+}