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fix: resolve OoO simulation timeout

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This commit is contained in:
abnerhexu
2026-06-27 03:38:34 +00:00
parent 502803c37f
commit a2e0126199
68 changed files with 78250 additions and 210 deletions
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38
generated-ooo/verification/OoOBackend_Verification.sv Normal file
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// Generated by CIRCT firtool-1.139.0
// Users can define 'PRINTF_COND' to add an extra gate to prints.
`ifndef PRINTF_COND_
`ifdef PRINTF_COND
`define PRINTF_COND_ (`PRINTF_COND)
`else // PRINTF_COND
`define PRINTF_COND_ 1
`endif // PRINTF_COND
`endif // not def PRINTF_COND_
module OoOBackend_Verification();
`ifndef SYNTHESIS
always @(posedge OoOBackend.clock) begin
automatic logic [63:0] _GEN;
_GEN =
OoOBackend.memSlot
? OoOBackend.issue_io_out_1_decoded_pc
: OoOBackend.issue_io_out_0_decoded_pc;
if ((`PRINTF_COND_) & OoOBackend._storeEnq_T & _GEN < 64'h80000050
& ~OoOBackend.reset)
$fwrite(32'h80000002,
"[mem-issue] pc=0x%x inst=0x%x isLoad=%d isStore=%d prs1=%d src1=0x%x immS=0x%x addr=0x%x ready=%d\n",
_GEN,
OoOBackend.memSlot
? OoOBackend.issue_io_out_1_decoded_inst
: OoOBackend.issue_io_out_0_decoded_inst, OoOBackend._layer_probe_0,
OoOBackend._layer_probe_1,
OoOBackend.memSlot
? OoOBackend.issue_io_out_1_prs1
: OoOBackend.issue_io_out_0_prs1, OoOBackend.memSrc1,
OoOBackend._layer_probe, OoOBackend.memAddr,
OoOBackend.memSlot
? OoOBackend.issue_io_outReady_1
: OoOBackend.issue_io_outReady_0);
end // always @(posedge)
`endif // not def SYNTHESIS
endmodule

32
generated-ooo/verification/RenameStage_Verification.sv Normal file
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// Generated by CIRCT firtool-1.139.0
// Users can define 'PRINTF_COND' to add an extra gate to prints.
`ifndef PRINTF_COND_
`ifdef PRINTF_COND
`define PRINTF_COND_ (`PRINTF_COND)
`else // PRINTF_COND
`define PRINTF_COND_ 1
`endif // PRINTF_COND
`endif // not def PRINTF_COND_
module RenameStage_Verification();
`ifndef SYNTHESIS
always @(posedge RenameStage.clock) begin
if ((`PRINTF_COND_) & RenameStage.io_outValid_0_0
& RenameStage.io_in_0_pc < 64'h80000050 & ~RenameStage.reset)
$fwrite(32'h80000002,
"[rename] pc=0x%x inst=0x%x rs1=%d prs1=%d src1Ready=%d src1FromOlder=%d rd=%d prd=%d\n",
RenameStage.io_in_0_pc, RenameStage.io_in_0_inst, RenameStage.io_in_0_rs1,
RenameStage.table_io_prs1_0, RenameStage.io_out_0_src1Ready_0, 1'h0,
RenameStage.io_in_0_rd, RenameStage.io_out_0_prd_0);
if ((`PRINTF_COND_) & RenameStage.io_outValid_1_0
& RenameStage.io_in_1_pc < 64'h80000050 & ~RenameStage.reset)
$fwrite(32'h80000002,
"[rename] pc=0x%x inst=0x%x rs1=%d prs1=%d src1Ready=%d src1FromOlder=%d rd=%d prd=%d\n",
RenameStage.io_in_1_pc, RenameStage.io_in_1_inst, RenameStage.io_in_1_rs1,
RenameStage.table_io_prs1_1, RenameStage.io_out_1_src1Ready_0,
RenameStage.src1FromOlder, RenameStage.io_in_1_rd,
RenameStage.io_out_1_prd_0);
end // always @(posedge)
`endif // not def SYNTHESIS
endmodule

5
generated-ooo/verification/assert/layers-Core-Verification-Assert.sv Normal file
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@@ -0,0 +1,5 @@
// Generated by CIRCT firtool-1.139.0
`ifndef layers_Core_Verification_Assert
`define layers_Core_Verification_Assert
`include "layers-Core-Verification.sv"
`endif // not def layers_Core_Verification_Assert

5
generated-ooo/verification/assume/layers-Core-Verification-Assume.sv Normal file
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@@ -0,0 +1,5 @@
// Generated by CIRCT firtool-1.139.0
`ifndef layers_Core_Verification_Assume
`define layers_Core_Verification_Assume
`include "layers-Core-Verification.sv"
`endif // not def layers_Core_Verification_Assume

5
generated-ooo/verification/cover/layers-Core-Verification-Cover.sv Normal file
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@@ -0,0 +1,5 @@
// Generated by CIRCT firtool-1.139.0
`ifndef layers_Core_Verification_Cover
`define layers_Core_Verification_Cover
`include "layers-Core-Verification.sv"
`endif // not def layers_Core_Verification_Cover

4
generated-ooo/verification/layers-Core-Verification.sv Normal file
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@@ -0,0 +1,4 @@
// Generated by CIRCT firtool-1.139.0
`ifndef layers_Core_Verification
`define layers_Core_Verification
`endif // not def layers_Core_Verification

6
generated-ooo/verification/layers-OoOBackend-Verification.sv Normal file
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@@ -0,0 +1,6 @@
// Generated by CIRCT firtool-1.139.0
`ifndef layers_OoOBackend_Verification
`define layers_OoOBackend_Verification
`include "layers-RenameStage-Verification.sv"
bind OoOBackend OoOBackend_Verification verification ();
`endif // not def layers_OoOBackend_Verification

5
generated-ooo/verification/layers-RenameStage-Verification.sv Normal file
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@@ -0,0 +1,5 @@
// Generated by CIRCT firtool-1.139.0
`ifndef layers_RenameStage_Verification
`define layers_RenameStage_Verification
bind RenameStage RenameStage_Verification verification ();
`endif // not def layers_RenameStage_Verification