fix: resolve OoO simulation timeout
This commit is contained in:
abnerhexu
961
generated-ooo/StoreQueue.sv
Normal file
961
generated-ooo/StoreQueue.sv
Normal file
@@ -0,0 +1,961 @@
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// Generated by CIRCT firtool-1.139.0
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module StoreQueue(
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input clock,
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reset,
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io_enqValid,
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input [5:0] io_enqRobIdx,
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output [3:0] io_enqIdx,
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input io_writeAddr,
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io_writeData,
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input [3:0] io_writeIdx,
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input [63:0] io_addr,
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io_data,
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input [2:0] io_size,
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input [63:0] io_loadAddr,
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input [5:0] io_loadRobIdx,
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output io_forwardValid,
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input io_commitValid,
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input [5:0] io_commitRobIdx,
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output io_drainValid,
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output [63:0] io_drain_addr,
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io_drain_data,
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output [2:0] io_drain_size,
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input io_drainReady,
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io_flush
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);
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reg entries_0_valid;
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reg [5:0] entries_0_robIdx;
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reg entries_0_addrValid;
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reg entries_0_dataValid;
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reg [63:0] entries_0_addr;
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reg [63:0] entries_0_data;
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reg [2:0] entries_0_size;
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reg entries_0_committed;
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reg entries_1_valid;
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reg [5:0] entries_1_robIdx;
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reg entries_1_addrValid;
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reg entries_1_dataValid;
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reg [63:0] entries_1_addr;
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reg [63:0] entries_1_data;
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reg [2:0] entries_1_size;
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reg entries_1_committed;
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reg entries_2_valid;
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reg [5:0] entries_2_robIdx;
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reg entries_2_addrValid;
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reg entries_2_dataValid;
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reg [63:0] entries_2_addr;
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reg [63:0] entries_2_data;
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reg [2:0] entries_2_size;
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reg entries_2_committed;
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reg entries_3_valid;
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reg [5:0] entries_3_robIdx;
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reg entries_3_addrValid;
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reg entries_3_dataValid;
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reg [63:0] entries_3_addr;
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reg [63:0] entries_3_data;
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reg [2:0] entries_3_size;
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reg entries_3_committed;
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reg entries_4_valid;
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reg [5:0] entries_4_robIdx;
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reg entries_4_addrValid;
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reg entries_4_dataValid;
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reg [63:0] entries_4_addr;
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reg [63:0] entries_4_data;
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reg [2:0] entries_4_size;
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reg entries_4_committed;
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reg entries_5_valid;
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reg [5:0] entries_5_robIdx;
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reg entries_5_addrValid;
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reg entries_5_dataValid;
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reg [63:0] entries_5_addr;
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reg [63:0] entries_5_data;
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reg [2:0] entries_5_size;
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reg entries_5_committed;
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reg entries_6_valid;
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reg [5:0] entries_6_robIdx;
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reg entries_6_addrValid;
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reg entries_6_dataValid;
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reg [63:0] entries_6_addr;
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reg [63:0] entries_6_data;
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reg [2:0] entries_6_size;
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reg entries_6_committed;
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reg entries_7_valid;
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reg [5:0] entries_7_robIdx;
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reg entries_7_addrValid;
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reg entries_7_dataValid;
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reg [63:0] entries_7_addr;
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reg [63:0] entries_7_data;
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reg [2:0] entries_7_size;
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reg entries_7_committed;
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reg entries_8_valid;
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reg [5:0] entries_8_robIdx;
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reg entries_8_addrValid;
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reg entries_8_dataValid;
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reg [63:0] entries_8_addr;
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reg [63:0] entries_8_data;
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reg [2:0] entries_8_size;
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reg entries_8_committed;
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reg entries_9_valid;
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reg [5:0] entries_9_robIdx;
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reg entries_9_addrValid;
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reg entries_9_dataValid;
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reg [63:0] entries_9_addr;
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reg [63:0] entries_9_data;
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reg [2:0] entries_9_size;
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reg entries_9_committed;
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reg entries_10_valid;
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reg [5:0] entries_10_robIdx;
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reg entries_10_addrValid;
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reg entries_10_dataValid;
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reg [63:0] entries_10_addr;
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reg [63:0] entries_10_data;
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reg [2:0] entries_10_size;
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reg entries_10_committed;
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reg entries_11_valid;
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reg [5:0] entries_11_robIdx;
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reg entries_11_addrValid;
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reg entries_11_dataValid;
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reg [63:0] entries_11_addr;
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reg [63:0] entries_11_data;
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reg [2:0] entries_11_size;
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reg entries_11_committed;
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reg entries_12_valid;
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reg [5:0] entries_12_robIdx;
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reg entries_12_addrValid;
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reg entries_12_dataValid;
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reg [63:0] entries_12_addr;
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reg [63:0] entries_12_data;
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reg [2:0] entries_12_size;
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reg entries_12_committed;
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reg entries_13_valid;
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reg [5:0] entries_13_robIdx;
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reg entries_13_addrValid;
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reg entries_13_dataValid;
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reg [63:0] entries_13_addr;
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reg [63:0] entries_13_data;
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reg [2:0] entries_13_size;
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reg entries_13_committed;
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reg entries_14_valid;
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reg [5:0] entries_14_robIdx;
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reg entries_14_addrValid;
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reg entries_14_dataValid;
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reg [63:0] entries_14_addr;
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reg [63:0] entries_14_data;
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reg [2:0] entries_14_size;
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reg entries_14_committed;
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reg entries_15_valid;
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reg [5:0] entries_15_robIdx;
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reg entries_15_addrValid;
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reg entries_15_dataValid;
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reg [63:0] entries_15_addr;
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reg [63:0] entries_15_data;
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reg [2:0] entries_15_size;
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reg entries_15_committed;
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wire [14:0] enqOH =
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entries_0_valid
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? (entries_1_valid
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? (entries_2_valid
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? (entries_3_valid
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? (entries_4_valid
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? (entries_5_valid
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? (entries_6_valid
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? (entries_7_valid
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? (entries_8_valid
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? (entries_9_valid
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? (entries_10_valid
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? (entries_11_valid
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? (entries_12_valid
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? (entries_13_valid
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? (entries_14_valid
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? {~entries_15_valid,
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14'h0}
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: 15'h2000)
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: 15'h1000)
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: 15'h800)
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: 15'h400)
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: 15'h200)
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: 15'h100)
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: 15'h80)
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: 15'h40)
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: 15'h20)
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: 15'h10)
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: 15'h8)
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: 15'h4)
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: 15'h2)
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: 15'h1)
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: 15'h0;
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wire [6:0] _enqIdx_T_1 = enqOH[14:8] | enqOH[6:0];
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wire [2:0] _enqIdx_T_3 = _enqIdx_T_1[6:4] | _enqIdx_T_1[2:0];
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wire [3:0] enqIdx =
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{|(enqOH[14:7]),
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|(_enqIdx_T_1[6:3]),
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|(_enqIdx_T_3[2:1]),
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_enqIdx_T_3[2] | _enqIdx_T_3[0]};
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wire drainVec_0 =
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entries_0_valid & entries_0_committed & entries_0_addrValid & entries_0_dataValid;
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wire drainVec_1 =
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entries_1_valid & entries_1_committed & entries_1_addrValid & entries_1_dataValid;
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wire drainVec_2 =
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entries_2_valid & entries_2_committed & entries_2_addrValid & entries_2_dataValid;
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wire drainVec_3 =
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entries_3_valid & entries_3_committed & entries_3_addrValid & entries_3_dataValid;
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wire drainVec_4 =
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entries_4_valid & entries_4_committed & entries_4_addrValid & entries_4_dataValid;
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wire drainVec_5 =
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entries_5_valid & entries_5_committed & entries_5_addrValid & entries_5_dataValid;
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wire drainVec_6 =
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entries_6_valid & entries_6_committed & entries_6_addrValid & entries_6_dataValid;
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wire drainVec_7 =
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entries_7_valid & entries_7_committed & entries_7_addrValid & entries_7_dataValid;
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wire drainVec_8 =
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entries_8_valid & entries_8_committed & entries_8_addrValid & entries_8_dataValid;
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wire drainVec_9 =
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entries_9_valid & entries_9_committed & entries_9_addrValid & entries_9_dataValid;
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wire drainVec_10 =
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entries_10_valid & entries_10_committed & entries_10_addrValid & entries_10_dataValid;
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wire drainVec_11 =
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entries_11_valid & entries_11_committed & entries_11_addrValid & entries_11_dataValid;
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wire drainVec_12 =
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entries_12_valid & entries_12_committed & entries_12_addrValid & entries_12_dataValid;
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wire drainVec_13 =
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entries_13_valid & entries_13_committed & entries_13_addrValid & entries_13_dataValid;
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wire drainVec_14 =
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entries_14_valid & entries_14_committed & entries_14_addrValid & entries_14_dataValid;
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wire drainVec_15 =
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entries_15_valid & entries_15_committed & entries_15_addrValid & entries_15_dataValid;
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wire [15:0] _io_drainValid_T =
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{drainVec_15,
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drainVec_14,
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drainVec_13,
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drainVec_12,
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drainVec_11,
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drainVec_10,
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drainVec_9,
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drainVec_8,
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drainVec_7,
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drainVec_6,
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drainVec_5,
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drainVec_4,
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drainVec_3,
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drainVec_2,
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drainVec_1,
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drainVec_0};
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wire [14:0] drainOH =
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drainVec_0
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? 15'h0
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: drainVec_1
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? 15'h1
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: drainVec_2
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? 15'h2
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: drainVec_3
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? 15'h4
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: drainVec_4
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? 15'h8
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: drainVec_5
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? 15'h10
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: drainVec_6
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? 15'h20
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: drainVec_7
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? 15'h40
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: drainVec_8
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? 15'h80
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: drainVec_9
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? 15'h100
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: drainVec_10
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? 15'h200
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: drainVec_11
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? 15'h400
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: drainVec_12
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? 15'h800
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: drainVec_13
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? 15'h1000
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: drainVec_14
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? 15'h2000
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: {drainVec_15, 14'h0};
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wire [6:0] _drainIdx_T_1 = drainOH[14:8] | drainOH[6:0];
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wire [2:0] _drainIdx_T_3 = _drainIdx_T_1[6:4] | _drainIdx_T_1[2:0];
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wire [3:0] drainIdx =
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{|(drainOH[14:7]),
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|(_drainIdx_T_1[6:3]),
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|(_drainIdx_T_3[2:1]),
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_drainIdx_T_3[2] | _drainIdx_T_3[0]};
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wire [15:0][63:0] _GEN =
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{{entries_15_addr},
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{entries_14_addr},
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{entries_13_addr},
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{entries_12_addr},
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{entries_11_addr},
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{entries_10_addr},
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{entries_9_addr},
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{entries_8_addr},
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{entries_7_addr},
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{entries_6_addr},
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{entries_5_addr},
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{entries_4_addr},
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{entries_3_addr},
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{entries_2_addr},
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{entries_1_addr},
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{entries_0_addr}};
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wire [15:0][63:0] _GEN_0 =
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{{entries_15_data},
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{entries_14_data},
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{entries_13_data},
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{entries_12_data},
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{entries_11_data},
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{entries_10_data},
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{entries_9_data},
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{entries_8_data},
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{entries_7_data},
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{entries_6_data},
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{entries_5_data},
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{entries_4_data},
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{entries_3_data},
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{entries_2_data},
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{entries_1_data},
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{entries_0_data}};
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wire [15:0][2:0] _GEN_1 =
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{{entries_15_size},
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{entries_14_size},
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{entries_13_size},
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{entries_12_size},
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{entries_11_size},
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{entries_10_size},
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{entries_9_size},
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{entries_8_size},
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{entries_7_size},
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{entries_6_size},
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{entries_5_size},
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{entries_4_size},
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{entries_3_size},
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{entries_2_size},
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{entries_1_size},
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{entries_0_size}};
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always @(posedge clock) begin
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if (reset) begin
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entries_0_valid <= 1'h0;
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entries_0_robIdx <= 6'h0;
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entries_0_addrValid <= 1'h0;
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entries_0_dataValid <= 1'h0;
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entries_0_addr <= 64'h0;
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entries_0_data <= 64'h0;
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entries_0_size <= 3'h0;
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entries_0_committed <= 1'h0;
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entries_1_valid <= 1'h0;
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entries_1_robIdx <= 6'h0;
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entries_1_addrValid <= 1'h0;
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entries_1_dataValid <= 1'h0;
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entries_1_addr <= 64'h0;
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entries_1_data <= 64'h0;
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entries_1_size <= 3'h0;
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entries_1_committed <= 1'h0;
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entries_2_valid <= 1'h0;
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entries_2_robIdx <= 6'h0;
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entries_2_addrValid <= 1'h0;
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entries_2_dataValid <= 1'h0;
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entries_2_addr <= 64'h0;
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entries_2_data <= 64'h0;
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entries_2_size <= 3'h0;
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entries_2_committed <= 1'h0;
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entries_3_valid <= 1'h0;
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entries_3_robIdx <= 6'h0;
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entries_3_addrValid <= 1'h0;
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entries_3_dataValid <= 1'h0;
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entries_3_addr <= 64'h0;
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entries_3_data <= 64'h0;
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entries_3_size <= 3'h0;
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entries_3_committed <= 1'h0;
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entries_4_valid <= 1'h0;
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entries_4_robIdx <= 6'h0;
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entries_4_addrValid <= 1'h0;
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entries_4_dataValid <= 1'h0;
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entries_4_addr <= 64'h0;
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entries_4_data <= 64'h0;
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entries_4_size <= 3'h0;
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entries_4_committed <= 1'h0;
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entries_5_valid <= 1'h0;
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entries_5_robIdx <= 6'h0;
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entries_5_addrValid <= 1'h0;
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entries_5_dataValid <= 1'h0;
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entries_5_addr <= 64'h0;
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entries_5_data <= 64'h0;
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entries_5_size <= 3'h0;
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entries_5_committed <= 1'h0;
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entries_6_valid <= 1'h0;
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entries_6_robIdx <= 6'h0;
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entries_6_addrValid <= 1'h0;
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entries_6_dataValid <= 1'h0;
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entries_6_addr <= 64'h0;
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entries_6_data <= 64'h0;
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entries_6_size <= 3'h0;
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entries_6_committed <= 1'h0;
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entries_7_valid <= 1'h0;
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entries_7_robIdx <= 6'h0;
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entries_7_addrValid <= 1'h0;
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entries_7_dataValid <= 1'h0;
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entries_7_addr <= 64'h0;
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entries_7_data <= 64'h0;
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entries_7_size <= 3'h0;
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entries_7_committed <= 1'h0;
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entries_8_valid <= 1'h0;
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entries_8_robIdx <= 6'h0;
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entries_8_addrValid <= 1'h0;
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entries_8_dataValid <= 1'h0;
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entries_8_addr <= 64'h0;
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entries_8_data <= 64'h0;
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entries_8_size <= 3'h0;
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entries_8_committed <= 1'h0;
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entries_9_valid <= 1'h0;
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entries_9_robIdx <= 6'h0;
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entries_9_addrValid <= 1'h0;
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entries_9_dataValid <= 1'h0;
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entries_9_addr <= 64'h0;
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entries_9_data <= 64'h0;
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entries_9_size <= 3'h0;
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entries_9_committed <= 1'h0;
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entries_10_valid <= 1'h0;
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entries_10_robIdx <= 6'h0;
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entries_10_addrValid <= 1'h0;
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entries_10_dataValid <= 1'h0;
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entries_10_addr <= 64'h0;
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entries_10_data <= 64'h0;
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entries_10_size <= 3'h0;
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entries_10_committed <= 1'h0;
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entries_11_valid <= 1'h0;
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entries_11_robIdx <= 6'h0;
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entries_11_addrValid <= 1'h0;
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entries_11_dataValid <= 1'h0;
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entries_11_addr <= 64'h0;
|
||||
entries_11_data <= 64'h0;
|
||||
entries_11_size <= 3'h0;
|
||||
entries_11_committed <= 1'h0;
|
||||
entries_12_valid <= 1'h0;
|
||||
entries_12_robIdx <= 6'h0;
|
||||
entries_12_addrValid <= 1'h0;
|
||||
entries_12_dataValid <= 1'h0;
|
||||
entries_12_addr <= 64'h0;
|
||||
entries_12_data <= 64'h0;
|
||||
entries_12_size <= 3'h0;
|
||||
entries_12_committed <= 1'h0;
|
||||
entries_13_valid <= 1'h0;
|
||||
entries_13_robIdx <= 6'h0;
|
||||
entries_13_addrValid <= 1'h0;
|
||||
entries_13_dataValid <= 1'h0;
|
||||
entries_13_addr <= 64'h0;
|
||||
entries_13_data <= 64'h0;
|
||||
entries_13_size <= 3'h0;
|
||||
entries_13_committed <= 1'h0;
|
||||
entries_14_valid <= 1'h0;
|
||||
entries_14_robIdx <= 6'h0;
|
||||
entries_14_addrValid <= 1'h0;
|
||||
entries_14_dataValid <= 1'h0;
|
||||
entries_14_addr <= 64'h0;
|
||||
entries_14_data <= 64'h0;
|
||||
entries_14_size <= 3'h0;
|
||||
entries_14_committed <= 1'h0;
|
||||
entries_15_valid <= 1'h0;
|
||||
entries_15_robIdx <= 6'h0;
|
||||
entries_15_addrValid <= 1'h0;
|
||||
entries_15_dataValid <= 1'h0;
|
||||
entries_15_addr <= 64'h0;
|
||||
entries_15_data <= 64'h0;
|
||||
entries_15_size <= 3'h0;
|
||||
entries_15_committed <= 1'h0;
|
||||
end
|
||||
else begin
|
||||
automatic logic _GEN_2 =
|
||||
io_enqValid
|
||||
& (|{~entries_15_valid,
|
||||
~entries_14_valid,
|
||||
~entries_13_valid,
|
||||
~entries_12_valid,
|
||||
~entries_11_valid,
|
||||
~entries_10_valid,
|
||||
~entries_9_valid,
|
||||
~entries_8_valid,
|
||||
~entries_7_valid,
|
||||
~entries_6_valid,
|
||||
~entries_5_valid,
|
||||
~entries_4_valid,
|
||||
~entries_3_valid,
|
||||
~entries_2_valid,
|
||||
~entries_1_valid,
|
||||
~entries_0_valid});
|
||||
automatic logic _GEN_3;
|
||||
automatic logic _GEN_4;
|
||||
automatic logic _GEN_5;
|
||||
automatic logic _GEN_6;
|
||||
automatic logic _GEN_7;
|
||||
automatic logic _GEN_8;
|
||||
automatic logic _GEN_9;
|
||||
automatic logic _GEN_10;
|
||||
automatic logic _GEN_11;
|
||||
automatic logic _GEN_12;
|
||||
automatic logic _GEN_13;
|
||||
automatic logic _GEN_14;
|
||||
automatic logic _GEN_15;
|
||||
automatic logic _GEN_16;
|
||||
automatic logic _GEN_17;
|
||||
automatic logic _GEN_18;
|
||||
automatic logic _GEN_19 = io_writeIdx == 4'h0;
|
||||
automatic logic _GEN_20;
|
||||
automatic logic _GEN_21 = io_writeIdx == 4'h1;
|
||||
automatic logic _GEN_22;
|
||||
automatic logic _GEN_23 = io_writeIdx == 4'h2;
|
||||
automatic logic _GEN_24;
|
||||
automatic logic _GEN_25 = io_writeIdx == 4'h3;
|
||||
automatic logic _GEN_26;
|
||||
automatic logic _GEN_27 = io_writeIdx == 4'h4;
|
||||
automatic logic _GEN_28;
|
||||
automatic logic _GEN_29 = io_writeIdx == 4'h5;
|
||||
automatic logic _GEN_30;
|
||||
automatic logic _GEN_31 = io_writeIdx == 4'h6;
|
||||
automatic logic _GEN_32;
|
||||
automatic logic _GEN_33 = io_writeIdx == 4'h7;
|
||||
automatic logic _GEN_34;
|
||||
automatic logic _GEN_35 = io_writeIdx == 4'h8;
|
||||
automatic logic _GEN_36;
|
||||
automatic logic _GEN_37 = io_writeIdx == 4'h9;
|
||||
automatic logic _GEN_38;
|
||||
automatic logic _GEN_39 = io_writeIdx == 4'hA;
|
||||
automatic logic _GEN_40;
|
||||
automatic logic _GEN_41 = io_writeIdx == 4'hB;
|
||||
automatic logic _GEN_42;
|
||||
automatic logic _GEN_43 = io_writeIdx == 4'hC;
|
||||
automatic logic _GEN_44;
|
||||
automatic logic _GEN_45 = io_writeIdx == 4'hD;
|
||||
automatic logic _GEN_46;
|
||||
automatic logic _GEN_47 = io_writeIdx == 4'hE;
|
||||
automatic logic _GEN_48;
|
||||
automatic logic _GEN_49;
|
||||
automatic logic _GEN_50;
|
||||
automatic logic _GEN_51;
|
||||
automatic logic _GEN_52;
|
||||
automatic logic _GEN_53;
|
||||
automatic logic _GEN_54;
|
||||
automatic logic _GEN_55;
|
||||
automatic logic _GEN_56;
|
||||
automatic logic _GEN_57;
|
||||
automatic logic _GEN_58;
|
||||
automatic logic _GEN_59;
|
||||
automatic logic _GEN_60;
|
||||
automatic logic _GEN_61;
|
||||
automatic logic _GEN_62;
|
||||
automatic logic _GEN_63;
|
||||
automatic logic _GEN_64;
|
||||
automatic logic _GEN_65;
|
||||
automatic logic _GEN_66 = (|_io_drainValid_T) & io_drainReady;
|
||||
_GEN_3 = _GEN_2 & enqIdx == 4'h0;
|
||||
_GEN_4 = _GEN_2 & enqIdx == 4'h1;
|
||||
_GEN_5 = _GEN_2 & enqIdx == 4'h2;
|
||||
_GEN_6 = _GEN_2 & enqIdx == 4'h3;
|
||||
_GEN_7 = _GEN_2 & enqIdx == 4'h4;
|
||||
_GEN_8 = _GEN_2 & enqIdx == 4'h5;
|
||||
_GEN_9 = _GEN_2 & enqIdx == 4'h6;
|
||||
_GEN_10 = _GEN_2 & enqIdx == 4'h7;
|
||||
_GEN_11 = _GEN_2 & enqIdx == 4'h8;
|
||||
_GEN_12 = _GEN_2 & enqIdx == 4'h9;
|
||||
_GEN_13 = _GEN_2 & enqIdx == 4'hA;
|
||||
_GEN_14 = _GEN_2 & enqIdx == 4'hB;
|
||||
_GEN_15 = _GEN_2 & enqIdx == 4'hC;
|
||||
_GEN_16 = _GEN_2 & enqIdx == 4'hD;
|
||||
_GEN_17 = _GEN_2 & enqIdx == 4'hE;
|
||||
_GEN_18 = _GEN_2 & (&enqIdx);
|
||||
_GEN_20 = io_writeAddr & _GEN_19;
|
||||
_GEN_22 = io_writeAddr & _GEN_21;
|
||||
_GEN_24 = io_writeAddr & _GEN_23;
|
||||
_GEN_26 = io_writeAddr & _GEN_25;
|
||||
_GEN_28 = io_writeAddr & _GEN_27;
|
||||
_GEN_30 = io_writeAddr & _GEN_29;
|
||||
_GEN_32 = io_writeAddr & _GEN_31;
|
||||
_GEN_34 = io_writeAddr & _GEN_33;
|
||||
_GEN_36 = io_writeAddr & _GEN_35;
|
||||
_GEN_38 = io_writeAddr & _GEN_37;
|
||||
_GEN_40 = io_writeAddr & _GEN_39;
|
||||
_GEN_42 = io_writeAddr & _GEN_41;
|
||||
_GEN_44 = io_writeAddr & _GEN_43;
|
||||
_GEN_46 = io_writeAddr & _GEN_45;
|
||||
_GEN_48 = io_writeAddr & _GEN_47;
|
||||
_GEN_49 = io_writeAddr & (&io_writeIdx);
|
||||
_GEN_50 = io_writeData & _GEN_19;
|
||||
_GEN_51 = io_writeData & _GEN_21;
|
||||
_GEN_52 = io_writeData & _GEN_23;
|
||||
_GEN_53 = io_writeData & _GEN_25;
|
||||
_GEN_54 = io_writeData & _GEN_27;
|
||||
_GEN_55 = io_writeData & _GEN_29;
|
||||
_GEN_56 = io_writeData & _GEN_31;
|
||||
_GEN_57 = io_writeData & _GEN_33;
|
||||
_GEN_58 = io_writeData & _GEN_35;
|
||||
_GEN_59 = io_writeData & _GEN_37;
|
||||
_GEN_60 = io_writeData & _GEN_39;
|
||||
_GEN_61 = io_writeData & _GEN_41;
|
||||
_GEN_62 = io_writeData & _GEN_43;
|
||||
_GEN_63 = io_writeData & _GEN_45;
|
||||
_GEN_64 = io_writeData & _GEN_47;
|
||||
_GEN_65 = io_writeData & (&io_writeIdx);
|
||||
entries_0_valid <=
|
||||
~(io_flush | _GEN_66 & drainIdx == 4'h0) & (_GEN_3 | entries_0_valid);
|
||||
if (io_flush) begin
|
||||
entries_0_robIdx <= 6'h0;
|
||||
entries_0_addr <= 64'h0;
|
||||
entries_0_data <= 64'h0;
|
||||
entries_0_size <= 3'h0;
|
||||
entries_1_robIdx <= 6'h0;
|
||||
entries_1_addr <= 64'h0;
|
||||
entries_1_data <= 64'h0;
|
||||
entries_1_size <= 3'h0;
|
||||
entries_2_robIdx <= 6'h0;
|
||||
entries_2_addr <= 64'h0;
|
||||
entries_2_data <= 64'h0;
|
||||
entries_2_size <= 3'h0;
|
||||
entries_3_robIdx <= 6'h0;
|
||||
entries_3_addr <= 64'h0;
|
||||
entries_3_data <= 64'h0;
|
||||
entries_3_size <= 3'h0;
|
||||
entries_4_robIdx <= 6'h0;
|
||||
entries_4_addr <= 64'h0;
|
||||
entries_4_data <= 64'h0;
|
||||
entries_4_size <= 3'h0;
|
||||
entries_5_robIdx <= 6'h0;
|
||||
entries_5_addr <= 64'h0;
|
||||
entries_5_data <= 64'h0;
|
||||
entries_5_size <= 3'h0;
|
||||
entries_6_robIdx <= 6'h0;
|
||||
entries_6_addr <= 64'h0;
|
||||
entries_6_data <= 64'h0;
|
||||
entries_6_size <= 3'h0;
|
||||
entries_7_robIdx <= 6'h0;
|
||||
entries_7_addr <= 64'h0;
|
||||
entries_7_data <= 64'h0;
|
||||
entries_7_size <= 3'h0;
|
||||
entries_8_robIdx <= 6'h0;
|
||||
entries_8_addr <= 64'h0;
|
||||
entries_8_data <= 64'h0;
|
||||
entries_8_size <= 3'h0;
|
||||
entries_9_robIdx <= 6'h0;
|
||||
entries_9_addr <= 64'h0;
|
||||
entries_9_data <= 64'h0;
|
||||
entries_9_size <= 3'h0;
|
||||
entries_10_robIdx <= 6'h0;
|
||||
entries_10_addr <= 64'h0;
|
||||
entries_10_data <= 64'h0;
|
||||
entries_10_size <= 3'h0;
|
||||
entries_11_robIdx <= 6'h0;
|
||||
entries_11_addr <= 64'h0;
|
||||
entries_11_data <= 64'h0;
|
||||
entries_11_size <= 3'h0;
|
||||
entries_12_robIdx <= 6'h0;
|
||||
entries_12_addr <= 64'h0;
|
||||
entries_12_data <= 64'h0;
|
||||
entries_12_size <= 3'h0;
|
||||
entries_13_robIdx <= 6'h0;
|
||||
entries_13_addr <= 64'h0;
|
||||
entries_13_data <= 64'h0;
|
||||
entries_13_size <= 3'h0;
|
||||
entries_14_robIdx <= 6'h0;
|
||||
entries_14_addr <= 64'h0;
|
||||
entries_14_data <= 64'h0;
|
||||
entries_14_size <= 3'h0;
|
||||
entries_15_robIdx <= 6'h0;
|
||||
entries_15_addr <= 64'h0;
|
||||
entries_15_data <= 64'h0;
|
||||
entries_15_size <= 3'h0;
|
||||
end
|
||||
else begin
|
||||
if (_GEN_3)
|
||||
entries_0_robIdx <= io_enqRobIdx;
|
||||
if (_GEN_20) begin
|
||||
entries_0_addr <= io_addr;
|
||||
entries_0_size <= io_size;
|
||||
end
|
||||
if (_GEN_50)
|
||||
entries_0_data <= io_data;
|
||||
if (_GEN_4)
|
||||
entries_1_robIdx <= io_enqRobIdx;
|
||||
if (_GEN_22) begin
|
||||
entries_1_addr <= io_addr;
|
||||
entries_1_size <= io_size;
|
||||
end
|
||||
if (_GEN_51)
|
||||
entries_1_data <= io_data;
|
||||
if (_GEN_5)
|
||||
entries_2_robIdx <= io_enqRobIdx;
|
||||
if (_GEN_24) begin
|
||||
entries_2_addr <= io_addr;
|
||||
entries_2_size <= io_size;
|
||||
end
|
||||
if (_GEN_52)
|
||||
entries_2_data <= io_data;
|
||||
if (_GEN_6)
|
||||
entries_3_robIdx <= io_enqRobIdx;
|
||||
if (_GEN_26) begin
|
||||
entries_3_addr <= io_addr;
|
||||
entries_3_size <= io_size;
|
||||
end
|
||||
if (_GEN_53)
|
||||
entries_3_data <= io_data;
|
||||
if (_GEN_7)
|
||||
entries_4_robIdx <= io_enqRobIdx;
|
||||
if (_GEN_28) begin
|
||||
entries_4_addr <= io_addr;
|
||||
entries_4_size <= io_size;
|
||||
end
|
||||
if (_GEN_54)
|
||||
entries_4_data <= io_data;
|
||||
if (_GEN_8)
|
||||
entries_5_robIdx <= io_enqRobIdx;
|
||||
if (_GEN_30) begin
|
||||
entries_5_addr <= io_addr;
|
||||
entries_5_size <= io_size;
|
||||
end
|
||||
if (_GEN_55)
|
||||
entries_5_data <= io_data;
|
||||
if (_GEN_9)
|
||||
entries_6_robIdx <= io_enqRobIdx;
|
||||
if (_GEN_32) begin
|
||||
entries_6_addr <= io_addr;
|
||||
entries_6_size <= io_size;
|
||||
end
|
||||
if (_GEN_56)
|
||||
entries_6_data <= io_data;
|
||||
if (_GEN_10)
|
||||
entries_7_robIdx <= io_enqRobIdx;
|
||||
if (_GEN_34) begin
|
||||
entries_7_addr <= io_addr;
|
||||
entries_7_size <= io_size;
|
||||
end
|
||||
if (_GEN_57)
|
||||
entries_7_data <= io_data;
|
||||
if (_GEN_11)
|
||||
entries_8_robIdx <= io_enqRobIdx;
|
||||
if (_GEN_36) begin
|
||||
entries_8_addr <= io_addr;
|
||||
entries_8_size <= io_size;
|
||||
end
|
||||
if (_GEN_58)
|
||||
entries_8_data <= io_data;
|
||||
if (_GEN_12)
|
||||
entries_9_robIdx <= io_enqRobIdx;
|
||||
if (_GEN_38) begin
|
||||
entries_9_addr <= io_addr;
|
||||
entries_9_size <= io_size;
|
||||
end
|
||||
if (_GEN_59)
|
||||
entries_9_data <= io_data;
|
||||
if (_GEN_13)
|
||||
entries_10_robIdx <= io_enqRobIdx;
|
||||
if (_GEN_40) begin
|
||||
entries_10_addr <= io_addr;
|
||||
entries_10_size <= io_size;
|
||||
end
|
||||
if (_GEN_60)
|
||||
entries_10_data <= io_data;
|
||||
if (_GEN_14)
|
||||
entries_11_robIdx <= io_enqRobIdx;
|
||||
if (_GEN_42) begin
|
||||
entries_11_addr <= io_addr;
|
||||
entries_11_size <= io_size;
|
||||
end
|
||||
if (_GEN_61)
|
||||
entries_11_data <= io_data;
|
||||
if (_GEN_15)
|
||||
entries_12_robIdx <= io_enqRobIdx;
|
||||
if (_GEN_44) begin
|
||||
entries_12_addr <= io_addr;
|
||||
entries_12_size <= io_size;
|
||||
end
|
||||
if (_GEN_62)
|
||||
entries_12_data <= io_data;
|
||||
if (_GEN_16)
|
||||
entries_13_robIdx <= io_enqRobIdx;
|
||||
if (_GEN_46) begin
|
||||
entries_13_addr <= io_addr;
|
||||
entries_13_size <= io_size;
|
||||
end
|
||||
if (_GEN_63)
|
||||
entries_13_data <= io_data;
|
||||
if (_GEN_17)
|
||||
entries_14_robIdx <= io_enqRobIdx;
|
||||
if (_GEN_48) begin
|
||||
entries_14_addr <= io_addr;
|
||||
entries_14_size <= io_size;
|
||||
end
|
||||
if (_GEN_64)
|
||||
entries_14_data <= io_data;
|
||||
if (_GEN_18)
|
||||
entries_15_robIdx <= io_enqRobIdx;
|
||||
if (_GEN_49) begin
|
||||
entries_15_addr <= io_addr;
|
||||
entries_15_size <= io_size;
|
||||
end
|
||||
if (_GEN_65)
|
||||
entries_15_data <= io_data;
|
||||
end
|
||||
entries_0_addrValid <= ~io_flush & (_GEN_20 | ~_GEN_3 & entries_0_addrValid);
|
||||
entries_0_dataValid <= ~io_flush & (_GEN_50 | ~_GEN_3 & entries_0_dataValid);
|
||||
entries_0_committed <=
|
||||
~io_flush
|
||||
& (io_commitValid & entries_0_valid & entries_0_robIdx == io_commitRobIdx
|
||||
| ~_GEN_3 & entries_0_committed);
|
||||
entries_1_valid <=
|
||||
~(io_flush | _GEN_66 & drainIdx == 4'h1) & (_GEN_4 | entries_1_valid);
|
||||
entries_1_addrValid <= ~io_flush & (_GEN_22 | ~_GEN_4 & entries_1_addrValid);
|
||||
entries_1_dataValid <= ~io_flush & (_GEN_51 | ~_GEN_4 & entries_1_dataValid);
|
||||
entries_1_committed <=
|
||||
~io_flush
|
||||
& (io_commitValid & entries_1_valid & entries_1_robIdx == io_commitRobIdx
|
||||
| ~_GEN_4 & entries_1_committed);
|
||||
entries_2_valid <=
|
||||
~(io_flush | _GEN_66 & drainIdx == 4'h2) & (_GEN_5 | entries_2_valid);
|
||||
entries_2_addrValid <= ~io_flush & (_GEN_24 | ~_GEN_5 & entries_2_addrValid);
|
||||
entries_2_dataValid <= ~io_flush & (_GEN_52 | ~_GEN_5 & entries_2_dataValid);
|
||||
entries_2_committed <=
|
||||
~io_flush
|
||||
& (io_commitValid & entries_2_valid & entries_2_robIdx == io_commitRobIdx
|
||||
| ~_GEN_5 & entries_2_committed);
|
||||
entries_3_valid <=
|
||||
~(io_flush | _GEN_66 & drainIdx == 4'h3) & (_GEN_6 | entries_3_valid);
|
||||
entries_3_addrValid <= ~io_flush & (_GEN_26 | ~_GEN_6 & entries_3_addrValid);
|
||||
entries_3_dataValid <= ~io_flush & (_GEN_53 | ~_GEN_6 & entries_3_dataValid);
|
||||
entries_3_committed <=
|
||||
~io_flush
|
||||
& (io_commitValid & entries_3_valid & entries_3_robIdx == io_commitRobIdx
|
||||
| ~_GEN_6 & entries_3_committed);
|
||||
entries_4_valid <=
|
||||
~(io_flush | _GEN_66 & drainIdx == 4'h4) & (_GEN_7 | entries_4_valid);
|
||||
entries_4_addrValid <= ~io_flush & (_GEN_28 | ~_GEN_7 & entries_4_addrValid);
|
||||
entries_4_dataValid <= ~io_flush & (_GEN_54 | ~_GEN_7 & entries_4_dataValid);
|
||||
entries_4_committed <=
|
||||
~io_flush
|
||||
& (io_commitValid & entries_4_valid & entries_4_robIdx == io_commitRobIdx
|
||||
| ~_GEN_7 & entries_4_committed);
|
||||
entries_5_valid <=
|
||||
~(io_flush | _GEN_66 & drainIdx == 4'h5) & (_GEN_8 | entries_5_valid);
|
||||
entries_5_addrValid <= ~io_flush & (_GEN_30 | ~_GEN_8 & entries_5_addrValid);
|
||||
entries_5_dataValid <= ~io_flush & (_GEN_55 | ~_GEN_8 & entries_5_dataValid);
|
||||
entries_5_committed <=
|
||||
~io_flush
|
||||
& (io_commitValid & entries_5_valid & entries_5_robIdx == io_commitRobIdx
|
||||
| ~_GEN_8 & entries_5_committed);
|
||||
entries_6_valid <=
|
||||
~(io_flush | _GEN_66 & drainIdx == 4'h6) & (_GEN_9 | entries_6_valid);
|
||||
entries_6_addrValid <= ~io_flush & (_GEN_32 | ~_GEN_9 & entries_6_addrValid);
|
||||
entries_6_dataValid <= ~io_flush & (_GEN_56 | ~_GEN_9 & entries_6_dataValid);
|
||||
entries_6_committed <=
|
||||
~io_flush
|
||||
& (io_commitValid & entries_6_valid & entries_6_robIdx == io_commitRobIdx
|
||||
| ~_GEN_9 & entries_6_committed);
|
||||
entries_7_valid <=
|
||||
~(io_flush | _GEN_66 & drainIdx == 4'h7) & (_GEN_10 | entries_7_valid);
|
||||
entries_7_addrValid <= ~io_flush & (_GEN_34 | ~_GEN_10 & entries_7_addrValid);
|
||||
entries_7_dataValid <= ~io_flush & (_GEN_57 | ~_GEN_10 & entries_7_dataValid);
|
||||
entries_7_committed <=
|
||||
~io_flush
|
||||
& (io_commitValid & entries_7_valid & entries_7_robIdx == io_commitRobIdx
|
||||
| ~_GEN_10 & entries_7_committed);
|
||||
entries_8_valid <=
|
||||
~(io_flush | _GEN_66 & drainIdx == 4'h8) & (_GEN_11 | entries_8_valid);
|
||||
entries_8_addrValid <= ~io_flush & (_GEN_36 | ~_GEN_11 & entries_8_addrValid);
|
||||
entries_8_dataValid <= ~io_flush & (_GEN_58 | ~_GEN_11 & entries_8_dataValid);
|
||||
entries_8_committed <=
|
||||
~io_flush
|
||||
& (io_commitValid & entries_8_valid & entries_8_robIdx == io_commitRobIdx
|
||||
| ~_GEN_11 & entries_8_committed);
|
||||
entries_9_valid <=
|
||||
~(io_flush | _GEN_66 & drainIdx == 4'h9) & (_GEN_12 | entries_9_valid);
|
||||
entries_9_addrValid <= ~io_flush & (_GEN_38 | ~_GEN_12 & entries_9_addrValid);
|
||||
entries_9_dataValid <= ~io_flush & (_GEN_59 | ~_GEN_12 & entries_9_dataValid);
|
||||
entries_9_committed <=
|
||||
~io_flush
|
||||
& (io_commitValid & entries_9_valid & entries_9_robIdx == io_commitRobIdx
|
||||
| ~_GEN_12 & entries_9_committed);
|
||||
entries_10_valid <=
|
||||
~(io_flush | _GEN_66 & drainIdx == 4'hA) & (_GEN_13 | entries_10_valid);
|
||||
entries_10_addrValid <= ~io_flush & (_GEN_40 | ~_GEN_13 & entries_10_addrValid);
|
||||
entries_10_dataValid <= ~io_flush & (_GEN_60 | ~_GEN_13 & entries_10_dataValid);
|
||||
entries_10_committed <=
|
||||
~io_flush
|
||||
& (io_commitValid & entries_10_valid & entries_10_robIdx == io_commitRobIdx
|
||||
| ~_GEN_13 & entries_10_committed);
|
||||
entries_11_valid <=
|
||||
~(io_flush | _GEN_66 & drainIdx == 4'hB) & (_GEN_14 | entries_11_valid);
|
||||
entries_11_addrValid <= ~io_flush & (_GEN_42 | ~_GEN_14 & entries_11_addrValid);
|
||||
entries_11_dataValid <= ~io_flush & (_GEN_61 | ~_GEN_14 & entries_11_dataValid);
|
||||
entries_11_committed <=
|
||||
~io_flush
|
||||
& (io_commitValid & entries_11_valid & entries_11_robIdx == io_commitRobIdx
|
||||
| ~_GEN_14 & entries_11_committed);
|
||||
entries_12_valid <=
|
||||
~(io_flush | _GEN_66 & drainIdx == 4'hC) & (_GEN_15 | entries_12_valid);
|
||||
entries_12_addrValid <= ~io_flush & (_GEN_44 | ~_GEN_15 & entries_12_addrValid);
|
||||
entries_12_dataValid <= ~io_flush & (_GEN_62 | ~_GEN_15 & entries_12_dataValid);
|
||||
entries_12_committed <=
|
||||
~io_flush
|
||||
& (io_commitValid & entries_12_valid & entries_12_robIdx == io_commitRobIdx
|
||||
| ~_GEN_15 & entries_12_committed);
|
||||
entries_13_valid <=
|
||||
~(io_flush | _GEN_66 & drainIdx == 4'hD) & (_GEN_16 | entries_13_valid);
|
||||
entries_13_addrValid <= ~io_flush & (_GEN_46 | ~_GEN_16 & entries_13_addrValid);
|
||||
entries_13_dataValid <= ~io_flush & (_GEN_63 | ~_GEN_16 & entries_13_dataValid);
|
||||
entries_13_committed <=
|
||||
~io_flush
|
||||
& (io_commitValid & entries_13_valid & entries_13_robIdx == io_commitRobIdx
|
||||
| ~_GEN_16 & entries_13_committed);
|
||||
entries_14_valid <=
|
||||
~(io_flush | _GEN_66 & drainIdx == 4'hE) & (_GEN_17 | entries_14_valid);
|
||||
entries_14_addrValid <= ~io_flush & (_GEN_48 | ~_GEN_17 & entries_14_addrValid);
|
||||
entries_14_dataValid <= ~io_flush & (_GEN_64 | ~_GEN_17 & entries_14_dataValid);
|
||||
entries_14_committed <=
|
||||
~io_flush
|
||||
& (io_commitValid & entries_14_valid & entries_14_robIdx == io_commitRobIdx
|
||||
| ~_GEN_17 & entries_14_committed);
|
||||
entries_15_valid <=
|
||||
~(io_flush | _GEN_66 & (&drainIdx)) & (_GEN_18 | entries_15_valid);
|
||||
entries_15_addrValid <= ~io_flush & (_GEN_49 | ~_GEN_18 & entries_15_addrValid);
|
||||
entries_15_dataValid <= ~io_flush & (_GEN_65 | ~_GEN_18 & entries_15_dataValid);
|
||||
entries_15_committed <=
|
||||
~io_flush
|
||||
& (io_commitValid & entries_15_valid & entries_15_robIdx == io_commitRobIdx
|
||||
| ~_GEN_18 & entries_15_committed);
|
||||
end
|
||||
end // always @(posedge)
|
||||
assign io_enqIdx = enqIdx;
|
||||
assign io_forwardValid =
|
||||
|{entries_15_valid & entries_15_addrValid & entries_15_dataValid
|
||||
& entries_15_robIdx < io_loadRobIdx & entries_15_addr[63:3] == io_loadAddr[63:3],
|
||||
entries_14_valid & entries_14_addrValid & entries_14_dataValid
|
||||
& entries_14_robIdx < io_loadRobIdx & entries_14_addr[63:3] == io_loadAddr[63:3],
|
||||
entries_13_valid & entries_13_addrValid & entries_13_dataValid
|
||||
& entries_13_robIdx < io_loadRobIdx & entries_13_addr[63:3] == io_loadAddr[63:3],
|
||||
entries_12_valid & entries_12_addrValid & entries_12_dataValid
|
||||
& entries_12_robIdx < io_loadRobIdx & entries_12_addr[63:3] == io_loadAddr[63:3],
|
||||
entries_11_valid & entries_11_addrValid & entries_11_dataValid
|
||||
& entries_11_robIdx < io_loadRobIdx & entries_11_addr[63:3] == io_loadAddr[63:3],
|
||||
entries_10_valid & entries_10_addrValid & entries_10_dataValid
|
||||
& entries_10_robIdx < io_loadRobIdx & entries_10_addr[63:3] == io_loadAddr[63:3],
|
||||
entries_9_valid & entries_9_addrValid & entries_9_dataValid
|
||||
& entries_9_robIdx < io_loadRobIdx & entries_9_addr[63:3] == io_loadAddr[63:3],
|
||||
entries_8_valid & entries_8_addrValid & entries_8_dataValid
|
||||
& entries_8_robIdx < io_loadRobIdx & entries_8_addr[63:3] == io_loadAddr[63:3],
|
||||
entries_7_valid & entries_7_addrValid & entries_7_dataValid
|
||||
& entries_7_robIdx < io_loadRobIdx & entries_7_addr[63:3] == io_loadAddr[63:3],
|
||||
entries_6_valid & entries_6_addrValid & entries_6_dataValid
|
||||
& entries_6_robIdx < io_loadRobIdx & entries_6_addr[63:3] == io_loadAddr[63:3],
|
||||
entries_5_valid & entries_5_addrValid & entries_5_dataValid
|
||||
& entries_5_robIdx < io_loadRobIdx & entries_5_addr[63:3] == io_loadAddr[63:3],
|
||||
entries_4_valid & entries_4_addrValid & entries_4_dataValid
|
||||
& entries_4_robIdx < io_loadRobIdx & entries_4_addr[63:3] == io_loadAddr[63:3],
|
||||
entries_3_valid & entries_3_addrValid & entries_3_dataValid
|
||||
& entries_3_robIdx < io_loadRobIdx & entries_3_addr[63:3] == io_loadAddr[63:3],
|
||||
entries_2_valid & entries_2_addrValid & entries_2_dataValid
|
||||
& entries_2_robIdx < io_loadRobIdx & entries_2_addr[63:3] == io_loadAddr[63:3],
|
||||
entries_1_valid & entries_1_addrValid & entries_1_dataValid
|
||||
& entries_1_robIdx < io_loadRobIdx & entries_1_addr[63:3] == io_loadAddr[63:3],
|
||||
entries_0_valid & entries_0_addrValid & entries_0_dataValid
|
||||
& entries_0_robIdx < io_loadRobIdx & entries_0_addr[63:3] == io_loadAddr[63:3]};
|
||||
assign io_drainValid = |_io_drainValid_T;
|
||||
assign io_drain_addr = _GEN[drainIdx];
|
||||
assign io_drain_data = _GEN_0[drainIdx];
|
||||
assign io_drain_size = _GEN_1[drainIdx];
|
||||
endmodule
|
||||
|
||||
Reference in New Issue
Block a user