fix: resolve OoO simulation timeout
This commit is contained in:
abnerhexu
565
generated-ooo/RenameTable.sv
Normal file
565
generated-ooo/RenameTable.sv
Normal file
@@ -0,0 +1,565 @@
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// Generated by CIRCT firtool-1.139.0
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module RenameTable(
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input clock,
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reset,
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input [4:0] io_rs1_0,
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io_rs1_1,
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io_rs2_0,
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io_rs2_1,
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io_rd_0,
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io_rd_1,
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input [5:0] io_newPhys_0,
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io_newPhys_1,
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input io_wen_0,
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io_wen_1,
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output [5:0] io_prs1_0,
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io_prs1_1,
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io_prs2_0,
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io_prs2_1,
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io_oldPrd_0,
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io_oldPrd_1,
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input io_commitWen_0,
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io_commitWen_1,
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input [4:0] io_commitRd_0,
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io_commitRd_1,
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input [5:0] io_commitPhys_0,
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io_commitPhys_1,
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input io_recover,
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output [5:0] io_committedPhys_0,
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io_committedPhys_1,
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io_committedPhys_2,
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io_committedPhys_3,
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io_committedPhys_4,
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io_committedPhys_5,
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io_committedPhys_6,
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io_committedPhys_7,
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io_committedPhys_8,
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io_committedPhys_9,
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io_committedPhys_10,
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io_committedPhys_11,
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io_committedPhys_12,
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io_committedPhys_13,
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io_committedPhys_14,
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io_committedPhys_15,
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io_committedPhys_16,
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io_committedPhys_17,
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io_committedPhys_18,
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io_committedPhys_19,
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io_committedPhys_20,
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io_committedPhys_21,
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io_committedPhys_22,
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io_committedPhys_23,
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io_committedPhys_24,
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io_committedPhys_25,
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io_committedPhys_26,
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io_committedPhys_27,
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io_committedPhys_28,
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io_committedPhys_29,
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io_committedPhys_30,
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io_committedPhys_31
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);
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reg [5:0] speculative_0;
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reg [5:0] speculative_1;
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reg [5:0] speculative_2;
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reg [5:0] speculative_3;
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reg [5:0] speculative_4;
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reg [5:0] speculative_5;
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reg [5:0] speculative_6;
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reg [5:0] speculative_7;
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reg [5:0] speculative_8;
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reg [5:0] speculative_9;
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reg [5:0] speculative_10;
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reg [5:0] speculative_11;
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reg [5:0] speculative_12;
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reg [5:0] speculative_13;
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reg [5:0] speculative_14;
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reg [5:0] speculative_15;
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reg [5:0] speculative_16;
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reg [5:0] speculative_17;
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reg [5:0] speculative_18;
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reg [5:0] speculative_19;
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reg [5:0] speculative_20;
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reg [5:0] speculative_21;
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reg [5:0] speculative_22;
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reg [5:0] speculative_23;
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reg [5:0] speculative_24;
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reg [5:0] speculative_25;
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reg [5:0] speculative_26;
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reg [5:0] speculative_27;
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reg [5:0] speculative_28;
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reg [5:0] speculative_29;
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reg [5:0] speculative_30;
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reg [5:0] speculative_31;
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reg [5:0] committed_0;
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reg [5:0] committed_1;
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reg [5:0] committed_2;
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reg [5:0] committed_3;
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reg [5:0] committed_4;
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reg [5:0] committed_5;
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reg [5:0] committed_6;
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reg [5:0] committed_7;
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reg [5:0] committed_8;
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reg [5:0] committed_9;
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reg [5:0] committed_10;
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reg [5:0] committed_11;
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reg [5:0] committed_12;
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reg [5:0] committed_13;
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reg [5:0] committed_14;
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reg [5:0] committed_15;
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reg [5:0] committed_16;
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reg [5:0] committed_17;
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reg [5:0] committed_18;
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reg [5:0] committed_19;
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reg [5:0] committed_20;
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reg [5:0] committed_21;
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reg [5:0] committed_22;
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reg [5:0] committed_23;
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reg [5:0] committed_24;
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reg [5:0] committed_25;
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reg [5:0] committed_26;
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reg [5:0] committed_27;
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reg [5:0] committed_28;
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reg [5:0] committed_29;
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reg [5:0] committed_30;
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reg [5:0] committed_31;
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wire [31:0][5:0] _GEN =
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{{speculative_31},
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{speculative_30},
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{speculative_29},
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{speculative_28},
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{speculative_27},
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{speculative_26},
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{speculative_25},
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{speculative_24},
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{speculative_23},
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{speculative_22},
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{speculative_21},
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{speculative_20},
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{speculative_19},
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{speculative_18},
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{speculative_17},
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{speculative_16},
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{speculative_15},
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{speculative_14},
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{speculative_13},
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{speculative_12},
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{speculative_11},
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{speculative_10},
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{speculative_9},
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{speculative_8},
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{speculative_7},
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{speculative_6},
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{speculative_5},
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{speculative_4},
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{speculative_3},
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{speculative_2},
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{speculative_1},
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{speculative_0}};
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wire slot0Writes = io_wen_0 & (|io_rd_0);
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always @(posedge clock) begin
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if (reset) begin
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speculative_0 <= 6'h0;
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speculative_1 <= 6'h1;
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speculative_2 <= 6'h2;
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speculative_3 <= 6'h3;
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speculative_4 <= 6'h4;
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speculative_5 <= 6'h5;
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speculative_6 <= 6'h6;
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speculative_7 <= 6'h7;
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speculative_8 <= 6'h8;
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speculative_9 <= 6'h9;
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speculative_10 <= 6'hA;
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speculative_11 <= 6'hB;
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speculative_12 <= 6'hC;
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speculative_13 <= 6'hD;
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speculative_14 <= 6'hE;
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speculative_15 <= 6'hF;
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speculative_16 <= 6'h10;
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speculative_17 <= 6'h11;
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speculative_18 <= 6'h12;
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speculative_19 <= 6'h13;
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speculative_20 <= 6'h14;
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speculative_21 <= 6'h15;
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speculative_22 <= 6'h16;
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speculative_23 <= 6'h17;
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speculative_24 <= 6'h18;
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speculative_25 <= 6'h19;
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speculative_26 <= 6'h1A;
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speculative_27 <= 6'h1B;
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speculative_28 <= 6'h1C;
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speculative_29 <= 6'h1D;
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speculative_30 <= 6'h1E;
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speculative_31 <= 6'h1F;
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committed_0 <= 6'h0;
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committed_1 <= 6'h1;
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committed_2 <= 6'h2;
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committed_3 <= 6'h3;
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committed_4 <= 6'h4;
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committed_5 <= 6'h5;
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committed_6 <= 6'h6;
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committed_7 <= 6'h7;
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committed_8 <= 6'h8;
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committed_9 <= 6'h9;
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committed_10 <= 6'hA;
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committed_11 <= 6'hB;
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committed_12 <= 6'hC;
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committed_13 <= 6'hD;
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committed_14 <= 6'hE;
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committed_15 <= 6'hF;
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committed_16 <= 6'h10;
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committed_17 <= 6'h11;
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committed_18 <= 6'h12;
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committed_19 <= 6'h13;
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committed_20 <= 6'h14;
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committed_21 <= 6'h15;
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committed_22 <= 6'h16;
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committed_23 <= 6'h17;
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committed_24 <= 6'h18;
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committed_25 <= 6'h19;
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committed_26 <= 6'h1A;
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committed_27 <= 6'h1B;
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committed_28 <= 6'h1C;
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committed_29 <= 6'h1D;
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committed_30 <= 6'h1E;
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committed_31 <= 6'h1F;
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end
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else if (io_recover) begin
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speculative_0 <= committed_0;
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speculative_1 <= committed_1;
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speculative_2 <= committed_2;
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speculative_3 <= committed_3;
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speculative_4 <= committed_4;
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speculative_5 <= committed_5;
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speculative_6 <= committed_6;
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speculative_7 <= committed_7;
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speculative_8 <= committed_8;
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speculative_9 <= committed_9;
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speculative_10 <= committed_10;
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speculative_11 <= committed_11;
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speculative_12 <= committed_12;
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speculative_13 <= committed_13;
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speculative_14 <= committed_14;
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speculative_15 <= committed_15;
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speculative_16 <= committed_16;
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speculative_17 <= committed_17;
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speculative_18 <= committed_18;
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speculative_19 <= committed_19;
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speculative_20 <= committed_20;
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speculative_21 <= committed_21;
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speculative_22 <= committed_22;
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speculative_23 <= committed_23;
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speculative_24 <= committed_24;
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speculative_25 <= committed_25;
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speculative_26 <= committed_26;
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speculative_27 <= committed_27;
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speculative_28 <= committed_28;
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speculative_29 <= committed_29;
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speculative_30 <= committed_30;
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speculative_31 <= committed_31;
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end
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else begin
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automatic logic _GEN_0;
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automatic logic _GEN_1;
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automatic logic _GEN_2 = io_wen_1 & (|io_rd_1);
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automatic logic _GEN_3 = io_commitWen_1 & (|io_commitRd_1);
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_GEN_0 = io_wen_0 & (|io_rd_0);
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_GEN_1 = io_commitWen_0 & (|io_commitRd_0);
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if (_GEN_2 & ~(|io_rd_1))
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speculative_0 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'h0)
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speculative_0 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'h1)
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speculative_1 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'h1)
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speculative_1 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'h2)
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speculative_2 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'h2)
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speculative_2 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'h3)
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speculative_3 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'h3)
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speculative_3 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'h4)
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speculative_4 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'h4)
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speculative_4 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'h5)
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speculative_5 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'h5)
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speculative_5 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'h6)
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speculative_6 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'h6)
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speculative_6 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'h7)
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speculative_7 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'h7)
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speculative_7 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'h8)
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speculative_8 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'h8)
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speculative_8 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'h9)
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speculative_9 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'h9)
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speculative_9 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'hA)
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speculative_10 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'hA)
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speculative_10 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'hB)
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speculative_11 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'hB)
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speculative_11 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'hC)
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speculative_12 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'hC)
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speculative_12 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'hD)
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speculative_13 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'hD)
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speculative_13 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'hE)
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speculative_14 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'hE)
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speculative_14 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'hF)
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speculative_15 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'hF)
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speculative_15 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'h10)
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speculative_16 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'h10)
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speculative_16 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'h11)
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speculative_17 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'h11)
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speculative_17 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'h12)
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speculative_18 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'h12)
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speculative_18 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'h13)
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speculative_19 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'h13)
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speculative_19 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'h14)
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speculative_20 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'h14)
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speculative_20 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'h15)
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speculative_21 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'h15)
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speculative_21 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'h16)
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speculative_22 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'h16)
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speculative_22 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'h17)
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speculative_23 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'h17)
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speculative_23 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'h18)
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speculative_24 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'h18)
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speculative_24 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'h19)
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speculative_25 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'h19)
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speculative_25 <= io_newPhys_0;
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if (_GEN_2 & io_rd_1 == 5'h1A)
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speculative_26 <= io_newPhys_1;
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else if (_GEN_0 & io_rd_0 == 5'h1A)
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speculative_26 <= io_newPhys_0;
|
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if (_GEN_2 & io_rd_1 == 5'h1B)
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speculative_27 <= io_newPhys_1;
|
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else if (_GEN_0 & io_rd_0 == 5'h1B)
|
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speculative_27 <= io_newPhys_0;
|
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if (_GEN_2 & io_rd_1 == 5'h1C)
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speculative_28 <= io_newPhys_1;
|
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else if (_GEN_0 & io_rd_0 == 5'h1C)
|
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speculative_28 <= io_newPhys_0;
|
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if (_GEN_2 & io_rd_1 == 5'h1D)
|
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speculative_29 <= io_newPhys_1;
|
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else if (_GEN_0 & io_rd_0 == 5'h1D)
|
||||
speculative_29 <= io_newPhys_0;
|
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if (_GEN_2 & io_rd_1 == 5'h1E)
|
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speculative_30 <= io_newPhys_1;
|
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else if (_GEN_0 & io_rd_0 == 5'h1E)
|
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speculative_30 <= io_newPhys_0;
|
||||
if (_GEN_2 & (&io_rd_1))
|
||||
speculative_31 <= io_newPhys_1;
|
||||
else if (_GEN_0 & (&io_rd_0))
|
||||
speculative_31 <= io_newPhys_0;
|
||||
if (_GEN_3 & ~(|io_commitRd_1))
|
||||
committed_0 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & ~(|io_commitRd_0))
|
||||
committed_0 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h1)
|
||||
committed_1 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h1)
|
||||
committed_1 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h2)
|
||||
committed_2 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h2)
|
||||
committed_2 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h3)
|
||||
committed_3 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h3)
|
||||
committed_3 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h4)
|
||||
committed_4 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h4)
|
||||
committed_4 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h5)
|
||||
committed_5 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h5)
|
||||
committed_5 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h6)
|
||||
committed_6 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h6)
|
||||
committed_6 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h7)
|
||||
committed_7 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h7)
|
||||
committed_7 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h8)
|
||||
committed_8 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h8)
|
||||
committed_8 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h9)
|
||||
committed_9 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h9)
|
||||
committed_9 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'hA)
|
||||
committed_10 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'hA)
|
||||
committed_10 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'hB)
|
||||
committed_11 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'hB)
|
||||
committed_11 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'hC)
|
||||
committed_12 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'hC)
|
||||
committed_12 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'hD)
|
||||
committed_13 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'hD)
|
||||
committed_13 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'hE)
|
||||
committed_14 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'hE)
|
||||
committed_14 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'hF)
|
||||
committed_15 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'hF)
|
||||
committed_15 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h10)
|
||||
committed_16 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h10)
|
||||
committed_16 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h11)
|
||||
committed_17 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h11)
|
||||
committed_17 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h12)
|
||||
committed_18 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h12)
|
||||
committed_18 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h13)
|
||||
committed_19 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h13)
|
||||
committed_19 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h14)
|
||||
committed_20 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h14)
|
||||
committed_20 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h15)
|
||||
committed_21 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h15)
|
||||
committed_21 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h16)
|
||||
committed_22 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h16)
|
||||
committed_22 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h17)
|
||||
committed_23 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h17)
|
||||
committed_23 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h18)
|
||||
committed_24 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h18)
|
||||
committed_24 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h19)
|
||||
committed_25 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h19)
|
||||
committed_25 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h1A)
|
||||
committed_26 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h1A)
|
||||
committed_26 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h1B)
|
||||
committed_27 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h1B)
|
||||
committed_27 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h1C)
|
||||
committed_28 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h1C)
|
||||
committed_28 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h1D)
|
||||
committed_29 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h1D)
|
||||
committed_29 <= io_commitPhys_0;
|
||||
if (_GEN_3 & io_commitRd_1 == 5'h1E)
|
||||
committed_30 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & io_commitRd_0 == 5'h1E)
|
||||
committed_30 <= io_commitPhys_0;
|
||||
if (_GEN_3 & (&io_commitRd_1))
|
||||
committed_31 <= io_commitPhys_1;
|
||||
else if (_GEN_1 & (&io_commitRd_0))
|
||||
committed_31 <= io_commitPhys_0;
|
||||
end
|
||||
end // always @(posedge)
|
||||
assign io_prs1_0 = _GEN[io_rs1_0];
|
||||
assign io_prs1_1 = slot0Writes & io_rd_0 == io_rs1_1 ? io_newPhys_0 : _GEN[io_rs1_1];
|
||||
assign io_prs2_0 = _GEN[io_rs2_0];
|
||||
assign io_prs2_1 = slot0Writes & io_rd_0 == io_rs2_1 ? io_newPhys_0 : _GEN[io_rs2_1];
|
||||
assign io_oldPrd_0 = _GEN[io_rd_0];
|
||||
assign io_oldPrd_1 = slot0Writes & io_rd_0 == io_rd_1 ? io_newPhys_0 : _GEN[io_rd_1];
|
||||
assign io_committedPhys_0 = committed_0;
|
||||
assign io_committedPhys_1 = committed_1;
|
||||
assign io_committedPhys_2 = committed_2;
|
||||
assign io_committedPhys_3 = committed_3;
|
||||
assign io_committedPhys_4 = committed_4;
|
||||
assign io_committedPhys_5 = committed_5;
|
||||
assign io_committedPhys_6 = committed_6;
|
||||
assign io_committedPhys_7 = committed_7;
|
||||
assign io_committedPhys_8 = committed_8;
|
||||
assign io_committedPhys_9 = committed_9;
|
||||
assign io_committedPhys_10 = committed_10;
|
||||
assign io_committedPhys_11 = committed_11;
|
||||
assign io_committedPhys_12 = committed_12;
|
||||
assign io_committedPhys_13 = committed_13;
|
||||
assign io_committedPhys_14 = committed_14;
|
||||
assign io_committedPhys_15 = committed_15;
|
||||
assign io_committedPhys_16 = committed_16;
|
||||
assign io_committedPhys_17 = committed_17;
|
||||
assign io_committedPhys_18 = committed_18;
|
||||
assign io_committedPhys_19 = committed_19;
|
||||
assign io_committedPhys_20 = committed_20;
|
||||
assign io_committedPhys_21 = committed_21;
|
||||
assign io_committedPhys_22 = committed_22;
|
||||
assign io_committedPhys_23 = committed_23;
|
||||
assign io_committedPhys_24 = committed_24;
|
||||
assign io_committedPhys_25 = committed_25;
|
||||
assign io_committedPhys_26 = committed_26;
|
||||
assign io_committedPhys_27 = committed_27;
|
||||
assign io_committedPhys_28 = committed_28;
|
||||
assign io_committedPhys_29 = committed_29;
|
||||
assign io_committedPhys_30 = committed_30;
|
||||
assign io_committedPhys_31 = committed_31;
|
||||
endmodule
|
||||
|
||||
Reference in New Issue
Block a user