Initial Chisel core implementation

src/main/scala/memory/LoadQueue.scala

@@ -0,0 +1,23 @@
+import chisel3._
+import chisel3.util._
+
+class LoadQueue(p: CoreParams = CoreParams()) extends Module {
+  val io = IO(new Bundle {
+    val enqValid = Input(Bool())
+    val enqAddr = Input(UInt(p.xlen.W))
+    val enqReady = Output(Bool())
+    val complete = Input(Bool())
+    val flush = Input(Bool())
+  })
+
+  val count = RegInit(0.U(log2Ceil(p.loadQueueEntries + 1).W))
+  io.enqReady := count =/= p.loadQueueEntries.U
+
+  when(io.flush) {
+    count := 0.U
+  }.otherwise {
+    when(io.enqValid && io.enqReady) { count := count + 1.U }
+    when(io.complete && count =/= 0.U) { count := count - 1.U }
+  }
+}
+