Initial Chisel core implementation
This commit is contained in:
21
src/main/scala/csr/PrivilegeControl.scala
Normal file
21
src/main/scala/csr/PrivilegeControl.scala
Normal file
@@ -0,0 +1,21 @@
|
||||
import chisel3._
|
||||
|
||||
class PrivilegeControl(p: CoreParams = CoreParams()) extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val trap = Input(Bool())
|
||||
val mret = Input(Bool())
|
||||
val sret = Input(Bool())
|
||||
val privilege = Output(UInt(2.W))
|
||||
})
|
||||
|
||||
val mode = RegInit(3.U(2.W))
|
||||
when(io.trap) {
|
||||
mode := 3.U
|
||||
}.elsewhen(io.mret) {
|
||||
mode := 0.U
|
||||
}.elsewhen(io.sret) {
|
||||
mode := 0.U
|
||||
}
|
||||
io.privilege := mode
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user