pagetable lab initialized

This commit is contained in:
2025-05-06 11:20:36 +08:00
parent 0e751d690f
commit 38997cbef6
42 changed files with 1963 additions and 1154 deletions

View File

@@ -13,7 +13,7 @@
// the UART control registers are memory-mapped
// at address UART0. this macro returns the
// address of one of the registers.
#define Reg(reg) ((volatile unsigned char *)(UART0 + reg))
#define Reg(reg) ((volatile unsigned char *)(UART0 + (reg)))
// the UART control registers.
// some have different meanings for
@@ -136,6 +136,7 @@ uartstart()
while(1){
if(uart_tx_w == uart_tx_r){
// transmit buffer is empty.
ReadReg(ISR);
return;
}