deploy-20250820-3 #1
@@ -1,13 +1,14 @@
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#include "RISCv64Backend.h"
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#include "RISCv64ISel.h"
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#include "RISCv64RegAlloc.h"
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#include "RISCv64LinearScan.h" // <--- 新增此行
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#include "RISCv64LinearScan.h"
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#include "RISCv64BasicBlockAlloc.h"
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#include "RISCv64AsmPrinter.h"
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#include "RISCv64Passes.h"
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#include <sstream>
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#include <future> // <--- 新增此行
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#include <chrono> // <--- 新增此行
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#include <iostream> // <--- 新增此行,用于打印超时警告
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#include <future>
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#include <chrono>
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#include <iostream>
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namespace sysy {
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// 顶层入口
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@@ -196,139 +197,7 @@ std::string RISCv64CodeGen::module_gen() {
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}
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std::string RISCv64CodeGen::function_gen(Function* func) {
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if (DEBUG) {
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// === 完整的后端处理流水线 ===
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// 阶段 1: 指令选择 (sysy::IR -> LLIR with virtual registers)
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DEBUG = 0;
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DEEPDEBUG = 0;
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RISCv64ISel isel;
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std::unique_ptr<MachineFunction> mfunc = isel.runOnFunction(func);
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// 第一次调试打印输出
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std::stringstream ss_after_isel;
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RISCv64AsmPrinter printer_isel(mfunc.get());
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printer_isel.run(ss_after_isel, true);
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// DEBUG = 1;
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// DEEPDEBUG = 1;
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if (DEBUG) {
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std::cerr << "====== Intermediate Representation after Instruction Selection ======\n"
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<< ss_after_isel.str();
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}
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// 阶段 2: 消除帧索引 (展开伪指令,计算局部变量偏移)
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// 这个Pass必须在寄存器分配之前运行
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EliminateFrameIndicesPass efi_pass;
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efi_pass.runOnMachineFunction(mfunc.get());
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if (DEBUG) {
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std::cerr << "====== stack info after eliminate frame indices ======\n";
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mfunc->dumpStackFrameInfo(std::cerr);
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std::stringstream ss_after_eli;
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printer_isel.run(ss_after_eli, true);
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std::cerr << "====== LLIR after eliminate frame indices ======\n"
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<< ss_after_eli.str();
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}
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// 阶段 2: 除法强度削弱优化 (Division Strength Reduction)
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DivStrengthReduction div_strength_reduction;
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div_strength_reduction.runOnMachineFunction(mfunc.get());
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// // 阶段 2.1: 指令调度 (Instruction Scheduling)
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// PreRA_Scheduler scheduler;
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// scheduler.runOnMachineFunction(mfunc.get());
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// 阶段 3: 物理寄存器分配 (Register Allocation)
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DEBUG = 1;
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// DEEPERDEBUG = 1;
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// 阶段 3: 物理寄存器分配 (带超时回退机制)
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/*
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* [临时修改]
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* 为了优先测试线性扫描分配器,暂时注释掉图着色分配器及其超时逻辑。
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* 原始逻辑是:优先使用图着色,超时(20s)后回退到线性扫描。
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* 在线性扫描分配器测试稳定后,可以恢复此处的代码。
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*/
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/*
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// 首先尝试图着色分配器
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if (DEBUG) std::cerr << "Attempting Register Allocation with Graph Coloring...\n";
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RISCv64RegAlloc gc_alloc(mfunc.get());
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// 异步执行图着色分配
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auto future = std::async(std::launch::async, [&gc_alloc]{
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gc_alloc.run();
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});
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// 等待最多20秒
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auto status = future.wait_for(std::chrono::seconds(20));
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if (status == std::future_status::timeout) {
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// 超时,切换到线性扫描分配器
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std::cerr << "Warning: Graph coloring register allocation timed out for function '"
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<< func->getName()
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<< "'. Switching to Linear Scan allocator."
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<< std::endl;
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// 注意:由于无法安全地停止gc_alloc线程,我们只能放弃它的结果。
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// 在此项目中,我们假设超时后原mfunc状态未被严重破坏,
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// 或者线性扫描会基于isel后的状态重新开始。
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// 为了安全,我们应该用一个新的mfunc或者重置mfunc状态,
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// 但在这里我们简化处理,直接在同一个mfunc上运行线性扫描。
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RISCv64LinearScan ls_alloc(mfunc.get());
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ls_alloc.run();
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} else {
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// 图着色成功完成
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if (DEBUG) std::cerr << "Graph Coloring allocation completed successfully.\n";
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// future.get()会重新抛出在线程中发生的任何异常
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future.get();
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}
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*/
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// [临时修改] 直接调用线性扫描分配器进行测试
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std::cerr << "Info: Directly testing Register Allocation with Linear Scan...\n";
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RISCv64LinearScan ls_alloc(mfunc.get());
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ls_alloc.run();
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// 阶段 3.1: 处理被调用者保存寄存器
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CalleeSavedHandler callee_handler;
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callee_handler.runOnMachineFunction(mfunc.get());
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if (DEBUG) {
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std::cerr << "====== stack info after callee handler ======\n";
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mfunc->dumpStackFrameInfo(std::cerr);
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}
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// // 阶段 4: 窥孔优化 (Peephole Optimization)
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// PeepholeOptimizer peephole;
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// peephole.runOnMachineFunction(mfunc.get());
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// 阶段 5: 局部指令调度 (Local Scheduling)
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PostRA_Scheduler local_scheduler;
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local_scheduler.runOnMachineFunction(mfunc.get());
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// 阶段 3.2: 插入序言和尾声
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PrologueEpilogueInsertionPass pei_pass;
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pei_pass.runOnMachineFunction(mfunc.get());
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DEBUG = 0;
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DEEPDEBUG = 0;
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// 阶段 3.3: 大立即数合法化
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LegalizeImmediatesPass legalizer;
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legalizer.runOnMachineFunction(mfunc.get());
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// 阶段 6: 代码发射 (Code Emission)
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std::stringstream ss;
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RISCv64AsmPrinter printer(mfunc.get());
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printer.run(ss);
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return ss.str();
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} else {
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// === 完整的后端处理流水线 ===
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// === 完整的后端处理流水线 ===
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// 阶段 1: 指令选择 (sysy::IR -> LLIR with virtual registers)
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RISCv64ISel isel;
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@@ -367,12 +236,56 @@ std::string RISCv64CodeGen::function_gen(Function* func) {
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// scheduler.runOnMachineFunction(mfunc.get());
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// 阶段 3: 物理寄存器分配 (Register Allocation)
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// RISCv64RegAlloc reg_alloc(mfunc.get());
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// reg_alloc.run();
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// [临时修改] 直接调用线性扫描分配器进行测试
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std::cerr << "Info: Directly testing Register Allocation with Linear Scan...\n";
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RISCv64LinearScan ls_alloc(mfunc.get());
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ls_alloc.run();
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// 首先尝试图着色分配器
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if (DEBUG) std::cerr << "Attempting Register Allocation with Graph Coloring...\n";
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RISCv64RegAlloc gc_alloc(mfunc.get());
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// 异步执行图着色分配
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auto future = std::async(std::launch::async, [&gc_alloc]{
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gc_alloc.run();
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});
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// 等待最多20秒
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auto status = future.wait_for(std::chrono::seconds(20));
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if (status == std::future_status::timeout) {
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// 超时,切换到线性扫描分配器
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std::cerr << "Warning: Graph coloring register allocation timed out for function '"
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<< func->getName()
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<< "'. Switching to Linear Scan allocator."
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<< std::endl;
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// 注意:由于无法安全地停止gc_alloc线程,我们只能放弃它的结果。
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// 在此项目中,我们假设超时后原mfunc状态未被严重破坏,
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// 或者线性扫描会基于isel后的状态重新开始。
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// 为了安全,我们应该用一个新的mfunc或者重置mfunc状态,
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// 但在这里我们简化处理,直接在同一个mfunc上运行线性扫描。
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RISCv64LinearScan ls_alloc(mfunc.get());
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bool success = ls_alloc.run();
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if (!success) {
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// 如果线性扫描最终失败,则调用基本块分配器作为终极后备
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std::cerr << "Info: Linear Scan failed. Switching to Basic Block Allocator as final fallback.\n";
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// 注意:我们需要在一个“干净”的MachineFunction上运行。
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// 最安全的方式是重新运行指令选择。
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RISCv64ISel isel_fallback;
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mfunc = isel_fallback.runOnFunction(func);
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EliminateFrameIndicesPass efi_pass_fallback;
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efi_pass_fallback.runOnMachineFunction(mfunc.get());
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if (DEBUG) {
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std::cerr << "====== stack info after reg alloc ======\n";
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}
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RISCv64BasicBlockAlloc bb_alloc(mfunc.get());
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bb_alloc.run();
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}
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} else {
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// 图着色成功完成
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if (DEBUG) std::cerr << "Graph Coloring allocation completed successfully.\n";
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// future.get()会重新抛出在线程中发生的任何异常
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future.get();
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}
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if (DEBUG) {
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std::cerr << "====== stack info after reg alloc ======\n";
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@@ -410,7 +323,6 @@ std::string RISCv64CodeGen::function_gen(Function* func) {
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printer.run(ss);
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return ss.str();
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}
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}
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} // namespace sysy
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@@ -643,31 +643,31 @@ void RISCv64LinearScan::applyAllocation() {
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}
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}
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void getInstrUseDef(const MachineInstr* instr, std::set<unsigned>& use, std::set<unsigned>& def) {
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auto opcode = instr->getOpcode();
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const auto& operands = instr->getOperands();
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// void getInstrUseDef(const MachineInstr* instr, std::set<unsigned>& use, std::set<unsigned>& def) {
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// auto opcode = instr->getOpcode();
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// const auto& operands = instr->getOperands();
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auto get_vreg_id_if_virtual = [&](const MachineOperand* op, std::set<unsigned>& s) {
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if (op->getKind() == MachineOperand::KIND_REG) {
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auto reg_op = static_cast<const RegOperand*>(op);
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if (reg_op->isVirtual()) s.insert(reg_op->getVRegNum());
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} else if (op->getKind() == MachineOperand::KIND_MEM) {
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auto mem_op = static_cast<const MemOperand*>(op);
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auto reg_op = mem_op->getBase();
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if (reg_op->isVirtual()) s.insert(reg_op->getVRegNum());
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}
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};
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// auto get_vreg_id_if_virtual = [&](const MachineOperand* op, std::set<unsigned>& s) {
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// if (op->getKind() == MachineOperand::KIND_REG) {
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// auto reg_op = static_cast<const RegOperand*>(op);
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// if (reg_op->isVirtual()) s.insert(reg_op->getVRegNum());
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// } else if (op->getKind() == MachineOperand::KIND_MEM) {
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// auto mem_op = static_cast<const MemOperand*>(op);
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// auto reg_op = mem_op->getBase();
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// if (reg_op->isVirtual()) s.insert(reg_op->getVRegNum());
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// }
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// };
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if (op_info.count(opcode)) {
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const auto& info = op_info.at(opcode);
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for (int idx : info.first) if (idx < operands.size()) get_vreg_id_if_virtual(operands[idx].get(), def);
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for (int idx : info.second) if (idx < operands.size()) get_vreg_id_if_virtual(operands[idx].get(), use);
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for (const auto& op : operands) if (op->getKind() == MachineOperand::KIND_MEM) get_vreg_id_if_virtual(op.get(), use);
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} else if (opcode == RVOpcodes::CALL) {
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if (!operands.empty() && operands[0]->getKind() == MachineOperand::KIND_REG) get_vreg_id_if_virtual(operands[0].get(), def);
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for (size_t i = 1; i < operands.size(); ++i) if (operands[i]->getKind() == MachineOperand::KIND_REG) get_vreg_id_if_virtual(operands[i].get(), use);
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}
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}
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// if (op_info.count(opcode)) {
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// const auto& info = op_info.at(opcode);
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// for (int idx : info.first) if (idx < operands.size()) get_vreg_id_if_virtual(operands[idx].get(), def);
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// for (int idx : info.second) if (idx < operands.size()) get_vreg_id_if_virtual(operands[idx].get(), use);
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// for (const auto& op : operands) if (op->getKind() == MachineOperand::KIND_MEM) get_vreg_id_if_virtual(op.get(), use);
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// } else if (opcode == RVOpcodes::CALL) {
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// if (!operands.empty() && operands[0]->getKind() == MachineOperand::KIND_REG) get_vreg_id_if_virtual(operands[0].get(), def);
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// for (size_t i = 1; i < operands.size(); ++i) if (operands[i]->getKind() == MachineOperand::KIND_REG) get_vreg_id_if_virtual(operands[i].get(), use);
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// }
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// }
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bool RISCv64LinearScan::isFPVReg(unsigned vreg) const {
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return vreg_type_map.count(vreg) && vreg_type_map.at(vreg)->isFloat();
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@@ -45,7 +45,7 @@ RISCv64RegAlloc::RISCv64RegAlloc(MachineFunction* mfunc)
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}
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// 主入口: 迭代运行分配算法直到无溢出
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void RISCv64RegAlloc::run() {
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bool RISCv64RegAlloc::run() {
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if (DEBUG) std::cerr << "===== LLIR Before Running Graph Coloring Register Allocation " << MFunc->getName() << " =====\n";
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std::stringstream ss_before_reg_alloc;
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if (DEBUG) {
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@@ -108,6 +108,7 @@ void RISCv64RegAlloc::run() {
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MFunc->getFrameInfo().vreg_to_preg_map = this->color_map;
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collectUsedCalleeSavedRegs();
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if (DEBUG) std::cerr << "===== Finished Graph Coloring Register Allocation =====\n\n";
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return true;
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}
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// 单次分配的核心流程
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@@ -20,7 +20,7 @@ public:
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RISCv64RegAlloc(MachineFunction* mfunc);
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// 模块主入口
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void run();
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bool run();
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private:
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// 类型定义,与Python版本对应
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Reference in New Issue
Block a user