[backend]重构了后端
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Lixuanwang
246
src/RISCv64AsmPrinter.cpp
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246
src/RISCv64AsmPrinter.cpp
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#include "RISCv64AsmPrinter.h"
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#include <stdexcept>
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namespace sysy {
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void RISCv64AsmPrinter::runOnMachineFunction(MachineFunction* mfunc, std::ostream& os) {
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OS = &os;
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// 打印函数声明和全局符号
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*OS << ".text\n";
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*OS << ".globl " << mfunc->getName() << "\n";
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*OS << mfunc->getName() << ":\n";
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// 打印函数序言
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printPrologue(mfunc);
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// 遍历并打印所有基本块
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for (auto& mbb : mfunc->getBlocks()) {
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printBasicBlock(mbb.get());
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}
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}
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void RISCv64AsmPrinter::printPrologue(MachineFunction* mfunc) {
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int stack_size = mfunc->getFrameInfo().frame_size;
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// 确保栈大小是16字节对齐
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int aligned_stack_size = (stack_size + 15) & ~15;
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if (aligned_stack_size > 0) {
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*OS << " addi sp, sp, -" << aligned_stack_size << "\n";
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// RV64中ra和s0都是8字节
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*OS << " sd ra, " << (aligned_stack_size - 8) << "(sp)\n";
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*OS << " sd s0, " << (aligned_stack_size - 16) << "(sp)\n";
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*OS << " mv s0, sp\n";
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}
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}
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void RISCv64AsmPrinter::printEpilogue(MachineFunction* mfunc) {
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int stack_size = mfunc->getFrameInfo().frame_size;
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int aligned_stack_size = (stack_size + 15) & ~15;
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if (aligned_stack_size > 0) {
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*OS << " ld ra, " << (aligned_stack_size - 8) << "(sp)\n";
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*OS << " ld s0, " << (aligned_stack_size - 16) << "(sp)\n";
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*OS << " addi sp, sp, " << aligned_stack_size << "\n";
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}
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}
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void RISCv64AsmPrinter::printBasicBlock(MachineBasicBlock* mbb) {
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// 打印基本块标签
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if (!mbb->getName().empty()) {
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*OS << mbb->getName() << ":\n";
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}
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// 打印指令
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for (auto& instr : mbb->getInstructions()) {
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printInstruction(instr.get(), mbb);
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}
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}
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void RISCv64AsmPrinter::printInstruction(MachineInstr* instr, MachineBasicBlock* parent_bb) {
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*OS << " "; // 指令缩进
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auto opcode = instr->getOpcode();
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// RET指令需要特殊处理，在打印ret之前先打印函数尾声
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if (opcode == RVOpcodes::RET) {
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printEpilogue(parent_bb->getParent());
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}
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// 使用switch将Opcode转换为汇编助记符
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switch (opcode) {
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// Arithmatic
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case RVOpcodes::ADD: *OS << "add "; break;
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case RVOpcodes::ADDI: *OS << "addi "; break;
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case RVOpcodes::ADDW: *OS << "addw "; break;
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case RVOpcodes::ADDIW: *OS << "addiw "; break;
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case RVOpcodes::SUB: *OS << "sub "; break;
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case RVOpcodes::SUBW: *OS << "subw "; break;
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case RVOpcodes::MUL: *OS << "mul "; break;
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case RVOpcodes::MULW: *OS << "mulw "; break;
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case RVOpcodes::DIV: *OS << "div "; break;
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case RVOpcodes::DIVW: *OS << "divw "; break;
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case RVOpcodes::REM: *OS << "rem "; break;
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case RVOpcodes::REMW: *OS << "remw "; break;
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// Logical
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case RVOpcodes::XOR: *OS << "xor "; break;
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case RVOpcodes::XORI: *OS << "xori "; break;
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case RVOpcodes::OR: *OS << "or "; break;
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case RVOpcodes::ORI: *OS << "ori "; break;
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case RVOpcodes::AND: *OS << "and "; break;
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case RVOpcodes::ANDI: *OS << "andi "; break;
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// Shift
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case RVOpcodes::SLL: *OS << "sll "; break;
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case RVOpcodes::SLLI: *OS << "slli "; break;
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case RVOpcodes::SLLW: *OS << "sllw "; break;
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case RVOpcodes::SLLIW: *OS << "slliw "; break;
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case RVOpcodes::SRL: *OS << "srl "; break;
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case RVOpcodes::SRLI: *OS << "srli "; break;
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case RVOpcodes::SRLW: *OS << "srlw "; break;
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case RVOpcodes::SRLIW: *OS << "srliw "; break;
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case RVOpcodes::SRA: *OS << "sra "; break;
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case RVOpcodes::SRAI: *OS << "srai "; break;
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case RVOpcodes::SRAW: *OS << "sraw "; break;
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case RVOpcodes::SRAIW: *OS << "sraiw "; break;
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// Compare
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case RVOpcodes::SLT: *OS << "slt "; break;
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case RVOpcodes::SLTI: *OS << "slti "; break;
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case RVOpcodes::SLTU: *OS << "sltu "; break;
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case RVOpcodes::SLTIU: *OS << "sltiu "; break;
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// Memory
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case RVOpcodes::LW: *OS << "lw "; break;
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case RVOpcodes::LH: *OS << "lh "; break;
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case RVOpcodes::LB: *OS << "lb "; break;
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case RVOpcodes::LWU: *OS << "lwu "; break;
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case RVOpcodes::LHU: *OS << "lhu "; break;
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case RVOpcodes::LBU: *OS << "lbu "; break;
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case RVOpcodes::SW: *OS << "sw "; break;
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case RVOpcodes::SH: *OS << "sh "; break;
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case RVOpcodes::SB: *OS << "sb "; break;
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case RVOpcodes::LD: *OS << "ld "; break;
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case RVOpcodes::SD: *OS << "sd "; break;
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// Control Flow
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case RVOpcodes::J: *OS << "j "; break;
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case RVOpcodes::JAL: *OS << "jal "; break;
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case RVOpcodes::JALR: *OS << "jalr "; break;
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case RVOpcodes::RET: *OS << "ret"; break;
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case RVOpcodes::BEQ: *OS << "beq "; break;
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case RVOpcodes::BNE: *OS << "bne "; break;
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case RVOpcodes::BLT: *OS << "blt "; break;
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case RVOpcodes::BGE: *OS << "bge "; break;
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case RVOpcodes::BLTU: *OS << "bltu "; break;
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case RVOpcodes::BGEU: *OS << "bgeu "; break;
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// Pseudo-Instructions
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case RVOpcodes::LI: *OS << "li "; break;
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case RVOpcodes::LA: *OS << "la "; break;
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case RVOpcodes::MV: *OS << "mv "; break;
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case RVOpcodes::NEG: *OS << "neg "; break;
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case RVOpcodes::NEGW: *OS << "negw "; break;
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case RVOpcodes::SEQZ: *OS << "seqz "; break;
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case RVOpcodes::SNEZ: *OS << "snez "; break;
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// Call
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case RVOpcodes::CALL: *OS << "call "; break;
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// Special
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case RVOpcodes::LABEL:
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*OS << "\b\b\b\b";
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printOperand(instr->getOperands()[0].get());
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*OS << ":";
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break;
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default:
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throw std::runtime_error("Unknown opcode in AsmPrinter");
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}
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// 打印操作数
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const auto& operands = instr->getOperands();
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for (size_t i = 0; i < operands.size(); ++i) {
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// 对于LW/SW, 操作数格式是 rd, offset(rs1)
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if (opcode == RVOpcodes::LW || opcode == RVOpcodes::SW || opcode == RVOpcodes::LD || opcode == RVOpcodes::SD) {
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printOperand(operands[0].get());
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*OS << ", ";
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printOperand(operands[1].get());
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break; // LW/SW只有两个操作数部分
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}
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printOperand(operands[i].get());
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if (i < operands.size() - 1) {
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*OS << ", ";
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}
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}
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*OS << "\n";
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}
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void RISCv64AsmPrinter::printOperand(MachineOperand* op) {
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if (!op) return;
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switch(op->getKind()) {
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case MachineOperand::KIND_REG: {
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auto reg_op = static_cast<RegOperand*>(op);
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if (reg_op->isVirtual()) {
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// 在这个阶段不应该再有虚拟寄存器了
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*OS << "%vreg" << reg_op->getVRegNum();
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} else {
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*OS << regToString(reg_op->getPReg());
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}
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break;
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}
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case MachineOperand::KIND_IMM: {
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*OS << static_cast<ImmOperand*>(op)->getValue();
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break;
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}
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case MachineOperand::KIND_LABEL: {
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*OS << static_cast<LabelOperand*>(op)->getName();
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break;
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}
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case MachineOperand::KIND_MEM: {
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auto mem_op = static_cast<MemOperand*>(op);
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printOperand(mem_op->getOffset());
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*OS << "(";
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printOperand(mem_op->getBase());
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*OS << ")";
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break;
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}
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}
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}
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// 物理寄存器到字符串的转换 (从原RISCv64Backend.cpp迁移)
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std::string RISCv64AsmPrinter::regToString(PhysicalReg reg) {
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switch (reg) {
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case PhysicalReg::ZERO: return "x0";
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case PhysicalReg::RA: return "ra";
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case PhysicalReg::SP: return "sp";
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case PhysicalReg::GP: return "gp";
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case PhysicalReg::TP: return "tp";
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case PhysicalReg::T0: return "t0";
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case PhysicalReg::T1: return "t1";
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case PhysicalReg::T2: return "t2";
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case PhysicalReg::S0: return "s0";
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case PhysicalReg::S1: return "s1";
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case PhysicalReg::A0: return "a0";
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case PhysicalReg::A1: return "a1";
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case PhysicalReg::A2: return "a2";
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case PhysicalReg::A3: return "a3";
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case PhysicalReg::A4: return "a4";
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case PhysicalReg::A5: return "a5";
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case PhysicalReg::A6: return "a6";
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case PhysicalReg::A7: return "a7";
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case PhysicalReg::S2: return "s2";
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case PhysicalReg::S3: return "s3";
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case PhysicalReg::S4: return "s4";
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case PhysicalReg::S5: return "s5";
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case PhysicalReg::S6: return "s6";
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case PhysicalReg::S7: return "s7";
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case PhysicalReg::S8: return "s8";
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case PhysicalReg::S9: return "s9";
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case PhysicalReg::S10: return "s10";
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case PhysicalReg::S11: return "s11";
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case PhysicalReg::T3: return "t3";
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case PhysicalReg::T4: return "t4";
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case PhysicalReg::T5: return "t5";
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case PhysicalReg::T6: return "t6";
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default: return "UNKNOWN_REG";
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}
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}
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} // namespace sysy
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