[backend-llir]引入了LLIR定义

src/RISCv64Backend.cpp

@@ -1,4 +1,5 @@
 #include "RISCv64Backend.h"
+#include "RISCv64LLIR.h"
 #include <sstream>
 #include <algorithm>
 #include <stdexcept>

src/include/RISCv64LLIR.h

@@ -0,0 +1,229 @@
+#ifndef RISCV64_LLIR_H
+#define RISCV64_LLIR_H
+
+#include <string>
+#include <vector>
+#include <memory>
+#include <cstdint>
+#include <map>
+
+namespace sysy {
+
+// 物理寄存器定义 (从 RISCv64Backend.h 移至此)
+enum class PhysicalReg {
+    ZERO, RA, SP, GP, TP, T0, T1, T2, S0, S1, A0, A1, A2, A3, A4, A5, A6, A7, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, T3, T4, T5, T6,
+    F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15,F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31
+};
+
+
+// RISC-V 指令操作码枚举
+enum class RVOpcodes {
+    // 算术指令
+    ADD, ADDI, ADDW, ADDIW,
+    SUB, SUBW,
+    MUL, MULW,
+    DIV, DIVW,
+    REM, REMW,
+
+    // 逻辑指令
+    XOR, XORI,
+    OR, ORI,
+    AND, ANDI,
+    
+    // 移位指令
+    SLL, SLLI, SLLW, SLLIW,
+    SRL, SRLI, SRLW, SRLIW,
+    SRA, SRAI, SRAW, SRAIW,
+
+    // 比较指令
+    SLT, SLTI, SLTU, SLTIU,
+    
+    // 内存访问指令
+    LW, LH, LB, LWU, LHU, LBU,
+    SW, SH, SB,
+    LD, SD, // 64位
+    
+    // 控制流指令
+    J, JAL, JALR, RET, // RET 是 JALR x0, 0(ra) 的伪指令
+    BEQ, BNE, BLT, BGE, BLTU, BGEU,
+    
+    // 伪指令 (方便指令选择)
+    LI,   // Load Immediate
+    LA,   // Load Address
+    MV,   // Move register
+    NEG,  // Negate
+    NEGW, // Negate Word
+    SEQZ, // Set if Equal to Zero
+    SNEZ, // Set if Not Equal to Zero
+    
+    // 函数调用
+    CALL,
+
+    // 特殊标记，非指令
+    LABEL, // 用于表示一个标签位置
+};
+
+class MachineOperand;
+class RegOperand;
+class ImmOperand;
+class LabelOperand;
+class MemOperand;
+class MachineInstr;
+class MachineBasicBlock;
+class MachineFunction;
+
+// --- 操作数定义 ---
+
+// 操作数基类
+class MachineOperand {
+public:
+    enum OperandKind {
+        KIND_REG,
+        KIND_IMM,
+        KIND_LABEL,
+        KIND_MEM
+    };
+
+    MachineOperand(OperandKind kind) : kind(kind) {}
+    virtual ~MachineOperand() = default;
+    OperandKind getKind() const { return kind; }
+
+private:
+    OperandKind kind;
+};
+
+// 寄存器操作数
+class RegOperand : public MachineOperand {
+public:
+    // 构造虚拟寄存器
+    RegOperand(unsigned vreg_num) 
+        : MachineOperand(KIND_REG), vreg_num(vreg_num), is_virtual(true) {}
+
+    // 构造物理寄存器
+    RegOperand(PhysicalReg preg)
+        : MachineOperand(KIND_REG), preg(preg), is_virtual(false) {}
+
+    bool isVirtual() const { return is_virtual; }
+    unsigned getVRegNum() const { return vreg_num; }
+    PhysicalReg getPReg() const { return preg; }
+
+    void setPReg(PhysicalReg new_preg) {
+        preg = new_preg;
+        is_virtual = false;
+    }
+
+private:
+    unsigned vreg_num = 0;
+    PhysicalReg preg = PhysicalReg::ZERO;
+    bool is_virtual;
+};
+
+// 立即数操作数
+class ImmOperand : public MachineOperand {
+public:
+    ImmOperand(int64_t value) 
+        : MachineOperand(KIND_IMM), value(value) {}
+
+    int64_t getValue() const { return value; }
+private:
+    int64_t value;
+};
+
+// 标签操作数
+class LabelOperand : public MachineOperand {
+public:
+    LabelOperand(const std::string& name) 
+        : MachineOperand(KIND_LABEL), name(name) {}
+    
+    const std::string& getName() const { return name; }
+private:
+    std::string name;
+};
+
+// 内存操作数, 表示 offset(base_reg)
+class MemOperand : public MachineOperand {
+public:
+    MemOperand(std::unique_ptr<RegOperand> base, std::unique_ptr<ImmOperand> offset)
+        : MachineOperand(KIND_MEM), base(std::move(base)), offset(std::move(offset)) {}
+
+    RegOperand* getBase() const { return base.get(); }
+    ImmOperand* getOffset() const { return offset.get(); }
+
+private:
+    std::unique_ptr<RegOperand> base;
+    std::unique_ptr<ImmOperand> offset;
+};
+
+
+// --- 组织结构定义 ---
+
+// 机器指令
+class MachineInstr {
+public:
+    MachineInstr(RVOpcodes opcode) : opcode(opcode) {}
+
+    RVOpcodes getOpcode() const { return opcode; }
+    const std::vector<std::unique_ptr<MachineOperand>>& getOperands() const { return operands; }
+    
+    void addOperand(std::unique_ptr<MachineOperand> operand) {
+        operands.push_back(std::move(operand));
+    }
+
+private:
+    RVOpcodes opcode;
+    std::vector<std::unique_ptr<MachineOperand>> operands;
+};
+
+// 机器基本块
+class MachineBasicBlock {
+public:
+    MachineBasicBlock(const std::string& name, MachineFunction* parent) 
+        : name(name), parent(parent) {}
+
+    const std::string& getName() const { return name; }
+    const std::vector<std::unique_ptr<MachineInstr>>& getInstructions() const { return instructions; }
+    MachineFunction* getParent() const { return parent; }
+
+    void addInstruction(std::unique_ptr<MachineInstr> instr) {
+        instructions.push_back(std::move(instr));
+    }
+    
+    std::vector<MachineBasicBlock*> successors;
+    std::vector<MachineBasicBlock*> predecessors;
+
+private:
+    std::string name;
+    std::vector<std::unique_ptr<MachineInstr>> instructions;
+    MachineFunction* parent; // 指向所属函数
+};
+
+// 栈帧信息
+struct StackFrameInfo {
+    int frame_size = 0;
+    std::map<int, int> spill_slots; // <虚拟寄存器号, 栈偏移>
+    // ... 未来可以添加更多信息
+};
+
+// 机器函数
+class MachineFunction {
+public:
+    MachineFunction(const std::string& name) : name(name) {}
+
+    const std::string& getName() const { return name; }
+    const std::vector<std::unique_ptr<MachineBasicBlock>>& getBlocks() const { return blocks; }
+    StackFrameInfo& getFrameInfo() { return frame_info; }
+
+    void addBlock(std::unique_ptr<MachineBasicBlock> block) {
+        blocks.push_back(std::move(block));
+    }
+
+private:
+    std::string name;
+    std::vector<std::unique_ptr<MachineBasicBlock>> blocks;
+    StackFrameInfo frame_info;
+};
+
+
+} // namespace sysy
+
+#endif // RISCV64_LLIR_H